US20090267687A1

US20090267687A1 - Chopper-stabilized amplifier and magnetic field sensor

Info

Publication number: US20090267687A1
Application number: US12/111,554
Authority: US
Inventors: Hernan D. Romero; Gerardo Monreal
Original assignee: Individual
Current assignee: Allegro Microsystems Inc
Priority date: 2008-04-29
Filing date: 2008-04-29
Publication date: 2009-10-29
Anticipated expiration: 2028-04-29
Also published as: US7605647B1; WO2009134735A1

Abstract

A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

Not Applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

Not Applicable.

FIELD OF THE INVENTION

This invention relates generally to chopper-stabilized amplifiers and to magnetic field sensors that use chopper-stabilized amplifiers and, more particularly, to a chopper-stabilized amplifier that can reduce an offset component of an input signal and provide improved common mode rejection while supporting a relatively high switching frequency, and to a magnetic field sensor that uses such a type of chopper-stabilized amplifier.

BACKGROUND OF THE INVENTION

As is known, some types of analog electronic signals include both a signal component and an offset component. The offset component is usually an undesirable DC component, while the signal component can be an AC component that usually carries information used by an electronic system that receives the electronic signal. It will be recognized that, if such an electronic signal is received by and amplified by an amplifier, the amplified offset component might saturate the amplifier or cause other undesirable effects upon the electronic system receiving the electronic signal. Also, an amplifier itself has an input offset voltage, which, if greatly amplified, can saturate the amplifier or another amplifier or cause undesirable effects upon the system.
Chopper-stabilized amplifiers are used to reduce the effects of offset components of signals. Some chopper-stabilized amplifiers receive an input signal having a signal component and an offset component and operate to reduce the offset component relative to the signal component. Chopper-stabilized amplifiers having a variety of configurations are known.
Magnetic field sensors are used in a wide variety of applications. As one example, magnetic field sensors are widely used in automobiles for mechanical position sensing. For example, one type of magnetic field sensor is used as a rotation sensor in antilock brake systems.
Some types of magnetic field sensors use a Hall effect element, sometimes referred to as a Hall plate. A Hall effect element can generate a signal with both a signal component and an offset component, which can be due to resistance gradients, geometrical asymmetries, and piezoresistive effects. The magnitude and polarity of the offset component (or offset voltage) can be related to stresses in a semiconductor substrate supporting the Hall effect element, which stresses tend to vary with mechanical pressure and with temperature. Various techniques have been used to address and cancel the Hall effect element offset voltage, including use of a chopper-stabilized amplifier in combination with a current spinning technique, which is described more fully below.
One type of Hall effect sensor includes a switched Hall element, a chopper-stabilized amplifier, and a low pass filter. The switched Hall element, sometimes referred to as a spinning Hall element, includes both a Hall element having (typically) four contacts and a modulation circuit to periodically connect a supply voltage and an amplifier input to one pair of contacts or the other. Quadrature phases of operation are provided by complementary (180 degree out of phase) clock signals. Operation of a switched Hall element is described more fully below in conjunction with FIGS. 2-3C.
Use of a switched Hall element provides a way to discriminate (and relatively reduce) the Hall effect element offset voltage (referred to herein as an offset component) from the magnetically induced signal (referred to herein as a magnetic field signal component). In one type of modulation circuit used in a switched Halle element circuit, the modulation circuit modulates the magnetic signal component and the offset component remains substantially unchanged, i.e., un-modulated. In conjunction with this modulation circuit, a chopper-stabilized amplifier demodulates the magnetic signal component and modulates the offset component. The offset component, which, after the chopper-stabilized amplifier is an AC signal, is attenuated by a low pass filter to provide the magnetic field sensor output signal without an offset component. The technique effectively removes the Hall effect element offset voltage.
It will be appreciated that it is desirable to make a switching frequency used in the chopper-stabilized amplifier as high as possible. A higher switching frequency tends to result in an ability to use a low pass filter with a wider passband, which further tends to result in the magnetic field sensor having a faster response time.
It will also be understood that the magnitude of any ripple remaining on the magnetic field sensor output signal must be balanced with the sensor response time. As the low pass filter passband is reduced to reduce the ripple, the response time of the magnetic field sensor increases, which is undesirable.
Conventional chopper-stabilized amplifiers and magnetic field sensors using the chopper-stabilized amplifiers suffer from certain disadvantages. For example, some conventional chopper-stabilized amplifiers require a relatively low switching frequency, and therefore, as described above, a low pass filter with a relatively narrow passband and a resulting relatively slow response time. For another example, some conventional chopper-stabilized amplifiers suffer from having a relatively low common mode rejection and/or a relatively low rejection of the offset component.
It would be desirable to provide a chopper-stabilized amplifier that can accommodate a relatively high switching frequency, that has a relatively high rejection of a common mode signal, and that has a relatively high rejection of an offset component of an input signal.

SUMMARY OF THE INVENTION

In some embodiments, a magnetic field sensor includes a Hall element, a modulation circuit, a chopper-stabilized amplifier, and a filter, all coupled in series. The output signal from the Hall effect element can include a magnetic field signal component and an offset component. The modulation circuit is responsive to the output signal of the Hall element and operates to modulate only the magnetic field signal component of the output signal from the Hall element. The chopper-stabilized amplifier is responsive to the modulation circuit output signal and provides an amplifier output signal with a reduced offset component. The chopper-stabilized amplifier has particular characteristics such that the chopper-stabilized amplifier can accommodate a relatively high switching frequency, has a relatively high rejection of a common mode signal, and has a relatively high rejection of an offset component of an input signal.
In accordance with one aspect of the present invention, a chopper-stabilized amplifier includes first and second front-end amplifiers, each having a respective input node and a respective feedback node. The first front-end amplifier is configured to generate a first amplified output signal and the second front-end amplifier is configured to generate a second amplified output signal. The chopper-stabilized amplifier also includes a first switching network coupled to receive a binary clock signal having first and second periodic states, coupled to receive the first and second amplified output signals, and configured to generate first and second switched output signals. During the first state of the binary clock signal, the first switched output signal is related to the first amplified output signal and the second switched output signal is related to the second amplified output signal. During the second state of the binary clock signal, the first switched output signal is related to the second amplified output signal and the second switched output signal is related to the first amplified output signal. The chopper-stabilized amplifier also includes first and second back-end amplifiers. The first back-end amplifier is coupled to receive the first switched output signal and the second back-end amplifier is coupled to receive the second switched output signal. The first back-end amplifier is configured to generate a first back-end output signal and the second back-end amplifier is configured to generate a second back-end output signal. An output signal of the chopper-stabilized amplifier is a differential signal comprised of the first and second back-end output signals. The chopper-stabilized amplifier also includes at least one of a feedback circuit or a second switching network coupled to receive the first and second back-end output signals. The other one of the feedback circuit or the second switching network is configured to generate first and second switched feedback signals. The second switching network is coupled to receive the binary clock signal. During the first state of the binary clock signal, the first switched feedback signal is related to the first back-end output signal and the second switched feedback signal is related to the second back-end output signal. During the second state of the binary clock signal, the first switched feedback signal is related to the second back-end output signal and the second switched feedback signal is related to the first back-end output signal. The feedback node of the first front-end amplifier is coupled to receive the first switched feedback signal, and the feedback node of the second front-end amplifier is coupled to receive the second switched feedback signal.
In accordance with another aspect of the present invention, a magnetic field sensor includes a Hall effect element having two output nodes at which is provided a differential output signal that varies in response to a magnetic field. The Hall effect element differential output signal includes a magnetic field signal component and an offset component. The magnetic field sensor also includes a chopper-stabilized amplifier as described above. The input nodes of the first and second front-end amplifiers are coupled to the Hall effect element.
In some embodiments, the magnetic field sensor also includes a modulation circuit coupled between the Hall effect element and the chopper-stabilized amplifier and coupled to receive the binary clock signal. The modulation circuit is operable to modulate the magnetic field signal component to provide to the first and second front-end amplifiers a modulated signal having the modulated magnetic field signal component and having an un-modulated offset component.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the invention, as well as the invention itself may be more fully understood from the following detailed description of the drawings, in which:

FIG. 1 is a block diagram showing a magnetic field sensor, which includes a Hall effect element, a modulation circuit, a chopper-stabilized amplifier, and a filter;

FIG. 2 is a block diagram showing a switched Hall element having a Hall effect element and having a modulation circuit that can be used as the Hall effect element and the modulation circuit in the sensor of FIG. 1 to modulate an offset component;

FIG. 2A is a graph showing clock signals for the switched Hall element of FIG. 2;

FIG. 2B is a graph showing a modulated offset component provided by the switched Hall element of FIG. 2;

FIG. 2C is a graph showing an un-modulated magnetic field signal component provided by the switched Hall element of FIG. 2;

FIG. 3 is a block diagram showing a switched Hall element having a Hall effect element and having a modulation circuit that can be used as the Hall effect element and the modulation circuit in the sensor of FIG. 1 to modulate a magnetic field signal component;

FIG. 3A is a graph showing clock signals for the switched Hall element of FIG. 3;

FIG. 3B is a graph showing an un-modulated offset component provided by the switched Hall element of FIG. 3;

FIG. 3C is a graph showing a modulated magnetic field signal component provided by the switched Hall element of FIG. 3;

FIG. 4 is a graph showing four single-ended signals appearing at a point A of FIG. 1;

FIG. 4A is a graph showing a differential signal having a modulated magnetic field signal component and an un-modulated offset component appearing at a point B of FIG. 1;

FIG. 4B is a graph showing a differential signal having a demodulated magnetic field signal component and a modulated offset component appearing at a point C of FIG. 1;

FIG. 4C is a graph showing a filtered differential signal having a demodulated signal component and a filtered modulated offset component appearing at a point D of FIG. 1;

FIG. 5 is a block diagram showing a type of prior art chopper-stabilized amplifier;

FIG. 6 is a block diagram showing another type of prior art chopper-stabilized amplifier;

FIG. 7 is a block diagram showing a chopper-stabilized amplifier in accordance with the present invention, which can be used as the chopper-stabilized amplifier of FIG. 1;

FIG. 7A is a graph showing a differential signal having a modulated signal component and an un-modulated offset component appearing at a point E of FIG. 7;

FIG. 7B is a graph showing a differential signal having a modulated offset component and a demodulated signal component appearing at a point F of FIG. 7; and

FIG. 7C is a graph showing a differential signal having a band-limited modulated offset component and a demodulated signal component appearing at a point G of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, a magnetic field sensor 10 includes a Hall effect element 12 providing four couplings with associated signals 14 a-14 d to a modulation circuit 16. The modulation circuit 16 can be of a type described below in conjunction with FIGS. 3 and 3A. The modulation circuit provides a differential output signal 18 a, 18 b to a chopper-stabilized amplifier 20. The chopper-stabilized amplifier 20 provides a differential amplified signal 22 a, 22 b to a filter module 24. The filter module 24 provides a differential output signal 26 a, 26 b. In some alternate arrangements, the differential signals 22 a, 22 b and 26 a, 26 b can be single ended signals.
The magnetic field sensor 10 also includes a clock circuit 30 configured to provide a clock signal 32 and a complementary (i.e., inverted) clock signal 34 to both the modulation circuit 16 and to the chopper-stabilized amplifier 20. Therefore, switching function of the modulation circuit 16 is synchronous with function of the chopper-stabilized amplifier 20.
It will become apparent from discussion below that, even if the Hall effect element 12 generates a source signal having both a signal component and an offset component, the output signal 26 a, 26 b from the magnetic field sensor 10 has a predominant magnetic field signal component and a comparatively reduced offset component.
Referring now to FIG. 2, a switched Hall element 50 of the type that modulates the Hall offset component includes a Hall element (or Hall plate) 52 and a modulation circuit 54. The Hall element 52 includes four contacts 52 a, 52 b, 52 c, and 52 d, each coupled to a first terminal of a respective switch 56 a, 56 b, 56 c, and 56d, as shown. Second terminals of switches 56 b and 56 c are coupled to provide a positive node of a switched Hall output signal, here labeled Vo+, and second terminals of switches 56 a and 56d are coupled to provide a negative node of the switched Hall output signal, here labeled Vo−.
Additional switches 60 a, 60 b, 60 c, and 60 d are arranged to selectively couple the Hall contacts 52 a, 52 b, 52 c, 52 d to the supply voltage, Vs, and ground. More particularly, switches 56 b, 56 d, 60 a, and 60 c are controlled by a clock signal, CLK, and switches 56 a, 56 c, 60 b, and 60 d are controlled by a complementary clock signal, CLK/, as shown. The clock signals CLK and CLK/have two states or phases, a Φ_0° state and a Φ_90° go state, as shown in FIG. 2A.
In operation, during phase Φ_0° current flows from the terminal 52 a to the terminal 52 c and the switched Hall output signal, Vo, is equal to V_H+V_op, where V_opis the Hall element offset voltage or Hall offset component and V_His the magnetic filed signal component. During the phase Φ_90°, current flows from the terminal 52 b to the terminal 52 d and the switched Hall output signal, Vo, is equal to V_H−V_op. Thus, the modulation circuit 54 modulates the Hall offset component, V_op, which is shown in FIG. 2B for a zero Gauss magnetic field. The magnetic field signal component, V_H, remains substantially invariant, as shown in FIG. 2C.
Referring now to FIG. 3, an alternative switched Hall element 70 of the type that modulates the magnetic signal component includes a Hall element 72 and a modulation circuit 74. The Hall effect element 72 is the same as the Hall effect element 52 of FIG. 2 and includes four contacts 72 a, 72 b, 72 c, and 72 d, each coupled to a first terminal of a respective switch 76 a, 76 b, 76 c, and 76 d. Second terminals of switches 76 a and 76 b are coupled to provide a positive node of a switched Hall output signal, here labeled Vo+, and second terminals of switches 56 c and 56 d are coupled to provide a negative node of the switched Hall output signal, here labeled Vo−. Thus, a comparison of FIGS. 2 and 3 reveals that the output contacts of the Hall element are interchanged during the Φ_90° phase.
Additional switches 80 a, 80 b, 80 c, and 80 d are arranged to selectively couple the Hall contacts 72 a, 72 b, 72 c, and 72 d to the supply voltage Vs and ground. Switches 76 b, 76 d , 80 a, and 80 c are controlled by clock signal, CLK, and switches 76 a, 76 c, 80 b, and 80 d are controlled by a complementary clock signal, CLK/, as shown. Clock signals, CLK and CLK/, are identical to like signals in FIG. 2 and thus have two states or phases, Φ_0° and Φ_90° as shown.
In operation, during phase Φ_0°, current flows from the terminal 72 a to the terminal 72 c, and the switched Hall output signal, Vo, is equal to V_H+V_op. During phase Φ_90°, current flows from the terminal 72 b to the terminal 72 d, and the switched Hall output signal, Vo, is equal to −V_H+V_op. Thus, the modulation circuit 74 modulates the magnetic signal component to provide a modulated magnetic signal component, V_H, which is shown in FIG. 3C for a zero Gauss magnetic field. The offset component, V_opremains substantially invariant as is shown in FIG. 3B.
It will be understood from discussion below in conjunction with FIGS. 7-7C that in a preferred embodiment, the modulation circuit 16 of FIG. 1 is of a type described above in conjunction with FIGS. 3-3C, rather than of a type described above in conjunction with FIGS. 2-2C. In other words, in a preferred embodiment, the chopper-stabilized amplifier 20 of FIG. 1 receives the differential signal 18 a, 18 b having a modulated signal component and an un-modulated offset component.
Referring now to FIGS. 4-4C, graphs 100, 120, 140, 160 are indicative of signals appearing at points A, B, C, and D, respectively, of FIG. 1. The graphs 100, 120, 140, 160 each have a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of volts.
The graph 100 includes four signals 102, 104, 106, 108, which are indicative of signals 14 a, 14 b, 14 c, 14 d, respectively, i.e., the signal A, shown in FIG. 1, and which are also indicative of the four signals received by the switches 76 a, 76 b, 76 c, 76 d of FIG. 3. In any half cycle of the clock signal, CLK, of FIGS. 1 and 3, two of the signals (102 and 108 or 104 and 106) are present at the output of the modulation circuit as the signals V_o+ and V_o− of FIG. 3, which are the signals 18 a, 18 b of FIG. 1, i.e., the signal B of FIG. 1. Differences between the signals V_o+ and V_o− of FIG. 3 and between the signals 18 a, 18 b of FIG. 1 are differential signals.
During a phase, Ph 0, signals 104 and 106 differ by an amount 110. During a phase Ph 90, signals 108 and 102 differ by an amount 112, which is opposite in polarity from the difference of the signals 104 and 106. A signal 122 of FIG. 4A is representative of the above-described difference of signals, is also representative of a sum of the signals V_opand V_Hof FIGS. 3B and 3C, and is also representative of a differential signal B of FIG. 1. The AC part of the signal 122 is representative of a modulated magnetic field signal component of the signal 122. A line 124 is representative of a DC part of the signal 122, i.e., an offset component of the signal 122, which is an un-modulated offset component.
A signal 144 is representative of the differential signal 22 a, 22 b of FIG. 1, i.e., the signal C of FIG. 1. The signal 144 can have rounded edges due to band limiting effects of the chopper-stabilized amplifier 20 of FIG. 1, depending upon a frequency of the clock signal 32, 34 of FIG. 1. The signal 144 is larger than the signal 122 due to amplification provided by the chopper-stabilized amplifier 20 of FIG. 1. The signal 144 has an AC part representative the offset component 124 of FIG. 4A, and is a modulated offset component generated by way of the chopper-stabilized amplifier 20 of FIG. 1. A line 142 is representative of a DC part of the signal 144, and is a demodulated version of the AC part of the modulated magnetic field signal 122.
It should be recognized that the desired signal is the DC part of the signal 144 represented by the line 142 and the undesired signal is the AC part of the signal 144. It should also be understood that the DC part of the signal 144 represented by the line 142 is only a DC signal when the magnetic field sensor 10 of FIG. 1 experiences a static magnetic field. In other words, if the magnetic field sensor 10 of FIG. 1 experiences a varying magnetic field, then the part of the signal 144 represented by the line 142 will have a varying (AC) part.
A curve 164 is representative of the differential signal 26 a, 26 b of FIG. 1, i.e., the signal D of FIG. 1. The curve 164 is a filtered version of the curve 144. It should be recognized that filtering the signal 144 to achieve the signal 164 removes much of the AC part of the signal 144, leaving a signal more closely representative of the desired DC part of the signal 144, of which lines 142 and 162 are representative. However, as described above, it should also be understood that the DC part of the signal 164 represented by the line 162 is only a DC signal when the magnetic field sensor 10 of FIG. 1 experiences a static magnetic field.
Referring now to FIG. 5, a prior art chopper-stabilized amplifier 180 includes a first switching network 184 for receiving a differential signal 182 a, 182 b. The first switching network 184 provides a first switched signal 186 a to a first front-end amplifier 188 and a second switched signal 186 b to a second front-end amplifier 196. Taken together, the signals 186 a, 186 b are a switched differential signal. The first front-end amplifier 188 provides a differential signal 190 a, 190 b to a first back-end amplifier 192 and the second front-end amplifier 196 provides a differential signal 198 a, 198 b to a second back-end amplifier 200. The first back-end amplifier 192 provides a first back-end output signal 194 a to a second switching network 206 and the second back-end amplifier 200 provides a second back-end output signal 194 b to the second switching network 206. The second switching network provides a differential output signal 208 a, 208 b from the chopper-stabilized amplifier 180.
The first back-end amplifier 192 also provides the first back-end output signal 194 a to a feedback network 202 and the second back-end amplifier 200 also provides the second back-end output signal 194 b to the feedback network 202. The feedback network 202 provides a first feedback signal 204 a to a feedback node of the first front-end amplifier 188 and the feedback network also provides a second feedback signal 204 b to a feedback node of the second front-end amplifier 196. The first and second switching networks 184, 206, respectively are coupled to receive a clock signal 210 a and an inverted clock signal 210 b.
One of ordinary skill in the art will be familiar with operation of the chopper-stabilized amplifier 180, thus, the operation will not be discussed herein in detail. However, it should be recognized that the chopper-stabilized amplifier 180 suffers from certain disadvantages.
The chopper-stabilized amplifier 180 is unable to support very high frequency of the clock signals 210 a, 210 b. This is partially because the second switching network 206 is after the back- end amplifiers 192, 200, which are generally band-limited when compared to the front- end amplifiers 188, 196. For example, in some arrangements, the first and second back- end amplifiers 192, 200 are Miller amplifiers, each having at least one respective pole in the frequency domain. As a result, the frequency of the clock signals 210 a, 210 b is generally limited to about twenty kilohertz.
Referring now to FIG. 6, another prior art chopper-stabilized amplifier 240 includes first and second switching networks 244, 262, respectively, for receiving a differential signal 242 a, 242 b. The first switching network 244 provides a switched differential signal 246 a, 246 b to a first front-end amplifier 248 and the second switching network 262 provides a switched differential signal 264 a, 264 b to a second front-end amplifier 266. The first front-end amplifier 248 provides a first differential amplified output signal 250 a, 250 b and the second front-end amplifier 266 provides a second differential amplified output signal 268 a, 268 b. The first differential amplified output signal 250 a, 250 b is received by a third switching network 252 and the second differential amplified output signal 268 a, 268 b is received by a fourth switching network 270. The third switching network 252 provides a differential signal 254 a, 254 b to a first back-end amplifier 256 and the fourth switching network 270 provides a differential signal 272 a, 272 b to a fourth back-end amplifier 274. The first back-end amplifier 256 provides a first back-end output signal 258 a and the second back-end amplifier 274 provides a second back-end output signal 258 b. The first and second back-end output signals 258 a, 258 b, respectively, together constitute a differential output signal from the chopper-stabilized amplifier 240.
A feedback circuit 276 receives the first and second back-end output signals 258 a, 258 b and provides a first feedback signal 278 a to the first switching network 244. The feedback circuit 276 also provides a second feedback signal 278 b to the second switching network 262. The first, second, third, and fourth switching networks 244, 262, 252, 270, respectively, are coupled to receive a clock signal 280 a and an inverted clock signal 280 b.
One of ordinary skill in the art will be familiar with operation of the chopper-stabilized amplifier 240, so the operation will not be discussed herein in detail. However, it should be recognized that the chopper-stabilized amplifier 240 suffers from certain disadvantages.
It will be recognized that the chopper-stabilized amplifier 240 can support higher clock frequencies than the chopper-stabilized amplifier 180 of FIG. 5. This is due in-part to the placement of the switching networks 244, 266,252, 270, which are before the band-limited back end amplifiers 256, 270.
However, the chopper-stabilized amplifier 240 is unable to provide as high a common mode rejection or as high a rejection of the above-described offset component as the chopper-stabilized amplifier 180 of FIG. 5. This is partially because the separate switching networks 244, 262 provide separate inputs to the first and second front-end amplifiers 248, 260, respectively: Unbalances within each front end amplifier will translate common mode signals into differential mode signals. Of particular concern, common mode interference having a frequency the same as the frequency of the clock signal 280 a, 280 b is translated into differential mode due to a finite common mode rejection between the first and second front end amplifiers 248, 266, which at the same time is down converted (to DC) by means of the third and fourth switching circuits 252, 270, respectively. Moreover, different common mode rejection provided by each individual front end amplifier 244, 266 can generate a difference on the generated differential signals 250 a, 250 b and 268 a, 268 b at the output of each front end amplifier 248, 262, yielding a differential signal at the very output 258 a, 258 b of the chopper-stabilized amplifier 240.
Referring now to FIG. 7, a chopper-stabilized amplifier 300 includes first and second front-end amplifiers, 306, 318, respectively, each having a respective input node 306 a, 318 a, and a respective feedback node 306 b, 318 b. The first front-end amplifier 306 is configured to generate a first amplified output signal 308 a, 308 b (which can be a differential signal) and the second front-end amplifier 318 is configured to generate a second amplified output signal 320 a, 320 b (which can be a differential signal).
The chopper-stabilized amplifier 300 also includes a first switching network 310 coupled to receive a binary clock signal 309a, 309b having first and second periodic states. The first switching network 310 is also coupled to receive the first and second amplified output signals 308 a, 308 b and 320 a, 320 b respectively. The first switching network 310 is configured to generate first and second switched output signals 310 a, 310 b and 322 a, 322 b, respectively, each of which can be differential signals.
During the first state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is related to the first amplified output signal 308 a, 308 b and the second switched output signal 322 a, 322 b is related to the second amplified output signal 320 a, 320 b. In some embodiments, during the first state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is equal to the first amplified output signal 308 a, 308 b and the second switched output signal 322 a, 322 b is equal to the second amplified output signal 320 a, 320 b. In some embodiments, during the first state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is linearly related to the first amplified output signal 308 a, 308 b and the second switched output signal 322 a, 322 b is linearly related to the second amplified output signal 320 a, 320 b.
During the second state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is related to the second amplified output signal 320 a, 320 b and the second switched output signal 322 a, 322 b is related to the first amplified output signal 308 a, 308 b. In some embodiments, during the second state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is equal to the second amplified output signal 320 a, 320 b and the second switched output signal 322 a, 322 b is equal to the first amplified output signal 308 a, 308 b. In some embodiments, during the second state of the binary clock signal 309 a, 309 b, the first switched output signal 310 a, 310 b is linearly related to the second amplified output signal 320 a, 320 b and the second switched output signal 322 a, 322 b is linearly related to the first amplified output signal 308 a, 308 b.
The chopper-stabilized amplifier 300 also includes first and second back- end amplifiers 314, 326, respectively. The first back-end amplifier 314 is coupled to receive the first switched output signal 310 a, 310 b and the second back-end amplifier 326 is coupled to receive the second switched output signal 322 a, 322 b. The first back-end amplifier 314 is configured to generate a first back-end output signal 316 a and the second back-end amplifier 326 is configured to generate a second back-end output signal 316 b. An output signal of the chopper-stabilized amplifier is a differential signal 316 a, 316 b comprised of the first and second back-end output signals 316 a, 316 b, respectively.
The chopper-stabilized amplifier 300 also includes a feedback circuit 328 coupled to receive the first and second back-end output signals 316 a, 316 b, respectively, and configured to generate first and second feedback signals 330 a, 330 b, respectively. The chopper-stabilized amplifier 300 also includes a second switching network 332 coupled to receive the binary clock signal 309 a, 309 b, coupled to receive the first and second feedback signals 330 a, 330 b, respectively, and configured to generate first and second switched feedback signals 332 a, 332 b, respectively.
During the first state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is related to the first feedback signal 330 a, which is related to the first back-end output signal 316 a, and the second switched feedback 332 b signal is related to the second feedback signal 330 b, which is related to the second back-end output signal 316 b. In some embodiments, during the first state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is equal to the first feedback signal 330 a and the second switched feedback 332 b signal is equal to the second feedback signal 330 b. In some embodiments, during the first state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is linearly related to the first feedback signal 330 a and the second switched feedback 332 b signal is linearly related to the second feedback signal 330 b.
During the second state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is related to the second feedback signal 330 b, which is related to the second back-end output signal 316 b, and the second switched feedback signal 332 b is related to the first feedback signal 330 a, which is related to the first back-end output signal 316 a. In some embodiments, during the second state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is equal to the second feedback signal 330 b and the second switched feedback signal 332 b is equal to the first feedback signal 330 a. In some embodiments, during the second state of the binary clock signals 309 a, 309 b, the first switched feedback signal 332 a is linearly related to the second feedback signal 330 b and the second switched feedback signal 332 b is linearly related to the first feedback signal 330 a.
It will be apparent that, in some embodiments, the feedback circuit 328 and the second switching network 332 can be swapped in position.
The feedback node 306 b of the first front-end amplifier 306 is coupled to receive the first switched feedback signal 332 a and the feedback node 318 b of the second front-end amplifier 318 is coupled to receive the second switched feedback signal 332 b.
In some embodiments, the feedback circuit 328 includes first, second, and third resistors, each having first and second respective nodes. The first node of the first resistor is coupled to receive the first back-end output signal 316 a. The first node of the second resistor is coupled to receive the second back-end output signal 316 b. The third resistor is coupled between the second nodes of the first and second resistors. The first feedback signal 330 a is generated at the second node of the first resistor and the second feedback signal 330 b is generated at the second node of the second resistor. In some embodiments, the third resistor comprises two series coupled resistors.
In some embodiments, the input nodes 308 a, 318 a of the first and second front-end amplifiers 308, 318, respectively, are coupled to receive a modulated differential input signal 302 a, 302 b. In some embodiments, the modulated differential input signal 302 a, 302 b includes a modulated signal component and an un-modulated offset component. In other arrangements, the modulated differential input signal 302 a, 302 b includes an un-modulated signal component and a modulated offset component. In some embodiments, the differential input signal 302 a, 302 b is unmodulated.
In some embodiments, the first and second amplified output signals 308 a, 308 b and 320 a, 320 b are differential signals and the first and second switched output signals 310 a, 310 b and 322 a, 322 b are differential signals. However, in other embodiments, the first and second amplified output signals 308 a, 308 b and 320 a, 320 b are single ended signals. Also, in other embodiments, the first and second switched output signals 310 a, 310 b and 322 a, 322 b are single ended signals.
Switches shown within the first switching network 310 and within the second switching network 332 can be a variety of types of switches, including, but not limited to, transistor switches, CMOS switches, and FET switches.
In operation, for embodiments in which the modulated differential input signal 302 a, 302 b includes a modulated signal component and an un-modulated offset component (see, e.g., FIG. 4A), it will be understood that the first and second back-end output signals 316 a, 316 b include a modulated offset component and an un-modulated signal component (see, e.g., FIG. 4B.) The unmodulated signal component is essentially a demodulated version of the modulated signal component received at the input to the chopper-stabilized amplifier 300.
In some embodiments, the first and second front- end amplifiers 306, 318 have a relatively larger gain-bandwidth product and the first and second back- end amplifiers 314, 318 have a relatively lower gain-bandwidth product. For example, in some embodiments, the first and second front- end amplifiers 306, 318 have a gain-bandwidth product in the range of about 100 kHz to 5 MHz and the first and second back- end amplifiers 314, 326 have a gain bandwidth product less than the gain bandwidth product of the front- end amplifiers 306, 318. In some embodiments, the first and second back- end amplifiers 314, 326 have a gain-bandwidth product in the range of about 10 kHz to 500 kHz.
In some embodiments, the first and second back-end amplifiers 314, 226 are Miller amplifiers, each having at least one respective pole in the frequency domain.
In some embodiments, the binary clock signal 309 a, 309 b has a frequency in a range of about 100 kHz to 1 MHz.
The chopper-stabilized amplifier 300 offers advantages over the chopper-stabilized amplifier 180 of FIG. 5 and the chopper-stabilized amplifier 240 of FIG. 6. Namely, the chopper-stabilized amplifier 300 can support higher frequencies of the clock signals 210 a, 210 b than the chopper-stabilized amplifier 180, and a higher rejection of common mode and of offset components than the chopper-stabilized amplifier 240 of FIG. 6.
In some alternate arrangements, a third switching network (not shown) is coupled to receive the output signals 316 a, 316 b, coupled to receive the clock signals 309 a, 309 b, and configured to provide a further differential output signal (not shown). These embodiments are particularly useful for arrangements in which the input signal 302 a, 302 b is un-modulated. However, these embodiments would suffer the same disadvantages described above in conjunction with the chopper-stabilized amplifier 180 of FIG. 5
Referring now to FIGS. 7A-7C, graphs 340, 360, 380 are indicative of signals appearing at points E, F, and G, respectively, of FIG. 7. It will be recognized that point E can be the same as point B of FIG. 1. It will also be recognized that point G can be the same as point C of FIG. 1. Point F, however, is internal to the chopper-stabilized amplifier 20 of FIG. 1. The graphs 340, 360, 380 each have a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of volts.
The graph 340, and signals appearing therein, is the same as the graph 120 of FIG. 4A. The graph 380, and signals appearing therein, is the same as the graph 140 of FIG. 4B. The graph 360 includes a signal 362 internal to the chopper-stabilized amplifier 20 of FIG. 1, which is an amplified and modulated offset component having a demodulated signal component 364. The signal 362 is larger than a signal 342 due to amplification provided by the chopper-stabilized amplifier 300 of FIG. 7.
It will be recognized that the AC part of the signal 342 comprises a modulated signal component, while the AC part of signal 362 and of signal 382 comprises a modulated offset component, which can be substantially removed by way of the low pass filter 24 of FIG. 1.
All references cited herein are hereby incorporated herein by reference in their entirety.
Having described preferred embodiments of the invention, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may be used. It is felt therefore that these embodiments should not be limited to disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.

Claims

1. A chopper-stabilized amplifier, comprising:

first and second front-end amplifiers, each having a respective input node and each having a respective feedback node, wherein the first front-end amplifier is configured to generate a first amplified output signal and the second front-end amplifier is configured to generate a second amplified output signal;

a first switching network coupled to receive a binary clock signal having first and second periodic states, coupled to receive the first and second amplified output signals, and configured to generate first and second switched output signals, wherein, during the first state of the binary clock signal, the first switched output signal is related to the first amplified output signal and the second switched output signal is related to the second amplified output signal, and wherein, during the second state of the binary clock signal, the first switched output signal is related to the second amplified output signal and the second switched output signal is related to the first amplified output signal;

first and second back-end amplifiers, wherein the first back-end amplifier is coupled to receive the first switched output signal and the second back-end amplifier is coupled to receive the second switched output signal, wherein the first back-end amplifier is configured to generate a first back-end output signal and the second back-end amplifier is configured to generate a second back-end output signal, wherein an output signal of the chopper-stabilized amplifier is a differential signal comprised of the first and second back-end output signals; and

at least one of a feedback circuit or a second switching network coupled to receive the first and second back-end output signals, wherein the other one of the feedback circuit or the second switching network is configured to generate first and second switched feedback signals, wherein the second switching network is coupled to receive the binary clock signal, wherein, during the first state of the binary clock signal, the first switched feedback signal is related to the first back-end output signal and the second switched feedback signal is related to the second back-end output signal, and wherein, during the second state of the binary clock signal, the first switched feedback signal is related to the second back-end output signal and the second switched feedback signal is related to the first back-end output signal, wherein the feedback node of the first front-end amplifier is coupled to receive the first switched feedback signal, and wherein the feedback node of the second front-end amplifier is coupled to receive the second switched feedback signal.

2. The chopper-stabilized amplifier of claim 1, wherein the feedback circuit comprises first, second, and third series coupled resistors.

3. The chopper-stabilized amplifier of claim 2, wherein the third resistor comprises two series coupled resistors.

4. The chopper-stabilized amplifier of claim 1, wherein the input nodes of the first and second front-end amplifiers are coupled to receive a modulated differential input signal.

5. The chopper-stabilized amplifier of claim 4, wherein the first and second amplified output signals are differential signals and wherein the first and second switched output signals are differential signals.

6. The chopper-stabilized amplifier of claim 4, wherein the modulated differential input signal includes a modulated signal component and an un-modulated offset component.

7. The chopper-stabilized amplifier of claim 1, wherein the first and second back-end output signals include a modulated offset component and an un-modulated signal component.

8. The chopper-stabilized amplifier of claim 1, wherein the first and second front-end amplifiers have a relatively larger gain-bandwidth product, and wherein the first and second back-end amplifiers have a relatively lower gain-bandwidth product.

9. The chopper-stabilized amplifier of claim 8, wherein the first and second front-end amplifiers have a gain-bandwidth product in the range of about 100 kHz to 5 MHz.

10. The chopper-stabilized amplifier of claim 9, wherein the first and second back-end amplifiers have a gain-bandwidth product in the range of about 10 kHz to 500 kHz.

11. The chopper-stabilized amplifier of claim 9, wherein the first and second back-end amplifiers are Miller amplifiers, each having at least one respective pole in the frequency domain.

12. The chopper-stabilized amplifier of claim 1, wherein the binary clock signal has a frequency in a range of about 100 kHz to 1 MHz.

13. A magnetic field sensor, comprising:

a Hall effect element having two output nodes at which is provided a differential output signal that varies in response to a magnetic field, the Hall effect element differential output signal comprising a magnetic field signal component and an offset component; and

a chopper-stabilized amplifier, comprising:

first and second front-end amplifiers, each having a respective input node coupled to the Hall effect element and each having a respective feedback node, wherein the first front-end amplifier is configured to generate a first amplified output signal and the second front-end amplifier is configured to generate a second amplified output signal;

first and second back-end amplifiers, wherein the first back-end

amplifier is coupled to receive the first switched output signal and the second back-end amplifier is coupled to receive the second switched output signal, wherein the first back-end amplifier is configured to generate a first back-end output signal and the second back-end amplifier is configured to generate a second back-end output signal, wherein an output signal of the chopper-stabilized amplifier is a differential signal comprised of the first and second back-end output signals; and

14. The magnetic field sensor of claim 13, further comprising a modulation circuit coupled between the Hall effect element and the chopper-stabilized amplifier and coupled to receive the binary clock signal, wherein the modulation circuit is operable to modulate the magnetic field signal component to provide to the first and second front-end amplifiers a modulated signal having the modulated magnetic field signal component and having an un-modulated offset component.

15. The magnetic field sensor of claim 14, wherein the modulation circuit is operable to modulate the magnetic field signal component in accordance with the frequency of the binary clock signal.

16. The magnetic field sensor of claim 14, wherein the feedback circuit comprises first, second, and third series coupled resistors.

17. The magnetic field sensor of claim 14, wherein the first and second amplified output signals are differential signals and wherein the first and second switched output signals are differential signals.

18. The magnetic field sensor of claim 14, wherein the first and second back-end output signals include a modulated offset component and a de-modulated magnetic field signal component.

19. The magnetic field sensor of claim 14, wherein the first and second front-end amplifiers have a relatively larger gain-bandwidth product, and wherein the first and second back-end amplifiers have a relatively lower gain-bandwidth product.

20. The magnetic field sensor of claim 19, wherein the first and second front-end amplifiers have a gain-bandwidth product in the range of about 100 kHz to 5 MHz.

21. The magnetic field sensor of claim 20, wherein the first and second back-end amplifiers have a gain-bandwidth product in the range of about 10 kHz to 500 kHz.

22. The magnetic field sensor of claim 19, wherein the first and second back-end amplifiers are Miller amplifiers, each having at least one respective pole in the frequency domain.

23. The magnetic field sensor of claim 14, wherein the binary clock signal has a frequency in a range of about 100 kHz to 1 MHz.