CN106419862A - Signal reading circuit, control method thereof and pulse detector - Google Patents
Signal reading circuit, control method thereof and pulse detector Download PDFInfo
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Abstract
A signal reading circuit comprises a first transistor, a second transistor, an amplifier and a resistor. The first terminal of the first transistor is used for receiving a first reference voltage. The second end of the first transistor is electrically coupled to the first node. The control end of the first transistor is used for receiving a first reference voltage. The first end of the second transistor is electrically coupled to the first node. The second terminal of the second transistor is used for receiving a second reference voltage. The control end of the second transistor is used for receiving the input voltage. The amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically coupled to the first node, and the second input terminal is used for receiving a second reference voltage. One end of the resistor is electrically coupled to the first input end of the amplifier. The other end of the resistor is electrically coupled to the output end of the amplifier. The invention also discloses a control method of the signal reading circuit and a pulse detector with the signal reading circuit.
Description
Technical field
The present invention relates to a kind of signal read circuits and its control method, especially with regard to the signal-obtaining electricity of sensing element
Road and its control method have the pulse wave detector of this signal read circuits.
Background technology
By signal read circuits, optical signal, thermal signal or the raw anaiog signals such as signal of curing may pass through suitably such as
Gain or compensation, so that user carries out follow-up analyzing and processing.Even described anaiog signal can also be carried out suitably
Sampling, form discrete signal or digital signal, to be user-friendly for digital signal process.
In system, often the efficiency of each block circuit is considered as consistent with standard criterion.But on side circuit
For, the element of each several part circuit is in extreme circumstances or after passing through long running, often special according to its physics
Property produce the degradation phenomena that differs of degree, cause circuit parameter drift, have influence on circuit performance.For signal read circuits,
The conduction resistance value OR gate sill magnitude of voltage of the transistor in circuit usually can hence deviate from originally designed preset value, causes letter
The output misalignment of number reading circuit, and make subsequent treatment analysis error.
Content of the invention
The technical problem to be solved is to provide a kind of signal read circuits and its control method, to overcome crystal
Pipe deterioration leads to parameter drift to make signal read circuits export the problem of misalignment.
To achieve these goals, the invention provides a kind of signal read circuits, described signal read circuits include
The first transistor, transistor seconds, amplifier and resistance.The first end of the first transistor is in order to receive the first reference voltage.The
Second end electric property coupling primary nodal point of one transistor.The control end of the first transistor is in order to receive the first reference voltage.Second
The first end electric property coupling primary nodal point of transistor.Second end of transistor seconds is in order to receive the second reference voltage.Second is brilliant
The control end of body pipe is in order to receives input voltage.Amplifier has first input end, the second input and outfan.First input
End electric property coupling primary nodal point.Second input is in order to receive the second reference voltage.One end electric property coupling amplifier of resistance
First input end.The outfan of the other end electric property coupling amplifier of resistance.
In order to above-mentioned purpose is better achieved, present invention also offers a kind of control method of signal read circuits, described
The control method of signal read circuits be applied to signal read circuits.Signal read circuits have the first transistor, the second crystalline substance
Body pipe, resistance and amplifier.Amplifier has first input end, the second input and outfan.One end electricity of the first transistor
Property couples first input end, and the other end is in order to receive the first reference voltage.One end electric property coupling first of transistor seconds inputs
End, the other end is in order to receive the second reference voltage.The two ends of resistance electric property coupling first input end and outfan respectively.Described
Control method includes operating the first transistor and transistor seconds in linear zone.And make the current value of the electric current flowing through resistance be the
The conducting electric current of one transistor and the difference of the conducting electric current of transistor seconds.And, make the cross-pressure at the two ends of the first transistor
Value is equal to the cross-pressure value at the two ends of transistor seconds.Wherein, the voltage quasi position of the outfan of amplifier is associated with the resistance of resistance
With the electric current flowing through resistance.
In order to above-mentioned purpose is better achieved, present invention also offers a kind of pulse wave detector, wherein, including：
Multiple detection modules, this detection module each includes：
Signal read circuits described above；And
One sensing unit, this signal read circuits of electric property coupling, this sensing unit is in order to produce according to an organism pulse
This input voltage.
The method have technical effect that：
Comprehensive the above, the signal read circuits of the present invention and its control method, using the mode of current subtraction, reduce
The impact that element electrically makes a variation for sensing element signal readout.Whereby, even if the parameter of the element in signal read circuits
Misalignment, signal read circuits still can avoid being affected by misalignment parameter, and remains to output accurately readings, is successfully overcome by
The problem of component parameters misalignment effects signal read circuits precisions.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Brief description
Fig. 1 is the circuit diagram of the signal read circuits according to depicted in first embodiment of the invention；
Fig. 2 is the circuit diagram of the signal read circuits according to depicted in second embodiment of the invention；
Fig. 3 is the circuit diagram of the signal read circuits according to depicted in third embodiment of the invention；
Fig. 4 is the circuit diagram of the signal read circuits according to depicted in fourth embodiment of the invention；
Fig. 5 is the circuit diagram of the signal read circuits according to depicted in fifth embodiment of the invention；
Fig. 6 is the circuit diagram of the signal read circuits according to depicted in sixth embodiment of the invention；
Fig. 7 is the circuit diagram of the signal read circuits according to depicted in seventh embodiment of the invention；
Fig. 8 is the circuit diagram of the signal read circuits according to depicted in eighth embodiment of the invention；
Fig. 9 is the circuit diagram of the subtraction block according to depicted in one embodiment of the invention；
Figure 10 is the schematic flow sheet of the control method of the signal read circuits according to depicted in one embodiment of the invention；
Figure 11 is the schematic diagram of the pulse wave detector according to depicted in one embodiment of the invention；
Figure 12 is the function side of one of detector unit of the pulse wave detector according to depicted in one embodiment of the invention
Block schematic diagram.
Wherein, reference
1～8 signal read circuits
72nd, 82 first sampling module
74th, 84 second sampling module
96 subtraction block
962 buffer cells
964 subtrators
C1, C2 electric capacity
CK first clock signal
IR, IR ', IT1, IT2, IT1 ', IT2 ' electric current
N1 primary nodal point
Nin1 first input end
Nin2 second input
Nout outfan
OP, OPS1, OPS2 amplifier
R, RS1～RS4 resistance
SW1, SW2 sampling switch
T1, T1 ' the first transistor
T2, T2 ' transistor seconds
T3, T3 ' third transistor
T4, T4 ' the 4th transistor
TS1 first sampling transistor
TS2 second sampling transistor
TS3 the 3rd sampling transistor
TS4 the 4th sampling transistor
V1 first reference voltage
V2 second reference voltage
Vref1 first reference voltage
Vref2 second reference voltage
Vref3 the 3rd reference voltage
Vref4 the 4th reference voltage
Vin input voltage
Vout, Vout ' output voltage
XCK second clock signal
Specific embodiment
Below in conjunction with the accompanying drawings the structural principle and operation principle of the present invention is described in detail：
Hereinafter detailed features and the advantage of the present invention are described in embodiments in detail, its content be enough to make this area skill
Art personnel understand that the technology contents of the present invention are simultaneously implemented according to this, and the content according to disclosed by this specification, claims and
Schema, skilled person readily understands that the related purpose of the present invention and advantage.Below example system is detailed further
Describe the viewpoint of the bright present invention in detail, but non-anyways to limit scope of the invention.
Refer to Fig. 1, Fig. 1 is the circuit diagram of the signal read circuits according to depicted in first embodiment of the invention.
As shown in figure 1, signal read circuits 1 include the first transistor T1, transistor seconds T2, amplifier OP and resistance R.First crystal
The first end of pipe T1 is in order to receive the first reference voltage V 1.The second end electric property coupling primary nodal point N1 of the first transistor T1.The
The control end of one transistor T1 is in order to receive the first reference voltage Vref 1.The first end electric property coupling first of transistor seconds T2
Node N1.Second end of transistor seconds T2 is in order to receive the second reference voltage V 2.The control end of transistor seconds T2 is in order to connect
Receive input voltage vin.Amplifier OP has first input end Nin1, the second input Nin2 and outfan Nout.First input
End Nin1 electric property coupling primary nodal point N1.Second input Nin2 is in order to receive the second reference voltage Vref 2.One end of resistance R
The first input end Nin1 of electric property coupling amplifier OP.The outfan Nout of the other end electric property coupling amplifier OP of resistance R.Its
In, a first reference voltage V 1 for example, relative high voltage level, a second reference voltage V 2 for example, relative low-voltage
Level.In one embodiment, the first reference voltage V 1 is the voltage VDD in system, and the second reference voltage V 2 is the electricity in system
Pressure VSS, voltage VDD are high levle reference voltage, and voltage VSS is low level reference voltage, but is not limited thereto.Here is implemented
In example, the first transistor T1 and transistor seconds T2 is metal oxide semiconductor transistor (the Metal Oxide of N-type
Semiconductor Field-Effect Transistor, MOSFET), but be not limited thereto.
The first transistor T1 is controlled by the first reference voltage Vref 1 and selectively turns on.Transistor seconds T2 is controlled by
Input voltage vin and selectively turn on.According to imaginary short (virtual short) characteristic of amplifier OP, amplifier OP's
The voltage quasi position of first input end Nin1 is substantially equal to the voltage quasi position of the second input Nin2 so that the electricity of primary nodal point N1
Pressure level is equal to the second reference voltage Vref 2.Additionally, the voltage quasi position of output node Nout is the electricity of first input end Nin1
The difference that the voltage quasi position amplified device OP of pressure level and the second input Nin2 amplifies, and the voltage quasi position of output node Nout
It is associated with the yield value of amplifier OP.The correlation properties of amplifier OP are known by skilled artisan, in this not
Repeat again.And when amplifier OP has height and opens loop gain, the current value flowing through the electric current IR of resistance R1 can be generally stream
The difference of the electric current IT1 through the first transistor T1 and electric current IT2 flowing through transistor seconds T2.
In an embodiment, the first transistor T1 and transistor seconds T2 is operated at linear zone (Triode Mode), because
This electric current IT1 and electric current IT2 such as following formula：
VDS1 in formula (1) is the cross-pressure with source terminal for the drain electrode end of the first transistor T1.VDS2 in formula (2) is second
The drain electrode end of transistor T2 and the cross-pressure of source terminal.And the Vth in formula (1) and formula (2) represents is the first transistor T1 and the
The threshold voltage value of two-transistor T2, what μ n represented is the carrier mobility of the first transistor T1 and transistor seconds T2, Cox generation
The specific capacitance size being the first transistor T1 with the grid oxic horizon of transistor seconds T2 of table,Represent is first crystal
The passage breadth length ratio of pipe T1 and transistor seconds T2.In this embodiment, the first transistor T1 and transistor seconds T2 has reality
Matter identical threshold voltage value Vth, substantially identical carrier mobility μ n, the specific capacitance of substantially identical grid oxic horizon
Cox and substantially identical passage breadth length ratioIn practice, above-mentioned parameter value is being read in detail for skilled artisan
After this specification, it is able to, in free adjustment without departing from the spirit of the invention, not be limited with above-mentioned.
On the other hand, the voltage quasi position of the second reference voltage Vref 2 is set to the first reference voltage V 1 and the second benchmark
The meansigma methodss of voltage V2 are so that the VDS1 in formula (1) is equal to the VDS2 in formula (2).Here replaces VDS1 and VDS2 with VDS,
In order to follow-up explanation.As earlier mentioned, due to the high input impedance charcteristic of amplifier OP, electric current IR is electric current IT1 and electric current IT2
Difference.Under conditions of above-mentioned, electric current IR such as following formula：
According to formula (3), electric current IR is already unrelated with the threshold voltage value of transistor seconds T2 with the first transistor T1.
Further, the output voltage Vout of signal read circuits 1 is expressed as follows formula：
Vout=Vref2-R × IR (4)
Therefore, the output voltage Vout of the signal read circuits 1 also threshold with the first transistor T1 and transistor seconds T2
Magnitude of voltage is unrelated.In other words, even if the first transistor T1 and transistor seconds T2 deteriorates and makes the first transistor T1 and second
The threshold voltage value drift of transistor T2, signal read circuits 1 also can produce more accurately output voltage according to input voltage vin
Vout, and output voltage Vout, can not be affected by the threshold voltage value offseting ideally.In this embodiment, export electricity
Pressure Vout system is associated with resistance, the electric current IR flowing through resistance R1 and second reference voltage Vref 2 of resistance R1.
Refer to Fig. 2, Fig. 2 is the circuit diagram of the signal read circuits according to depicted in second embodiment of the invention.
From unlike the embodiment shown in Fig. 1, signal read circuits 2 also have sampling switch SW1 and sampling switch SW2.Sampling is opened
Close the first input end Nin1 and outfan Nout of the two ends difference electric property coupling amplifier OP of SW1.One end of sampling switch SW2
One end of electric property coupling the first transistor T1 and transistor seconds T2 phase electric property coupling, the electrical coupling of the other end of sampling switch SW2
Meet the first input end Nin1 of amplifier OP.Sampling switch SW1 is controlled by the second clock signal XCK, and sampling switch SW2 is controlled by
First clock signal CK.
Under such circuit framework with signal sequence, when the first clock signal CK is low voltage level, sampling switch
SW1 turns on and sampling switch SW2 is not turned on, and the output voltage Vout of signal read circuits 2 is same as the second reference voltage
Vref2.When the first clock signal CK is low voltage level, sampling switch SW1 is not turned on and sampling switch SW2 conducting, signal
The output voltage Vout of reading circuit 2 is same as aforesaid formula (4).Whereby, it is able to enter according to the input voltage vin after adjusted
Row sampling.Wherein, sampling switch SW1 and sampling switch SW2 is, for example, bipolar transistor (bi-polar junction
Transistor, BJT), thin film transistor (TFT), metal oxide semiconductor transistor or with multiple element composition switch electricity
Road, here is not any limitation as.
Please referring next to Fig. 3, Fig. 3 is that the circuit of the signal read circuits according to depicted in third embodiment of the invention is illustrated
Figure.Compared to the embodiment shown in Fig. 2, signal read circuits 3 also have third transistor T3 and the 4th transistor T4.Is trimorphism
The first end of body pipe T3 is in order to receive the first reference voltage V 1.Second end electric property coupling the first transistor T1 of third transistor T3
First end.The control end of third transistor T3 is in order to receive the 3rd reference voltage Vref 3.The first end electricity of the 4th transistor T4
Property couples second end of transistor seconds T2.Second end electric property coupling second reference voltage V 2 of the 4th transistor T4.4th is brilliant
The control end of body pipe T4 is in order to receive the 4th reference voltage Vref 4.By similar to series connection the first transistor T1 and the 3rd crystal
Pipe T3, and series connection transistor seconds T2 and the 4th transistor T4.Skilled artisan is when it is understood that signal-obtaining
Circuit ought can be provided with the transistor being more mutually in series, and the number of transistor is not limited with the cited case.
Refer to Fig. 4, Fig. 5 and Fig. 6, Fig. 4 is the electricity of the signal read circuits according to depicted in fourth embodiment of the invention
Road schematic diagram, Fig. 5 is the circuit diagram of the signal read circuits according to depicted in fifth embodiment of the invention, according to Fig. 6
The circuit diagram of the signal read circuits depicted in sixth embodiment of the invention.Embodiment corresponding to Fig. 4 similar in Fig. 2 institute
Corresponding embodiment, Fig. 5 and the embodiment then similar embodiment corresponding in Fig. 3 corresponding to Fig. 6.Except for the difference that, in Fig. 4 institute
In corresponding embodiment, the first transistor T1 ' is the metal oxide semiconductor transistor of p-type.Embodiment corresponding in Fig. 5
In, the first transistor T1 ' and third transistor T3 ' for p-type metal oxide semiconductor transistor.Reality corresponding in Fig. 6
Apply in example, the first transistor T1 ' is so that the 4th transistor T4 ' is the metal oxide semiconductor transistor of p-type.By Fig. 1
Embodiment shown in Fig. 6, the signal read circuits of this case are able to be applied to different systems in the case of possessing core spirit
Journey, increased the wide usage in practice.Above are only citing demonstration, be actually not limited thereto.
Refer to Fig. 7, Fig. 7 is the circuit diagram of the signal read circuits according to depicted in seventh embodiment of the invention.
In embodiment corresponding in Fig. 7, compared to the embodiment shown in Fig. 1, signal read circuits 7 also have sampling switch SW1,
One sampling module 72 and the second sampling module 74.First input of the two ends difference electric property coupling amplifier OP of sampling switch SW1
The outfan Nout of end Nin1 and amplifier OP.Sampling switch SW1 optionally inputs first according to the second clock signal XCK
End Nin1 is conducted to outfan Nout.
First sampling module 72 has the first sampling transistor TS1 and the second sampling transistor TS2.Second sampling module 74
There is the 3rd sampling transistor TS3 and the 4th sampling transistor TS4.The first end of the first sampling transistor TS1 is in order to receive
One reference voltage Vref 1.The control end of the second end electric property coupling the first transistor T1 of the first sampling transistor TS1.First takes
The control end of sample transistor TS1 is in order to receive the first clock signal CK.The first end electric property coupling of the second sampling transistor TS2
The control end of one transistor T1.Second end of the second sampling transistor TS2 is in order to receive the second reference voltage Vref 2.Second takes
The control end of sample transistor TS2 is in order to receive the second clock signal XCK.
Second sampling module 74 has the 3rd sampling transistor TS3 and the 4th sampling transistor TS4.3rd sampling transistor
The first end of TS3 is in order to receives input voltage Vin.The second end electric property coupling transistor seconds T2 of the 3rd sampling transistor TS3
Control end.The control end of the 3rd sampling transistor TS3 is in order to receive the first clock signal CK.4th sampling transistor TS4's
The control end of first end electric property coupling the first transistor T1.Second end of the 4th sampling transistor TS4 is in order to receive the second benchmark
Voltage V2.The control end of the 4th sampling transistor TS4 is in order to receive the second clock signal XCK.
Under such circuit framework with signal sequence, when the first clock signal CK is low voltage level, the first sampling
Transistor TS1 is not turned on the 3rd sampling transistor TS3, the second sampling transistor TS2, the 4th sampling transistor TS4 and sampling
Switch SW1 conducting.Now, the second reference voltage Vref 2 is provided to the control end of the first transistor T1, the second reference voltage V 2
It is provided to the control end of transistor seconds T2.The voltage quasi position of the control end of the first transistor T1 similar in primary nodal point N1's
Voltage quasi position, the first transistor T1 is not turned on.The voltage quasi position of the control end of transistor seconds T2 similar in transistor seconds T2
The second end voltage quasi position, transistor seconds T2 is not turned on.By the second sampling transistor T2 and the 4th sampling transistor T4,
It is stabilized the voltage quasi position of the voltage quasi position of control end of the first transistor T1 and the control end of transistor seconds T2, and guarantee
The first transistor T1 and transistor seconds T2 is not turned on when the first clock signal CK is for low voltage level.
When the first clock signal CK is high voltage level, the first sampling transistor TS1 and the 3rd sampling transistor TS3 leads
Logical, the second sampling transistor TS2, the 4th sampling transistor TS4 and sampling switch SW1 are not turned on.Now, the first reference voltage
Vref1 is provided to the control end of the first transistor T1, and input voltage vin is provided to the control end of transistor seconds T2.Right
Ying Di, the electric current IT1 ' the flowing through the first transistor T1 and electric current IT2 ' flowing through transistor seconds T2 can be expressed as follows two respectively
Formula：
Parameter in formula (5) and formula (6) is it has been observed that repeat no more in this.Only Δ V is the first sampling transistor
The voltage difference that the conducting resistance of the conducting resistance of TS1 and the 3rd sampling transistor TS3 is led to.Similarly, in this embodiment,
The voltage difference that the conducting resistance of the first sampling transistor TS1 is led to and the conducting resistance of the 3rd sampling transistor TS3 are led to
Voltage difference be substantially the same, but be not limited thereto.Now, electric current IR ' equally expresses as formula (7)：
In other words, electric current IR ' is independent of the conducting resistance of the first sampling transistor TS1 and the 3rd sampling transistor TS3,
And electric current IR ' is independent of the threshold voltage of the first transistor T1 and transistor seconds T2.As earlier mentioned, now output voltage Vout
System is associated with resistance, the electric current IR flowing through resistance R1 and second reference voltage Vref 2 of resistance R1, therefore output voltage Vout
Conducting resistance independent of the first sampling transistor TS1 and the 3rd sampling transistor TS3 and the first transistor T1 and second are brilliant
The threshold voltage of body pipe T2.
And in the embodiment corresponding in Fig. 7, signal read circuits 7 also have electric capacity C1 and electric capacity C2.Electric capacity C1 is electrical
Couple second end of the first sampling transistor TS1 and the first end of the second sampling transistor TS2.Electric capacity C2 electric property coupling the 3rd takes
Second end of sample transistor TS3 and the first end of the 4th sampling transistor TS4.Electric capacity C1, C2 in order to voltage regulation filtering, to prevent
The voltage quasi position of control end of one transistor T1 and the voltage quasi position of the control end of transistor seconds T2 are disturbed by noise.One
In embodiment, electric capacity C1 is identical with the capacitance of electric capacity C2, but is not limited thereto.
Refer to Fig. 8, Fig. 8 is the circuit diagram of the signal read circuits according to depicted in eighth embodiment of the invention.
The similar embodiment corresponding in Fig. 7 of embodiment shown in Fig. 8, difference is, each transistor in Fig. 8 is the gold of p-type
Belong to oxide semi conductor transistor, and each voltage is also adjusted accordingly.Correlative detail is skilled artisan's warp
Can analogize after readding this specification in detail and obtain, here is not repeated here.Embodiment shown in Fig. 8 have with corresponding to Fig. 7
The similar effect of embodiment, and the mode of another implementation in technique is provided.
On the other hand, as shown in formula (4), output voltage Vout is of virtually one and is equal to the second reference voltage
The side-play amount of Vref2, and make the input voltage vin that output voltage Vout can not be directly through gain.In practice, this
Bright provided signal read circuits can also have subtraction block to eliminate the side-play amount of output voltage Vout.Please with reference to figure
9, Fig. 9 is the circuit diagram of the subtraction block according to depicted in one embodiment of the invention.Subtraction block 96 has buffer cell
962 with subtrator 964.The input of buffer cell 962 is in order to receive output voltage Vout as the aforementioned, buffer cell 962
Outfan electric property coupling subtrator 964 input.Buffer cell 962 has amplifier OPS1.Subtrator 964 has
Resistance RS1～RS4 and amplifier OPS2.Wherein, the non-inverting input electric property coupling amplifier OPS2's of amplifier OPS1 is defeated
Go out end and form voltage follower, amplifier OPS2 then becomes voltage subtraction device with resistance RS1～RS4 electric property coupling.Voltage subtraction
One end of device is the input of subtrator 964, and the other end of voltage subtraction device is then in order to receive the second reference voltage
Vref2.In this embodiment, the resistance value of resistance RS1～RS4 is mutually the same.Therefore, by formula (4) and the subtraction mould shown in Fig. 9
Block 96, subtraction block 96 produces output voltage Vout ' according to output voltage Vout and the second reference voltage Vref 2.Wherein, export
Voltage Vout ' is expressed as follows formula：
Vout '=R × IR (8)
That is, by subtraction block 96, output voltage Vout ' no longer has the skew having as output voltage Vout
Amount.And in another kind of embodiment, the other end of subtraction block is for example in order to receive time varying signal.The frequency of this time varying signal with
Waveform is same as the first clock signal CK as the aforementioned, its amplitude can according to actually required be exaggerated or be lowered.Whereby, except can
So that output voltage Vout ' no longer has the side-play amount as being associated with the second reference voltage Vref 2, also lifted back-end processing
Dynamic range (dynamic range).
According to above-mentioned, present invention also offers a kind of pulse sensor.Refer to Figure 11, Figure 11 is real according to the present invention one
Apply the schematic diagram of the pulse wave detector depicted in example.Pulse wave detector 20 has multiple detection modules.The row of act in this embodiment
Illustrate as a example the detection module 202a～202p arranging into array, so the number of each detection module actually in pulse wave detector
Amount should not be limited with the cited case with arrangement mode.
Please referring next to Figure 12 further to be described to pulse wave detector, Figure 12 is according to one embodiment of the invention
The function block schematic diagram of one of detector unit of depicted pulse wave detector.Figure 12 is according to the detection module in Figure 11
202a illustrates and forms.As shown in figure 12, detection module 202a has sensing unit 2022a and signal read circuits 2024a.
Sensing unit 2022a electric property coupling signal read circuits 2024a.In one embodiment, sensing unit 2022a is for example
For piezo sensor, sensing unit 2022a is in order to produce corresponding piezoelectric signal using as the aforementioned according to organism pulse
Input signal.Piezo sensor 30 for example has the piezoelectricity made with Kynoar (Polyvinylidene, PVDF) material
Thin film, but be not limited thereto.
Signal read circuits 2024a are, for example, arbitrary described signal read circuits in Fig. 1 to Fig. 9.Related start details
It has been observed that repeating no more in this.In this embodiment, detection module 202a also has modulation unit 2026a.Modulation unit
2026a electric property coupling signal read circuits 2024a.Modulation unit 2026a believes in order to the output of basis signal reading circuit 2024a
Number produce corresponding to subsequent conditioning circuit specification modulating signal, for subsequent conditioning circuit use.So modulation unit is a kind of selective
Design, each detection module not necessarily has modulation unit.
As above-mentioned concept, present invention also offers a kind of control method of signal read circuits, refer to Figure 10 to carry out
Illustrate, Figure 10 is the schematic flow sheet of the control method of the signal read circuits according to depicted in one embodiment of the invention.As figure
The control method of the signal read circuits described in 10 is it is adaptable to signal read circuits.Described signal read circuits have first
Transistor, transistor seconds, resistance and amplifier.Amplifier has first input end, the second input and outfan.First is brilliant
One end electric property coupling first input end of body pipe, the other end is in order to receive the first reference voltage.One end of transistor seconds is electrical
Couple first input end, the other end is in order to receive the second reference voltage.The two ends of resistance respectively electric property coupling first input end with
Outfan., in step S101, operation the first transistor is with transistor seconds in linear zone for described control method.In step
In S103, the current value that order flows through the electric current of resistance is conducting electric current and the conducting electric current of transistor seconds of the first transistor
Difference.And in step S105, make the cross-pressure value at the two ends of the first transistor be equal to the cross-pressure value at the two ends of transistor seconds.Its
In, the voltage quasi position of the outfan of amplifier is associated with the resistance of resistance and flows through the electric current of resistance.It is noted that it is above-mentioned
Step S103 and step S105 have no dividing of inevitable sequencing.
In an embodiment, the cross-pressure value at the two ends making the first transistor is equal to the cross-pressure value at the two ends of transistor seconds
Step in, provide the second reference voltage to the second input, the second reference voltage is that the first reference voltage and the second benchmark are electric
The meansigma methodss of pressure.
Comprehensive the above, the invention provides a kind of signal read circuits and its control method, using current subtraction
Mode, reduces the impact that element electrically makes a variation for sensing element signal readout.Whereby, even if the unit in signal read circuits
Because the situation misalignment in practice, signal read circuits are still avoided that to be affected part parameter by parameter misalignment, and still exportable
Accurately readings, successfully overcomes the problem of component parameters misalignment effects signal read circuits precision.
Certainly, the present invention also can have other various embodiments, in the case of without departing substantially from present invention spirit and its essence, ripe
Know those skilled in the art and work as and various corresponding changes and deformation can be made according to the present invention, but these corresponding changes and change
Shape all should belong to the protection domain of appended claims of the invention.
Claims (11)
1. a kind of signal read circuits are it is characterised in that include：
One the first transistor, a first end of this first transistor in order to receive one first reference voltage, this first transistor
One second end electric property coupling one primary nodal point, a control end of this first transistor is in order to receive one first reference voltage；
One transistor seconds, this primary nodal point of first end electric property coupling of this transistor seconds, the one of this transistor seconds
In order to receive one second reference voltage, a control end of this transistor seconds is in order to receive an input voltage at two ends；
One amplifier, has a first input end, one second input and an outfan, this first input end electric property coupling this
One node, this second input is in order to receive one second reference voltage；And
One resistance, this first input end of one end this amplifier of electric property coupling, this output of the other end this amplifier of electric property coupling
End.
2. signal read circuits as claimed in claim 1, the current value wherein flowing through the electric current of this resistance is this first crystal
The conducting electric current of pipe and the difference of the conducting electric current of this transistor seconds.
3. signal read circuits as claimed in claim 1 are it is characterised in that this first transistor is operated with this transistor seconds
In linear zone, the voltage quasi position of this outfan of this amplifier is associated with the resistance of this resistance, the electric current flowing through this resistance and is somebody's turn to do
Second reference voltage.
4. signal read circuits as claimed in claim 1 it is characterised in that this second reference voltage magnitude of voltage be this first
Reference voltage and the meansigma methodss of this second reference voltage.
5. signal read circuits as claimed in claim 1 it is characterised in that the passage breadth length ratio of this first transistor with this
The passage breadth length ratio of two-transistor is identical.
6. signal read circuits as claimed in claim 1 are it is characterised in that also include：
One third transistor, a first end of this third transistor in order to receive this first reference voltage, this third transistor
The first end of one second end this first transistor of electric property coupling, a control end of this third transistor is in order to receive one the 3rd reference
Voltage；And
One the 4th transistor, the second end of first end this transistor seconds of electric property coupling of the 4th transistor, the 4th is brilliant
This second reference voltage of one second end electric property coupling of body pipe, a control end of the 4th transistor is in order to receive one the 4th reference
Voltage.
7. the signal read circuits as any one of claim 1 to 6 are it is characterised in that also include：
One first sampling module, including：
One first sampling transistor, in order to receive this first reference voltage, this first for a first end of this first sampling transistor
This control end of one second end this first transistor of electric property coupling of sampling transistor, a control end of this first sampling transistor
In order to receive one first clock signal；And
One second sampling transistor, this control of first end this first transistor of electric property coupling of this second sampling transistor
End, one second end of this second sampling transistor is in order to receive this second reference voltage, a control of this second sampling transistor
End in order to receive one second clock signal, this second clock signal anti-phase in this first clock signal；And
One second sampling module, including：
One the 3rd sampling transistor, in order to receive this input voltage, the 3rd samples a first end of the 3rd sampling transistor
This control end of one second end this transistor seconds of electric property coupling of transistor, a control end of the 3rd sampling transistor in order to
Receive this first clock signal；And
One the 4th sampling transistor, this control of first end this first transistor of electric property coupling of the 4th sampling transistor
End, one second end of the 4th sampling transistor is in order to receive this second reference voltage, a control of the 4th sampling transistor
End is in order to this second clock signal；
One sampling switch, two ends this first input end of this amplifier of electric property coupling and this amplifier respectively of this sampling switch
This outfan, this first input end is optionally conducted to this outfan according to this second clock signal by this sampling switch.
8. signal read circuits as claimed in claim 1 are it is characterised in that also include a subtraction block, this subtraction block
This outfan of input this amplifier of electric property coupling, the output signal of this subtraction block is associated with the resistance of this resistance and flows through
The electric current of this resistance.
9. a kind of control method of signal read circuits is it is adaptable to signal read circuits are it is characterised in that this signal-obtaining is electric
Road has a first transistor, a transistor seconds, a resistance and an amplifier, this amplifier have a first input end, one
Second input and an outfan, this first input end of one end electric property coupling of this first transistor, the other end is in order to receive one
First reference voltage, this first input end of one end electric property coupling of this transistor seconds, the other end is in order to receive one second benchmark
Voltage, two ends this first input end of electric property coupling and this outfan respectively of this resistance, this control method includes：
Operate this first transistor and this transistor seconds in linear zone；
The current value making the electric current flowing through this resistance is the conducting electric current of this first transistor and the electric conduction of this transistor seconds
The difference of stream；And
Make this first transistor two ends cross-pressure value be equal to this transistor seconds two ends cross-pressure value；
Wherein, the voltage quasi position of this outfan of this amplifier is associated with the resistance of this resistance and flows through the electric current of this resistance.
10. control method as claimed in claim 9 is it is characterised in that cross-pressure value in the two ends making this first transistor etc.
In the step of the cross-pressure value at the two ends of this transistor seconds, including providing one second reference voltage to this second input, should
Second reference voltage system is the meansigma methodss of this first reference voltage and this second reference voltage.
A kind of 11. pulse wave detectors are it is characterised in that include：
Multiple detection modules, this detection module each includes：
Signal read circuits as any one of claim 1 to claim 8；And
One sensing unit, this signal read circuits of electric property coupling, this sensing unit is defeated in order to produce this according to an organism pulse
Enter voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105122518 | 2016-07-15 | ||
| TW105122518A TWI605683B (en) | 2016-07-15 | 2016-07-15 | Signal reading circuit and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106419862A true CN106419862A (en) | 2017-02-22 |
| CN106419862B CN106419862B (en) | 2019-08-09 |
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| CN201610929628.9A Expired - Fee Related CN106419862B (en) | 2016-07-15 | 2016-10-31 | Signal reading circuit, control method thereof and pulse detector |
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| Country | Link |
|---|---|
| CN (1) | CN106419862B (en) |
| TW (1) | TWI605683B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108777150A (en) * | 2018-05-02 | 2018-11-09 | 友达光电股份有限公司 | Sensing circuit |
| CN109965854A (en) * | 2018-08-29 | 2019-07-05 | 友达光电股份有限公司 | Sensing part and pulse condition measurement method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI709895B (en) * | 2020-01-14 | 2020-11-11 | 大陸商北京集創北方科技股份有限公司 | Analog front-end circuit, biological feature acquisition circuit, touch detection circuit and information processing device |
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| CN1590967A (en) * | 2003-09-03 | 2005-03-09 | 精工爱普生株式会社 | Sensing services and sensing circuits |
| CN103869860A (en) * | 2012-12-13 | 2014-06-18 | 创杰科技股份有限公司 | Voltage generator |
| CN104269140A (en) * | 2014-09-03 | 2015-01-07 | 友达光电股份有限公司 | Organic light emitting diode circuit |
| US20160056780A1 (en) * | 2014-08-19 | 2016-02-25 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
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2016
- 2016-07-15 TW TW105122518A patent/TWI605683B/en not_active IP Right Cessation
- 2016-10-31 CN CN201610929628.9A patent/CN106419862B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1590967A (en) * | 2003-09-03 | 2005-03-09 | 精工爱普生株式会社 | Sensing services and sensing circuits |
| CN103869860A (en) * | 2012-12-13 | 2014-06-18 | 创杰科技股份有限公司 | Voltage generator |
| US20160056780A1 (en) * | 2014-08-19 | 2016-02-25 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
| CN104269140A (en) * | 2014-09-03 | 2015-01-07 | 友达光电股份有限公司 | Organic light emitting diode circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108777150A (en) * | 2018-05-02 | 2018-11-09 | 友达光电股份有限公司 | Sensing circuit |
| CN109965854A (en) * | 2018-08-29 | 2019-07-05 | 友达光电股份有限公司 | Sensing part and pulse condition measurement method |
| US11262863B2 (en) | 2018-08-29 | 2022-03-01 | Au Optronics Corporation | Sensing component and pulse measuring method |
| CN109965854B (en) * | 2018-08-29 | 2022-03-01 | 友达光电股份有限公司 | Sensing component and pulse condition measuring method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106419862B (en) | 2019-08-09 |
| TWI605683B (en) | 2017-11-11 |
| TW201803264A (en) | 2018-01-16 |
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