TW201803264A - Signal reading circuit and control method thereof - Google Patents

Abstract

A signal reading circuit includes a first transistor, a second transistor, an amplifier and a resistor. One end of the first transistor is configured to receive a first base voltage. The second end of the first transistor is coupled to a first node. The control end of the first transistor is configured to receive a first reference voltage. The first end of the second transistor is coupled to the first node. The second end of the second transistor is configured to receive a second base voltage. The control end of the second transistor is configured to receive an input voltage. The amplifier includes a first input end, a second input end and an output end. The first input end is coupled to the first node. The second input end is configured to receive a second reference voltage. One end of the resistor is coupled to the first input end of the first input end. Another end of the resistor is coupled to the output end of the amplifier.

Description

Signal reading circuit and control method thereof

The invention relates to a signal reading circuit and a control method thereof, in particular to a signal reading circuit of a sensing element and a control method thereof.

With the signal reading circuit, analog signals such as optical signals, thermal signals, or biomedical signals can be appropriately gained or compensated for subsequent analysis and processing by users. It is even possible to sample the analog signal appropriately to form a discrete signal or a digital signal to facilitate user digital signal processing.

On the system, the efficiency of each block circuit is often regarded as consistent with the standard specifications. However, in terms of actual circuits, the components of each part of the circuit will often have varying degrees of degradation depending on their physical characteristics under extreme environments or after long periods of operation, causing circuit parameters to drift and affecting circuit performance. In the case of a signal reading circuit, the on-resistance value or threshold voltage value of the transistor in the circuit often deviates from the preset value originally designed, causing the output of the signal reading circuit to be out of alignment, and subsequent processing and analysis errors. .

The invention is to provide a signal reading circuit and a control method thereof, so as to overcome the problem of the parameter drift caused by the transistor deterioration and the output of the signal reading circuit being out of alignment.

The present invention discloses a signal reading circuit. The signal reading circuit includes a first transistor, a second transistor, an amplifier, and a resistor. The first terminal of the first transistor is used to receive a first reference voltage. The second terminal of the first transistor is electrically coupled to the first node. The control terminal of the first transistor is used to receive a first reference voltage. The first terminal of the second transistor is electrically coupled to the first node. The second terminal of the second transistor is used to receive a second reference voltage. The control terminal of the second transistor is used to receive the input voltage. The amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically coupled to the first node. The second input terminal is used to receive a second reference voltage. One end of the resistor is electrically coupled to the first input end of the amplifier. The other end of the resistor is electrically coupled to the output end of the amplifier.

The invention discloses a control method of a signal reading circuit. The control method of the signal reading circuit is suitable for a signal reading circuit. The signal reading circuit includes a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input terminal, a second input terminal and an output terminal. One end of the first transistor is electrically coupled to the first input end, and the other end is used to receive a first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is used to receive a second reference voltage. Both ends of the resistor are electrically coupled to the first input terminal and the output terminal, respectively. The control method includes operating the first transistor and the second transistor in a linear region. The current value of the current flowing through the resistor is the difference between the on-current of the first transistor and the on-current of the second transistor. In addition, the voltage across the first transistor is equal to the voltage across the second transistor. The voltage level at the output of the amplifier is related to the resistance of the resistor and the current flowing through the resistor.

To sum up, the present invention provides a signal reading circuit and a method for controlling the same. By using a current subtraction method, the influence of the electrical variation of the element on the signal read value of the sensing element is reduced. With this, even if the parameters of the components in the signal reading circuit are inaccurate, the signal reading circuit can still avoid being affected by the inaccurate parameters, and can still output accurate reading values, which successfully overcomes the component parameter inaccuracy and affects the signal reading. Take the problem of circuit accuracy.

The above description of the contents of this disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical content of the present invention, and according to the content disclosed in this specification, the scope of patent applications and the drawings. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1, which is a schematic circuit diagram of a signal reading circuit according to a first embodiment of the present invention. As shown in FIG. 1, the signal reading circuit 1 includes a first transistor T1, a second transistor T2, an amplifier OP, and a resistor R. The first terminal of the first transistor T1 is used to receive a first reference voltage V1. The second terminal of the first transistor T1 is electrically coupled to the first node N1. The control terminal of the first transistor T1 is used to receive a first reference voltage Vref1. The first terminal of the second transistor T2 is electrically coupled to the first node N1. The second terminal of the second transistor T2 is used to receive a second reference voltage V2. The control terminal of the second transistor T2 is used to receive the input voltage Vin. The amplifier OP has a first input terminal Nin1, a second input terminal Nin2, and an output terminal Nout. The first input terminal Nin1 is electrically coupled to the first node N1. The second input terminal Nin2 is used to receive a second reference voltage Vref2. One end of the resistor R is electrically coupled to the first input terminal Nin1 of the amplifier OP. The other end of the resistor R is electrically coupled to the output terminal Nout of the amplifier OP. The first reference voltage V1 is, for example, a relatively high voltage level, and the second reference voltage V2 is, for example, a relatively low voltage level. In an embodiment, the first reference voltage V1 is a voltage VDD in the system, the second reference voltage V2 is a voltage VSS in the system, the voltage VDD is a high-level reference voltage, and the voltage VSS is a low-level reference voltage. But it is not limited to this. In this embodiment, the first transistor T1 and the second transistor T2 are N-type metal oxide semiconductor transistor (Metal Oxide Semiconductor Field-Effect Transistor, MOSFET), but are not limited thereto.

The first transistor T1 is selectively turned on by the first reference voltage Vref1. The second transistor T2 is selectively turned on by the input voltage Vin. According to the virtual short characteristic of the amplifier OP, the voltage level of the first input terminal Nin1 of the amplifier OP is substantially equal to the voltage level of the second input terminal Nin2, so that the voltage level of the first node N1 is equal to the second reference Voltage Vref2. In addition, the voltage level of the output node Nout is the difference between the voltage level of the first input terminal Nin1 and the voltage level of the second input terminal Nin2 by the amplifier OP, and the voltage level of the output node Nout is related to the amplifier. OP gain value. The relevant characteristics of the amplifier OP are known to those having ordinary knowledge in the technical field, and will not be repeated here. When the amplifier OP has a high open loop gain, the current value of the current IR flowing through the resistor R1 will be approximately the difference between the current IT1 flowing through the first transistor T1 and the current IT2 flowing through the second transistor T2. value.

(1)

(2)In an embodiment, the first transistor T1 and the second transistor T2 are operated in a triode mode. Therefore, the current IT1 and the current IT2 are as follows:

(1)

(2)

代表的是第一電晶體T1與第二電晶體T2的通道寬長比。在此實施例中，第一電晶體T1與第二電晶體T2係具有實質相同的門檻電壓值Vth、實質相同的載子移動率μ_n 、實質相同的閘極氧化層的單位電容C_ox 與實質相同的通道寬長比

。於實務上，上述參數值係為所屬技術領域具有通常知識者在詳閱本說明書後，得以在不脫離本發明之精神的前提下自由調校，並不以上述為限。V _DS1 in the formula (1) is the voltage across the drain and source terminals of the first transistor T1. V _DS2 in the formula (2) is the cross-voltage between the drain terminal and the source terminal of the second transistor T2. Vth in equations (1) and (2) represents the threshold voltage of the first transistor T1 and the second transistor T2, and μ _n represents the load of the first transistor T1 and the second transistor T2. Sub mobility, _Cox represents the unit capacitance of the gate oxide layer of the first transistor T1 and the second transistor T2,

Represents the channel width-to-length ratio of the first transistor T1 and the second transistor T2. In this embodiment, the first transistor T1 and the second transistor T2 have substantially the same threshold voltage value Vth, substantially the same carrier mobility μ _n , and the unit capacitance _{Cox of the} substantially same gate oxide layer and Substantially the same channel width-to-length ratio

. In practice, the above-mentioned parameter values are those with ordinary knowledge in the technical field, which can be adjusted freely without departing from the spirit of the present invention after reading this specification, and is not limited to the above.

(3)On the other hand, the voltage level of the second reference voltage Vref2 is set to an average value of the first reference voltage V1 and the second reference voltage V2, so that V _DS1 in equation (1) is equal to V _DS2 in equation (2) . Here, V _DS1 and V _{DS2 are} replaced by V _{DS for the convenience of} subsequent description. As described above, due to the high input impedance characteristic of the amplifier OP, the current IR is the difference between the current IT1 and the current IT2. Based on the above conditions, the current IR is as follows:

(3)

According to formula (3), the current IR is already independent of the threshold voltage values of the first transistor T1 and the second transistor T2.

(4)Further, the output voltage Vout of the signal reading circuit 1 is expressed as follows:

(4)

Therefore, the output voltage Vout of the signal reading circuit 1 is also independent of the threshold voltage values of the first transistor T1 and the second transistor T2. In other words, even if the first transistor T1 and the second transistor T2 are degraded and the threshold voltage of the first transistor T1 and the second transistor T2 is shifted, the signal reading circuit 1 can generate a more accurate according to the input voltage Vin The output voltage Vout and the output voltage Vout are ideally not affected by the threshold voltage value of the offset. In this embodiment, the output voltage Vout is related to the resistance value of the resistor R1, the current IR flowing through the resistor R1, and the second reference voltage Vref2.

Please refer to FIG. 2, which is a schematic circuit diagram of a signal reading circuit according to a second embodiment of the present invention. Different from the embodiment shown in FIG. 1, the signal reading circuit 2 further includes a sampling switch SW1 and a sampling switch SW2. The two ends of the sampling switch SW1 are electrically coupled to the first input terminal Nin1 and the output terminal Nout of the amplifier OP, respectively. One end of the sampling switch SW2 is electrically coupled to one end of the first transistor T1 and the second transistor T2, and the other end of the sampling switch SW2 is electrically coupled to the first input terminal Nin1 of the amplifier OP. The sampling switch SW1 is controlled by the second clock signal XCK, and the sampling switch SW2 is controlled by the first clock signal CK.

Under such circuit architecture and signal timing, when the first clock signal CK is at a low voltage level, the sampling switch SW1 is turned on and the sampling switch SW2 is not turned on. The output voltage Vout of the signal reading circuit 2 is the same as the second reference voltage Vref2. When the first clock signal CK is at a low voltage level, the sampling switch SW1 is not turned on and the sampling switch SW2 is turned on. The output voltage Vout of the signal reading circuit 2 is the same as the aforementioned formula (4). Thereby, sampling can be performed according to the adjusted input voltage Vin. The sampling switch SW1 and the sampling switch SW2 are, for example, bi-polar junction transistors (BJT), thin-film transistors, metal-oxide-semiconductor transistors, or switching circuits composed of multiple elements. Be restricted.

Please refer to FIG. 3, which is a schematic circuit diagram of a signal reading circuit according to a third embodiment of the present invention. Compared with the embodiment shown in FIG. 2, the signal reading circuit 3 further includes a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 is used to receive the first reference voltage V1. The second terminal of the third transistor T3 is electrically coupled to the first terminal of the first transistor T1. The control terminal of the third transistor T3 is used to receive a third reference voltage Vref3. A first terminal of the fourth transistor T4 is electrically coupled to a second terminal of the second transistor T2. The second terminal of the fourth transistor T4 is electrically coupled to the second reference voltage V2. The control terminal of the fourth transistor T4 is used to receive a fourth reference voltage Vref4. This is similar to connecting the first transistor T1 and the third transistor T3 in series, and connecting the second transistor T2 and the fourth transistor T4 in series. Those skilled in the art can understand that the signal reading circuit can be provided with more transistors connected in series, and the number of the transistors is not limited to the examples.

Please refer to FIGS. 4, 5 and 6. FIG. 4 is a schematic circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention, and FIG. 5 is a signal diagram according to a fifth embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention. The embodiment corresponding to FIG. 4 is similar to the embodiment corresponding to FIG. 2, and the embodiments corresponding to FIG. 5 and FIG. 6 are similar to the embodiment corresponding to FIG. 3. The difference is that in the embodiment corresponding to FIG. 4, the first transistor T1 'is a P-type metal oxide semiconductor transistor. In the embodiment corresponding to FIG. 5, the first transistor T1 'and the third transistor T3' are P-type metal oxide semiconductor transistors. In the embodiment corresponding to FIG. 6, the first transistor T1 'to the fourth transistor T4' are P-type metal oxide semiconductor transistors. With the embodiments shown in FIG. 1 to FIG. 6, the signal reading circuit in this case can be applied to different processes while maintaining the core spirit, which increases practical versatility. The above is just an example, but it is not limited to this.

Please refer to FIG. 7, which is a schematic circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention. In the embodiment corresponding to FIG. 7, compared to the embodiment shown in FIG. 1, the signal reading circuit 7 further includes a sampling switch SW1, a first sampling module 72, and a second sampling module 74. The two ends of the sampling switch SW1 are electrically coupled to the first input terminal Nin1 of the amplifier OP and the output terminal Nout of the amplifier OP, respectively. The sampling switch SW1 selectively turns on the first input terminal Nin1 to the output terminal Nout according to the second clock signal XCK.

The first sampling module 72 includes a first sampling transistor TS1 and a second sampling transistor TS2. The second sampling module 74 includes a third sampling transistor TS3 and a fourth sampling transistor TS4. The first terminal of the first sampling transistor TS1 is used to receive a first reference voltage Vref1. The second terminal of the first sampling transistor TS1 is electrically coupled to the control terminal of the first transistor T1. The control terminal of the first sampling transistor TS1 is used to receive a first clock signal CK. The first terminal of the second sampling transistor TS2 is electrically coupled to the control terminal of the first transistor T1. The second terminal of the second sampling transistor TS2 is used to receive a second reference voltage Vref2. The control terminal of the second sampling transistor TS2 is used to receive the second clock signal XCK.

The second sampling module 74 includes a third sampling transistor TS3 and a fourth sampling transistor TS4. The first terminal of the third sampling transistor TS3 is used to receive the input voltage Vin. The second terminal of the third sampling transistor TS3 is electrically coupled to the control terminal of the second transistor T2. The control terminal of the third sampling transistor TS3 is used to receive the first clock signal CK. The first terminal of the fourth sampling transistor TS4 is electrically coupled to the control terminal of the first transistor T1. The second terminal of the fourth sampling transistor TS4 is used to receive a second reference voltage V2. The control terminal of the fourth sampling transistor TS4 is used to receive the second clock signal XCK.

Under such circuit architecture and signal timing, when the first clock signal CK is at a low voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are not conductive, and the second sampling transistor TS2 and the fourth sampling The transistor TS4 is turned on with the sampling switch SW1. At this time, the second reference voltage Vref2 is provided to the control terminal of the first transistor T1, and the second reference voltage V2 is provided to the control terminal of the second transistor T2. The voltage level of the control terminal of the first transistor T1 is similar to the voltage level of the first node N1, and the first transistor T1 is not turned on. The voltage level of the control terminal of the second transistor T2 is similar to the voltage level of the second terminal of the second transistor T2, and the second transistor T2 is not turned on. By the second sampling transistor T2 and the fourth sampling transistor T4, the voltage level of the control terminal of the first transistor T1 and the voltage level of the control terminal of the second transistor T2 can be stabilized, and the first transistor T1 and the The second transistor T2 is not turned on when the first clock signal CK is at a low voltage level.

(5)

(6)When the first clock signal CK is at a high voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are turned on, and the second sampling transistor TS2, the fourth sampling transistor TS4 and the sampling switch SW1 are not turned on. At this time, the first reference voltage Vref1 is provided to the control terminal of the first transistor T1, and the input voltage Vin is provided to the control terminal of the second transistor T2. Correspondingly, the current IT1 ′ flowing through the first transistor T1 and the current IT2 ′ flowing through the second transistor T2 can be respectively expressed by the following two formulas:

(5)

(6)

(7)The parameters in equations (5) and (6) are as described above, and are not repeated here. However, ΔV refers to a voltage difference caused by the on-resistance of the first sampling transistor TS1 and the on-resistance of the third sampling transistor TS3. Similarly, in this embodiment, the voltage difference caused by the on-resistance of the first sampling transistor TS1 and the voltage difference caused by the on-resistance of the third sampling transistor TS3 are substantially the same, but not limited thereto. At this time, the current IR 'is also expressed as Equation (7):

(7)

In other words, the current IR 'is not related to the on-resistance of the first sampling transistor TS1 and the third sampling transistor TS3, and the current IR' is not related to the threshold voltage of the first transistor T1 and the second transistor T2. As mentioned above, at this time, the output voltage Vout is related to the resistance of the resistor R1, the current IR flowing through the resistor R1, and the second reference voltage Vref2, so the output voltage Vout is also not related to the first sampling transistor TS1 and the third sampling voltage. The on-resistance of the crystal TS3 and the threshold voltage of the first transistor T1 and the second transistor T2.

In the embodiment corresponding to FIG. 7, the signal reading circuit 7 further includes a capacitor C1 and a capacitor C2. The capacitor C1 is electrically coupled to the second terminal of the first sampling transistor TS1 and the first terminal of the second sampling transistor TS2. The capacitor C2 is electrically coupled to the second terminal of the third sampling transistor TS3 and the first terminal of the fourth sampling transistor TS4. The capacitors C1 and C2 are used for voltage stabilization filtering to prevent the voltage level of the control terminal of the first transistor T1 and the voltage level of the control terminal of the second transistor T2 from being disturbed by noise. In one embodiment, the capacitance values of the capacitor C1 and the capacitor C2 are the same, but not limited thereto.

Please refer to FIG. 8, which is a schematic circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention. The embodiment shown in FIG. 8 is similar to the corresponding embodiment in FIG. 7 except that each of the transistor systems in FIG. 8 is a P-type metal oxide semiconductor transistor, and each voltage is adjusted accordingly. . Relevant details are deduced by those with ordinary knowledge in the technical field after reading this specification, and will not be repeated here. The embodiment shown in FIG. 8 has effects similar to those of the embodiment corresponding to FIG. 7, and provides another implementation manner in the manufacturing process.

(8)On the other hand, as shown in Equation (4), the output voltage Vout actually has an offset equal to the second reference voltage Vref2, so that the output voltage Vout cannot be directly the gain input voltage Vin. In practice, the signal reading circuit provided by the present invention may further have a subtraction module to eliminate the offset of the output voltage Vout. Please refer to FIG. 9 together, which is a schematic circuit diagram of a subtraction module according to an embodiment of the present invention. The subtraction module 96 includes a buffer unit 962 and a subtraction unit 964. The input terminal of the buffer unit 962 is used to receive the aforementioned output voltage Vout, and the output terminal of the buffer unit 962 is electrically coupled to the input terminal of the subtraction unit 964. The buffer unit 962 has an amplifier OPS1. The subtraction unit 964 includes resistors RS1 to RS4 and an amplifier OPS2. The non-inverting input terminal of the amplifier OPS1 is electrically coupled to the output terminal of the amplifier OPS2 to form a voltage follower, and the amplifier OPS2 and the resistors RS1 to RS4 are electrically coupled to form a voltage subtractor. One end of the voltage subtractor is the input terminal of the subtraction unit 964, and the other end of the voltage subtractor is used to receive the second reference voltage Vref2. In this embodiment, the resistance values of the resistors RS1 to RS4 are the same as each other. Therefore, the equation (4) and the subtraction module 96 shown in FIG. 9 are used to generate the output voltage Vout ′ according to the output voltage Vout and the second reference voltage Vref2. Among them, the output voltage Vout 'is expressed as follows:

(8)

That is, by the subtraction module 96, the output voltage Vout 'no longer has the offset amount as the output voltage Vout has. In another embodiment, the other end of the subtraction module is used to receive a time-varying signal, for example. At this time, the frequency and waveform of the variable signal are the same as the aforementioned first clock signal CK, and its amplitude can be amplified or reduced according to actual needs. Thereby, in addition to making the output voltage Vout 'no longer have an offset amount associated with the second reference voltage Vref2, the dynamic range of the back-end processing can be improved.

Based on the above, the present invention further provides a pulse sensor. Please refer to FIG. 11, which is a schematic diagram of a pulse detector according to an embodiment of the present invention. The pulse detector 20 has a plurality of detection modules. In this embodiment, the detection modules 202a to 202p arranged in an array are taken as an example for description. However, the number and arrangement of the detection modules in the pulse detector should not be based on the example given. limit.

Please refer to FIG. 12 to further describe the pulse detector. FIG. 12 is a functional block diagram of a detection unit of the pulse detector according to an embodiment of the present invention. FIG. 12 is based on the detection module 202a in FIG. 11. As shown in FIG. 12, the detection module 202a has a sensing unit 2022a and a signal reading circuit 2024a.

The sensing unit 2022a is electrically coupled to the signal reading circuit 2024a. In an embodiment, the sensing unit 2022a is, for example, a piezo-inductor, and the sensing unit 2022a is configured to generate a corresponding piezoelectric signal according to a biological pulse as the aforementioned input signal. The piezoelectric sensor 30 includes, for example, a piezoelectric film made of a polyvinylidene fluoride (PVDF) material, but is not limited thereto.

The signal reading circuit 2024a is, for example, the signal reading circuit described in any one of FIGS. 1 to 9. The relevant operation details are as described above, and will not be repeated here. In this embodiment, the detection module 202a further includes a modulation unit 2026a. The modulation unit 2026a is electrically coupled to the signal reading circuit 2024a. The modulation unit 2026a is configured to generate a modulation signal corresponding to a subsequent circuit specification according to an output signal of the signal reading circuit 2024a for use by the subsequent circuit. Although the modulation unit is a selective design, each detection module does not necessarily have a modulation unit.

As described above, the present invention further provides a control method of a signal reading circuit. Please refer to FIG. 10 for illustration. FIG. 10 is a schematic flowchart of a control method of a signal reading circuit according to an embodiment of the present invention. . The control method of the signal reading circuit shown in FIG. 10 is applicable to the signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input terminal, a second input terminal and an output terminal. One end of the first transistor is electrically coupled to the first input end, and the other end is used to receive a first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is used to receive a second reference voltage. Both ends of the resistor are electrically coupled to the first input terminal and the output terminal, respectively. In the control method, in step S101, the first transistor and the second transistor are operated in a linear region. In step S103, the current value of the current flowing through the resistor is the difference between the on-current of the first transistor and the on-current of the second transistor. In step S105, the voltage across the first transistor is equal to the voltage across the second transistor. The voltage level at the output of the amplifier is related to the resistance of the resistor and the current flowing through the resistor. It should be noted that there is no necessary sequence between step S103 and step S105.

In an embodiment, in the step of making the voltage across the first transistor equal to the voltage across the second transistor, a second reference voltage is provided to the second input terminal. The second reference voltage is Is the average of the first reference voltage and the second reference voltage.

To sum up, the present invention provides a signal reading circuit and a method for controlling the same. By using a current subtraction method, the influence of the electrical variation of the element on the signal read value of the sensing element is reduced. With this, even if the component parameters in the signal reading circuit are inaccurate due to practical conditions, the signal reading circuit can still avoid being affected by the parameter inaccuracy, and can still output accurate reading values, which successfully overcomes the component parameter mismatch Problems that affect the accuracy of the signal reading circuit.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the patent protection scope of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

1 ~ 8‧‧‧Signal reading circuit
72, 82‧‧‧First sampling module
74, 84‧‧‧Second Sampling Module
96‧‧‧ Subtraction Module
962‧‧‧Buffer unit
964‧‧‧ Subtraction Unit
C1, C2‧‧‧capacitor
CK‧‧‧First Clock Signal
IR, IR ', IT1, IT2, IT1', IT2'‧‧‧ Current
N1‧‧‧First Node
Nin1‧‧‧first input
Nin2‧‧‧second input
Nout‧‧‧ output
OP, OPS1, OPS2‧‧‧amplifier
R, RS1 ~ RS4‧‧‧ resistance
SW1, SW2‧‧‧ sampling switch
T1, T1'‧‧‧ the first transistor
T2, T2'‧‧‧Second transistor
T3, T3'‧‧‧Third transistor
T4, T4'‧‧‧ Fourth transistor
TS1‧‧‧first sampling transistor
TS2‧‧‧Second Sampling Transistor
TS3‧‧‧Third sampling transistor
TS4‧‧‧Fourth sampling transistor
V1‧‧‧first reference voltage
V2‧‧‧second reference voltage
Vref1‧‧‧first reference voltage
Vref2‧‧‧second reference voltage
Vref3‧‧‧ third reference voltage
Vref4‧‧‧ Fourth reference voltage
Vin‧‧‧ input voltage
Vout, Vout'‧‧‧ output voltage
XCK‧‧‧Second Clock Signal

FIG. 1 is a schematic circuit diagram of a signal reading circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a signal reading circuit according to a second embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a signal reading circuit according to a third embodiment of the present invention. FIG. 4 is a circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention. FIG. 5 is a circuit diagram of a signal reading circuit according to a fifth embodiment of the present invention. FIG. 6 is a circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention. FIG. 7 is a circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention. FIG. 8 is a circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention. FIG. 9 is a schematic circuit diagram of a subtraction module according to an embodiment of the present invention. FIG. 10 is a schematic flowchart of a control method of a signal reading circuit according to an embodiment of the present invention. FIG. 11 is a schematic diagram of a pulse detector according to an embodiment of the present invention. FIG. 12 is a functional block diagram of a detection unit of a pulse detector according to an embodiment of the present invention.

1‧‧‧Signal reading circuit

IR‧‧‧Current

N1‧‧‧First Node

Nin1‧‧‧first input

Nin2‧‧‧second input

Nout‧‧‧ output

OP‧‧‧Amplifier

R‧‧‧ resistance

T1‧‧‧First transistor

T2‧‧‧Second transistor

V1‧‧‧first reference voltage

V2‧‧‧second reference voltage

Vref1‧‧‧first reference voltage

Vref2‧‧‧second reference voltage

Vin‧‧‧ input voltage

Vout‧‧‧Output voltage

Claims (11)

A signal reading circuit includes a first transistor, a first terminal of the first transistor is used to receive a first reference voltage, and a second terminal of the first transistor is electrically coupled to a first A node, a control terminal of the first transistor is used to receive a first reference voltage; a second transistor, a first terminal of the second transistor is electrically coupled to the first node, the second transistor A second terminal of is used to receive a second reference voltage, a control terminal of the second transistor is used to receive an input voltage; an amplifier having a first input terminal, a second input terminal and an output terminal, The first input terminal is electrically coupled to the first node, the second input terminal is used to receive a second reference voltage; and a resistor, one terminal is electrically coupled to the first input terminal of the amplifier, and the other terminal is electrically connected. Coupled to the output terminal of the amplifier. The signal reading circuit according to claim 1, wherein a current value of the current flowing through the resistor is a difference between an on-current of the first transistor and an on-current of the second transistor. The signal reading circuit according to claim 1, wherein the first transistor and the second transistor operate in a linear region, and the voltage level of the output terminal of the amplifier is related to the resistance value of the resistor and flows through the resistor. And the second reference voltage. The signal reading circuit according to claim 1, wherein the voltage value of the second reference voltage is an average value of the first reference voltage and the second reference voltage. The signal reading circuit according to claim 1, wherein a channel width-length ratio of the first transistor is the same as a channel width-length ratio of the second transistor. The signal reading circuit according to claim 1, further comprising: a third transistor, a first terminal of the third transistor is used to receive the first reference voltage, and a second terminal of the third transistor Electrically coupled to a first terminal of the first transistor, a control terminal of the third transistor being used to receive a third reference voltage; and a fourth transistor, a first terminal of the fourth transistor is Coupled to the second terminal of the second transistor, a second terminal of the fourth transistor is electrically coupled to the second reference voltage, and a control terminal of the fourth transistor is used to receive a fourth reference voltage . The signal reading circuit according to any one of claims 1 to 6, further comprising: a first sampling module, including: a first sampling transistor, a first end of the first sampling transistor is used to receive the first sampling transistor; A reference voltage, a second terminal of the first sampling transistor is electrically coupled to the control terminal of the first transistor, and a control terminal of the first sampling transistor is used to receive a first clock signal; and A second sampling transistor, a first terminal of the second sampling transistor is electrically coupled to the control terminal of the first transistor, and a second terminal of the second sampling transistor is used to receive the second reference Voltage, a control terminal of the second sampling transistor is used to receive a second clock signal, the second clock signal is inverted to the first clock signal; and a second sampling module includes: a first A three sampling transistor, a first terminal of the third sampling transistor is used to receive the input voltage, a second terminal of the third sampling transistor is electrically coupled to the control terminal of the second transistor, and the first A control terminal of the three sampling transistor is used for receiving the first clock signal; and a fourth sampling transistor A transistor, a first terminal of the fourth sampling transistor is electrically coupled to the control terminal of the first transistor, and a second terminal of the fourth sampling transistor is used to receive the second reference voltage. A control terminal of the four sampling transistor is used for the second clock signal; a sampling switch, and two ends of the sampling switch are respectively electrically coupled to the first input terminal of the amplifier and the output terminal of the amplifier, and the sampling The switch selectively conducts the first input terminal to the output terminal according to the second clock signal. The signal reading circuit according to claim 1, further comprising a subtraction module, an input terminal of the subtraction module is electrically coupled to the output terminal of the amplifier, and an output signal of the subtraction module is associated with the resistor. Resistance value and the current flowing through the resistor. A control method of a signal reading circuit is suitable for a signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input terminal, A second input terminal and an output terminal, one end of the first transistor is electrically coupled to the first input terminal, the other terminal is used to receive a first reference voltage, and one end of the second transistor is electrically coupled to the The first input terminal and the other terminal are used to receive a second reference voltage. The two ends of the resistor are electrically coupled to the first input terminal and the output terminal, respectively. The control method includes: operating the first transistor and the first transistor. The two transistors are in the linear region; let the current value of the current flowing through the resistor be the difference between the on-current of the first transistor and the on-current of the second transistor; and The voltage value is equal to the voltage across the second transistor; the voltage level of the output terminal of the amplifier is related to the resistance value of the resistor and the current flowing through the resistor. The control method according to claim 9, wherein in the step of making the voltage across the first transistor equal to the voltage across the second transistor, the method includes providing a second reference voltage to the At the second input terminal, the second reference voltage is an average value of the first reference voltage and the second reference voltage. A pulse detector includes: a plurality of detection modules, each of which includes: a signal reading circuit according to any one of claim 1 to claim 8; and a sensing unit Is electrically coupled to the signal reading circuit, and the sensing unit is configured to generate the input voltage according to a biological pulse.