TWI605683B - Signal reading circuit and control method thereof - Google Patents

Description

Signal reading circuit and control method thereof

The present invention relates to a signal reading circuit and a control method thereof, and more particularly to a signal reading circuit of a sensing element and a control method thereof.

By means of the signal reading circuit, analog signals such as optical signals, thermal signals or biomedical signals can be appropriately gained or compensated for subsequent analysis by the user. It is even possible to appropriately sample the analog signal to form a discrete signal or a digital signal for the user to perform digital signal processing.

On the system, the performance of each block circuit is often considered to be consistent with the standard specification. However, in actual circuits, the components of each part of the circuit often have different degrees of degradation depending on their physical characteristics in an extreme environment or after a long period of operation, causing circuit parameters to drift and affecting circuit performance. In the case of the signal reading circuit, the on-resistance value or the threshold voltage value of the transistor in the circuit often deviates from the preset value originally designed, causing the output of the signal reading circuit to be out of alignment, and the subsequent processing analysis is in error. .

The present invention provides a signal reading circuit and a control method thereof for overcoming the problem that the output of the signal reading circuit is out of alignment due to the drift of the parameters caused by the deterioration of the transistor.

The invention discloses a signal reading circuit. The signal reading circuit comprises a first transistor, a second transistor, an amplifier and a resistor. The first end of the first transistor is configured to receive the first reference voltage. The second end of the first transistor is electrically coupled to the first node. The control end of the first transistor is configured to receive the first reference voltage. The first end of the second transistor is electrically coupled to the first node. The second end of the second transistor is configured to receive a second reference voltage. The control end of the second transistor is for receiving Input voltage. The amplifier has a first input, a second input, and an output. The first input is electrically coupled to the first node. The second input is configured to receive the second reference voltage. One end of the resistor is electrically coupled to the first input of the amplifier. The other end of the resistor is electrically coupled to the output of the amplifier.

The invention discloses a control method of a signal reading circuit, and the control method of the signal reading circuit is applicable to a signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input, a second input, and an output. One end of the first transistor is electrically coupled to the first input end, and the other end is configured to receive the first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is configured to receive the second reference voltage. The two ends of the resistor are electrically coupled to the first input end and the output end, respectively. The control method includes operating a first transistor and a second transistor in a linear region. And the current value of the current flowing through the resistor is the difference between the on current of the first transistor and the on current of the second transistor. And, the voltage across the two ends of the first transistor is equal to the voltage across the two ends of the second transistor. The voltage level at the output of the amplifier is related to the resistance of the resistor and the current flowing through the resistor.

In summary, the present invention provides a signal reading circuit and a control method thereof, which use a current subtraction method to reduce the influence of the electrical variation of the component on the signal reading value of the sensing component. Therefore, even if the parameters of the components in the signal reading circuit are out of alignment, the signal reading circuit can avoid the influence of the misalignment parameter, and can still output an accurate reading value, successfully overcoming the component parameter misalignment and affecting the signal reading. Take the problem of circuit accuracy.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

1~8‧‧‧Signal reading circuit

72, 82‧‧‧ first sampling module

74, 84‧‧‧Second sampling module

96‧‧‧Subtraction module

962‧‧‧buffer unit

964‧‧‧Subtraction unit

C1, C2‧‧‧ capacitor

CK‧‧‧ first clock signal

IR, IR', IT1, IT2, IT1', IT2'‧‧‧ current

N1‧‧‧ first node

Nin1‧‧‧ first input

Nin2‧‧‧ second input

Nout‧‧‧ output

OP, OPS1, OPS2‧‧‧ amplifier

R, RS1~RS4‧‧‧ resistance

SW1, SW2‧‧‧ sampling switch

T1, T1'‧‧‧ first transistor

T2, T2'‧‧‧second transistor

T3, T3'‧‧‧ third transistor

T4, T4'‧‧‧ fourth transistor

TS1‧‧‧ first sampling transistor

TS2‧‧‧Second sampling transistor

TS3‧‧‧ third sampling transistor

TS4‧‧‧ fourth sampling transistor

V1‧‧‧ first reference voltage

V2‧‧‧second reference voltage

Vref1‧‧‧ first reference voltage

Vref2‧‧‧second reference voltage

Vref3‧‧‧ third reference voltage

Vref4‧‧‧ fourth reference voltage

Vin‧‧‧Input voltage

Vout, Vout’‧‧‧ output voltage

XCK‧‧‧ second clock signal

1 is a circuit diagram of a signal reading circuit according to a first embodiment of the present invention.

2 is a circuit diagram of a signal reading circuit according to a second embodiment of the present invention.

3 is a circuit diagram of a signal reading circuit according to a third embodiment of the present invention.

4 is a circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a signal reading circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention.

FIG. 9 is a schematic circuit diagram of a subtraction module according to an embodiment of the invention.

FIG. 10 is a schematic flow chart of a method for controlling a signal reading circuit according to an embodiment of the invention.

FIG. 11 is a schematic diagram of a pulse detector according to an embodiment of the invention.

FIG. 12 is a functional block diagram of one of the detecting units of the pulse detector according to an embodiment of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a signal reading circuit according to a first embodiment of the present invention. As shown in FIG. 1, the signal reading circuit 1 includes a first transistor T1, a second transistor T2, an amplifier OP, and a resistor R. The first end of the first transistor T1 is configured to receive the first reference voltage V1. The second end of the first transistor T1 is electrically coupled to the first node N1. The control end of the first transistor T1 is configured to receive the first reference voltage Vref1. The first end of the second transistor T2 is electrically coupled to the first node N1. The second end of the second transistor T2 is for receiving the second reference voltage V2. The control terminal of the second transistor T2 is for receiving the input voltage Vin. The amplifier OP has a first input terminal Nin1, a second input terminal Nin2 and an output terminal Nout. The first input terminal Nin1 is electrically coupled to the first node N1. The second input terminal Nin2 is configured to receive the second reference voltage Vref2. One end of the resistor R is electrically coupled to the first input terminal Nin1 of the amplifier OP. The other end of the resistor R is electrically coupled to the output terminal Nout of the amplifier OP. The first reference voltage V1 is, for example, a relative high voltage level, and the second reference voltage V2 is, for example, a relatively low voltage level. In one embodiment, the first reference voltage V1 is the voltage VDD in the system, the second reference voltage V2 is the voltage VSS in the system, the voltage VDD is the high level reference voltage, and the voltage VSS is the low level reference voltage. But it is not limited to this. In this embodiment, the first transistor T1 and the second transistor T2 are N-type Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs), but are not limited thereto.

The first transistor T1 is selectively turned on by being controlled by the first reference voltage Vref1. The second transistor T2 is selectively turned on by the input voltage Vin. According to the virtual short characteristic of the amplifier OP, the voltage level of the first input terminal Nin1 of the amplifier OP is substantially equal to the voltage level of the second input terminal Nin2, so that the voltage level of the first node N1 is equal to the second reference. Voltage Vref2. In addition, the voltage level of the output node Nout is the difference between the voltage level of the first input terminal Nin1 and the voltage level of the second input terminal Nin2 through the amplifier OP, and the voltage level of the output node Nout is associated with the amplifier. The gain value of the OP. The relevant characteristics of the amplifier OP are known to those of ordinary skill in the art and will not be described again. When the amplifier OP has a high open loop gain, the current value of the current IR flowing through the resistor R1 is large. The result is the difference between the current IT1 flowing through the first transistor T1 and the current IT2 flowing through the second transistor T2.

In one embodiment, the first transistor T1 and the second transistor T2 are operated in a Triode Mode, so the current IT1 and the current IT2 are as follows:

V _DS1 in the formula (1) is the cross-pressure of the 汲 terminal and the source terminal of the first transistor T1. V _DS2 in the formula (2) is the cross-pressure of the 汲 terminal and the source terminal of the second transistor T2. The Vth in the formulas (1) and (2) represents the threshold voltage values of the first transistor T1 and the second transistor T2, and μ _n represents the loading of the first transistor T1 and the second transistor T2. Sub-movement rate, C _ox represents the unit capacitance of the gate oxide layer of the first transistor T1 and the second transistor T2, Representative of the channel width to length ratio of the first transistor T1 and the second transistor T2. In this embodiment, the first transistor T1 and the second transistor T2 have substantially the same threshold voltage value Vth, substantially the same carrier mobility μ _n , and substantially the same unit capacitance C _ox of the gate oxide layer. Substantially the same channel width to length ratio . In practice, the above-mentioned parameter values are those of ordinary skill in the art, and can be freely adjusted without departing from the spirit of the present invention, and are not limited to the above.

On the other hand, the voltage level of the second reference voltage Vref2 is set to an average value of the first reference voltage V1 and the second reference voltage V2 such that V _DS1 in the equation (1) is equal to V _DS2 in the equation (2) . Here, V _DS1 and V _{DS2 are} replaced with V _DS for subsequent explanation. As previously mentioned, due to the high input impedance characteristic of the amplifier OP, the current IR is the difference between the current IT1 and the current IT2. Based on the above conditions, the current IR is as follows:

According to equation (3), the current IR is already independent of the threshold voltage values of the first transistor T1 and the second transistor T2.

Further, the output voltage Vout of the signal reading circuit 1 is expressed as follows: Vout = Vref 2- R × IR (4)

Therefore, the output voltage Vout of the signal reading circuit 1 is also independent of the threshold voltage values of the first transistor T1 and the second transistor T2. In other words, even if the first transistor T1 and the second transistor T2 are degraded to cause the threshold voltage values of the first transistor T1 and the second transistor T2 to drift, the signal reading circuit 1 can generate more accurate according to the input voltage Vin. The output voltage Vout, and the output voltage Vout, is ideally unaffected by the offset threshold voltage value. In this embodiment, the output voltage Vout is associated with the resistance of the resistor R1, the current IR flowing through the resistor R1, and the second reference voltage Vref2.

Please refer to FIG. 2. FIG. 2 is a schematic circuit diagram of a signal reading circuit according to a second embodiment of the present invention. Different from the embodiment shown in FIG. 1, the signal reading circuit 2 further has a sampling switch SW1 and a sampling switch SW2. The two ends of the sampling switch SW1 are electrically coupled to the first input terminal Nin1 and the output terminal Nout of the amplifier OP, respectively. One end of the sampling switch SW2 is electrically coupled to one end of the first transistor T1 and the second transistor T2. The other end of the sampling switch SW2 is electrically coupled to the first input terminal Nin1 of the amplifier OP. The sampling switch SW1 is controlled by the second clock signal XCK, and the sampling switch SW2 is controlled by the first clock signal CK.

In such a circuit architecture and signal timing, when the first clock signal CK is at a low voltage level, the sampling switch SW1 is turned on and the sampling switch SW2 is not turned on, and the output voltage Vout of the signal reading circuit 2 is the same as the second reference voltage. Vref2. When the first clock signal CK is at a low voltage level, the sampling switch SW1 is not turned on and the sampling switch SW2 is turned on, and the output voltage Vout of the signal reading circuit 2 is the same as the above equation (4). Thereby, sampling can be performed based on the adjusted input voltage Vin. The sampling switch SW1 and the sampling switch SW2 are, for example, bi-polar iunction transistors (BJT), thin film transistors, metal oxide semiconductors. The body transistor or a switching circuit composed of a plurality of elements is not limited herein.

Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of a signal reading circuit according to a third embodiment of the present invention. Compared with the embodiment shown in FIG. 2, the signal reading circuit 3 further has a third transistor T3 and a fourth transistor T4. The first end of the third transistor T3 is for receiving the first reference voltage V1. The second end of the third transistor T3 is electrically coupled to the first end of the first transistor T1. The control terminal of the third transistor T3 is configured to receive the third reference voltage Vref3. The first end of the fourth transistor T4 is electrically coupled to the second end of the second transistor T2. The second end of the fourth transistor T4 is electrically coupled to the second reference voltage V2. The control terminal of the fourth transistor T4 is configured to receive the fourth reference voltage Vref4. By similarly connecting the first transistor T1 and the third transistor T3 in series, and the second transistor T2 and the fourth transistor T4 in series. It will be understood by those skilled in the art that the signal reading circuit can be provided with more transistors in series with each other, and the number of transistors is not limited to the examples.

Referring to FIG. 4, FIG. 5 and FIG. 6, FIG. 4 is a circuit diagram of a signal reading circuit according to a fourth embodiment of the present invention, and FIG. 5 is a signal diagram according to a fifth embodiment of the present invention. FIG. 6 is a circuit diagram of a signal reading circuit according to a sixth embodiment of the present invention. The embodiment corresponding to FIG. 4 is similar to the embodiment corresponding to FIG. 2, and the embodiment corresponding to FIG. 5 and FIG. 6 is similar to the embodiment corresponding to FIG. The difference is that in the embodiment corresponding to Fig. 4, the first transistor T1' is a P-type metal oxide semiconductor transistor. In the embodiment corresponding to Fig. 5, the first transistor T1' and the third transistor T3' are P-type metal oxide semiconductor transistors. In the embodiment corresponding to Fig. 6, the first transistor T1' is such that the fourth transistor T4' is a P-type metal oxide semiconductor transistor. By the embodiment shown in FIG. 1 to FIG. 6, the signal reading circuit of the present invention can be applied to different processes while maintaining the core spirit, which increases the versatility in practice. The above is merely an example and is not limited to this.

Please refer to FIG. 7. FIG. 7 is a schematic circuit diagram of a signal reading circuit according to a seventh embodiment of the present invention. In the embodiment corresponding to FIG. 7, compared to the actual one shown in FIG. For example, the signal reading circuit 7 further has a sampling switch SW1, a first sampling module 72 and a second sampling module 74. The two ends of the sampling switch SW1 are electrically coupled to the first input terminal Nin1 of the amplifier OP and the output terminal Nout of the amplifier OP, respectively. The sampling switch SW1 selectively turns on the first input terminal Nin1 to the output terminal Nout according to the second clock signal XCK.

The first sampling module 72 has a first sampling transistor TS1 and a second sampling transistor TS2. The second sampling module 74 has a third sampling transistor TS3 and a fourth sampling transistor TS4. The first end of the first sampling transistor TS1 is configured to receive the first reference voltage Vref1. The second end of the first sampling transistor TS1 is electrically coupled to the control end of the first transistor T1. The control end of the first sampling transistor TS1 is configured to receive the first clock signal CK. The first end of the second sampling transistor TS2 is electrically coupled to the control end of the first transistor T1. The second end of the second sampling transistor TS2 is configured to receive the second reference voltage Vref2. The control end of the second sampling transistor TS2 is configured to receive the second clock signal XCK.

The second sampling module 74 has a third sampling transistor TS3 and a fourth sampling transistor TS4. The first end of the third sampling transistor TS3 is for receiving the input voltage Vin. The second end of the third sampling transistor TS3 is electrically coupled to the control end of the second transistor T2. The control end of the third sampling transistor TS3 is configured to receive the first clock signal CK. The first end of the fourth sampling transistor TS4 is electrically coupled to the control end of the first transistor T1. The second end of the fourth sampling transistor TS4 is for receiving the second reference voltage V2. The control end of the fourth sampling transistor TS4 is configured to receive the second clock signal XCK.

In the circuit architecture and the signal timing, when the first clock signal CK is at a low voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are not turned on, and the second sampling transistor TS2 and the fourth sampling are performed. The transistor TS4 is turned on with the sampling switch SW1. At this time, the second reference voltage Vref2 is supplied to the control terminal of the first transistor T1, and the second reference voltage V2 is supplied to the control terminal of the second transistor T2. The voltage level of the control terminal of the first transistor T1 is similar to the voltage level of the first node N1, and the first transistor T1 is not turned on. The voltage level of the control terminal of the second transistor T2 is similar to the voltage level of the second terminal of the second transistor T2, and the second transistor T2 Not conductive. By the second sampling transistor T2 and the fourth sampling transistor T4, the voltage level of the control terminal of the first transistor T1 and the voltage level of the control terminal of the second transistor T2 are stabilized, and the first transistor T1 is ensured. The second transistor T2 is not turned on when the first clock signal CK is at a low voltage level.

When the first clock signal CK is at a high voltage level, the first sampling transistor TS1 and the third sampling transistor TS3 are turned on, and the second sampling transistor TS2, the fourth sampling transistor TS4 and the sampling switch SW1 are not turned on. At this time, the first reference voltage Vref1 is supplied to the control terminal of the first transistor T1, and the input voltage Vin is supplied to the control terminal of the second transistor T2. Correspondingly, the current IT1' flowing through the first transistor T1 and the current IT2' flowing through the second transistor T2 can be expressed as follows:

The parameters in the formulas (5) and (6) are as described above, and are not described herein again. ΔV is used to refer to the voltage difference caused by the on-resistance of the first sampling transistor TS1 and the on-resistance of the third sampling transistor TS3. Similarly, in this embodiment, the voltage difference caused by the on-resistance of the first sampling transistor TS1 is substantially the same as the voltage difference caused by the on-resistance of the third sampling transistor TS3, but is not limited thereto. At this time, the current IR' is also expressed as in equation (7):

In other words, the current IR' is independent of the on-resistance of the first sampling transistor TS1 and the third sampling transistor TS3, and the current IR' is independent of the threshold voltages of the first transistor T1 and the second transistor T2. As described above, the output voltage Vout is associated with the resistance of the resistor R1, the current IR flowing through the resistor R1, and the second reference voltage Vref2. Therefore, the output voltage Vout is also independent of the first sampling transistor TS1 and the third sampling battery. On-resistance of crystal TS3 and first transistor The threshold voltage of T1 and the second transistor T2.

In the embodiment corresponding to FIG. 7, the signal reading circuit 7 further has a capacitor C1 and a capacitor C2. The capacitor C1 is electrically coupled to the second end of the first sampling transistor TS1 and the first end of the second sampling transistor TS2. The capacitor C2 is electrically coupled to the second end of the third sampling transistor TS3 and the first end of the fourth sampling transistor TS4. The capacitors C1 and C2 are used for voltage stabilization filtering to prevent the voltage level of the control terminal of the first transistor T1 from being disturbed by the noise level of the control terminal of the second transistor T2. In an embodiment, the capacitance values of the capacitor C1 and the capacitor C2 are the same, but are not limited thereto.

Please refer to FIG. 8. FIG. 8 is a schematic circuit diagram of a signal reading circuit according to an eighth embodiment of the present invention. The embodiment shown in FIG. 8 is similar to the embodiment corresponding to FIG. 7, except that each of the electromorphic systems in FIG. 8 is a P-type metal oxide semiconductor transistor, and the voltages are also adjusted accordingly. . The relevant details are generally obtained by those skilled in the art after reading this specification, and are not described herein. The embodiment shown in Figure 8 has similar efficiencies to the embodiment corresponding to Figure 7, and provides another way of implementing the process.

On the other hand, as shown in the equation (4), the output voltage Vout actually has an offset equal to the second reference voltage Vref2, so that the output voltage Vout cannot be directly the gain input voltage Vin. In practice, the signal reading circuit provided by the present invention may further have a subtraction module to eliminate the offset of the output voltage Vout. Please refer to FIG. 9. FIG. 9 is a schematic circuit diagram of a subtraction module according to an embodiment of the invention. The subtraction module 96 has a buffer unit 962 and a subtraction unit 964. The input end of the buffer unit 962 is configured to receive the output voltage Vout as described above, and the output end of the buffer unit 962 is electrically coupled to the input end of the subtraction unit 964. The buffer unit 962 has an amplifier OPS1. The subtraction unit 964 has resistors RS1 to RS4 and an amplifier OPS2. The non-inverting input terminal of the amplifier OPS1 is electrically coupled to the output end of the amplifier OPS2 to form a voltage follower, and the amplifier OPS2 is electrically coupled to the resistors RS1~RS4 to form a voltage subtractor. One end of the voltage subtractor is the input end of the subtraction unit 964, and the other end of the voltage subtractor is used to receive the second reference voltage Vref2. In this embodiment, the resistance values of the resistors RS1 to RS4 are identical to each other. Therefore, from the subtraction module 96 shown in the formula (4) and FIG. 9, the subtraction module 96 generates the output voltage Vout' according to the output voltage Vout and the second reference voltage Vref2. Among them, the output voltage Vout' is expressed as follows: Vout ' = R × IR (8)

That is, with the subtraction module 96, the output voltage Vout' no longer has an offset as the output voltage Vout has. In another embodiment, the other end of the subtraction module is used to receive a time-varying signal, for example. At this time, the frequency and waveform of the variable signal are the same as the first clock signal CK as described above, and the amplitude thereof can be amplified or reduced as needed. Thereby, in addition to making the output voltage Vout' no longer have an offset as associated with the second reference voltage Vref2, the dynamic range of the back end processing can be improved.

In accordance with the above, the present invention further provides a pulse sensor. Please refer to FIG. 11. FIG. 11 is a schematic diagram of a pulse detector according to an embodiment of the invention. The pulse detector 20 has a plurality of detection modules. In this embodiment, the detection modules 202a-202p arranged in an array are taken as an example for description. However, the number and arrangement of the detection modules in the pulse detector should not be based on the example. limit.

Referring to FIG. 12, the pulse detector is further described. FIG. 12 is a functional block diagram of one of the detecting units of the pulse detector according to an embodiment of the invention. FIG. 12 is illustrated in accordance with the detection module 202a of FIG. As shown in FIG. 12, the detection module 202a has a sensing unit 2022a and a signal reading circuit 2024a.

The sensing unit 2022a is electrically coupled to the signal reading circuit 2024a. In one embodiment, the sensing unit 2022a is, for example, a piezoelectric sensor, and the sensing unit 2022a is configured to generate a corresponding piezoelectric signal according to the pulse of the living body as an input signal as described above. The piezoelectric detector 30 has, for example, a piezoelectric film made of a polyvinylidene fluoride (PVDF) material, but is not limited thereto.

The signal reading circuit 2024a is, for example, a signal reading as described in any of FIGS. 1 to 9. Take the circuit. The relevant actuation details are as described above and will not be described here. In this embodiment, the detection module 202a further has a modulation unit 2026a. The modulation unit 2026a is electrically coupled to the signal reading circuit 2024a. The modulation unit 2026a is configured to generate a modulation signal corresponding to the subsequent circuit specification according to the output signal of the signal reading circuit 2024a for use by the subsequent circuit. However, the modulation unit is an optional design, and each detection module does not necessarily have a modulation unit.

The present invention further provides a method for controlling the signal reading circuit. Referring to FIG. 10, FIG. 10 is a schematic flowchart of a method for controlling a signal reading circuit according to an embodiment of the invention. . The control method of the signal reading circuit as shown in FIG. 10 is applicable to the signal reading circuit. The signal reading circuit has a first transistor, a second transistor, a resistor and an amplifier. The amplifier has a first input, a second input, and an output. One end of the first transistor is electrically coupled to the first input end, and the other end is configured to receive the first reference voltage. One end of the second transistor is electrically coupled to the first input end, and the other end is configured to receive the second reference voltage. The two ends of the resistor are electrically coupled to the first input end and the output end, respectively. The control method is to operate the first transistor and the second transistor in the linear region in step S101. In step S103, the current value of the current flowing through the resistor is a difference between the on current of the first transistor and the on current of the second transistor. In step S105, the voltage across the two ends of the first transistor is equal to the voltage across the second transistor. The voltage level at the output of the amplifier is related to the resistance of the resistor and the current flowing through the resistor. It should be noted that the above steps S103 and S105 have no necessary sequence.

In an embodiment, in the step of making the voltage across the first transistor equal to the voltage across the second transistor, providing the second reference voltage to the second input terminal, the second reference voltage system It is an average value of the first reference voltage and the second reference voltage.

In summary, the present invention provides a signal reading circuit and a control method thereof, which use a current subtraction method to reduce the influence of the electrical variation of the component on the signal reading value of the sensing component. Therefore, even if the component parameters in the signal reading circuit are out of alignment due to the actual situation, the signal reading circuit can avoid the influence of the parameter misalignment, and can still output an accurate reading value, and succeeds. The ground overcomes the problem that the component parameter misalignment affects the accuracy of the signal reading circuit.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧‧Signal reading circuit

IR‧‧‧current

N1‧‧‧ first node

Nin1‧‧‧ first input

Nin2‧‧‧ second input

Nout‧‧‧ output

OP‧‧Amplifier

R‧‧‧resistance

T1‧‧‧first transistor

T2‧‧‧second transistor

V1‧‧‧ first reference voltage

V2‧‧‧second reference voltage

Vref1‧‧‧ first reference voltage

Vref2‧‧‧second reference voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Claims (10)

A signal reading circuit includes: a first transistor, a first end of the first transistor is configured to receive a first reference voltage, and a second end of the first transistor is electrically coupled to a first a node, a control end of the first transistor is configured to receive a first reference voltage; a second transistor, a first end of the second transistor is electrically coupled to the first node, the second transistor a second end is configured to receive a second reference voltage, a control end of the second transistor is configured to receive an input voltage, and an amplifier has a first input end, a second input end, and an output end. The first input end is electrically coupled to the first node, the second input end is configured to receive a second reference voltage, and a resistor is electrically coupled to the first input end of the amplifier, and the other end is electrically The output terminal of the amplifier is coupled to the amplifier; wherein a current value of a current flowing through the resistor is a difference between an on current of the first transistor and an on current of the second transistor. The signal reading circuit of claim 1, wherein the first transistor and the second transistor operate in a linear region, and a voltage level of the output of the amplifier is associated with a resistance of the resistor and flows through the resistor. The current is related to the second reference voltage. The signal reading circuit of claim 1, wherein the voltage value of the second reference voltage is an average of the first reference voltage and the second reference voltage. The signal reading circuit of claim 1, wherein a channel width to length ratio of the first transistor is the same as a channel width to length ratio of the second transistor. The signal reading circuit of claim 1, further comprising: a third transistor, a first end of the third transistor for receiving the first reference voltage, and a second end of the third transistor Electrically coupling a first end of the first transistor, a control end of the third transistor for receiving a third reference voltage, and a fourth transistor, a first end of the fourth transistor The second end of the fourth transistor is electrically coupled to the second reference voltage, and a control end of the fourth transistor is configured to receive a fourth reference voltage. . The signal reading circuit of any one of claims 1 to 5, further comprising: a first sampling module, comprising: a first sampling transistor, a first end of the first sampling transistor is configured to receive the first a reference voltage, a second end of the first sampling transistor is electrically coupled to the control end of the first transistor, and a control end of the first sampling transistor is configured to receive a first clock signal; a second sampling transistor, a first end of the second sampling transistor is electrically coupled to the control end of the first transistor, and a second end of the second sampling transistor is configured to receive the second reference a second sampling signal of the second sampling transistor for receiving a second clock signal, wherein the second clock signal is inverted to the first clock signal; and a second sampling module comprising: a first a third sampling transistor, a first end of the third sampling transistor is configured to receive the input voltage, and a second end of the third sampling transistor is electrically coupled to the control end of the second transistor a control terminal of the three sampling transistor is configured to receive the first clock signal; a fourth sampling transistor, a first end of the fourth sampling transistor is electrically coupled to the control end of the first transistor, and a second end of the fourth sampling transistor is configured to receive the second reference a voltage, a control terminal of the fourth sampling transistor is used for the second clock signal; a sampling switch, the two ends of the sampling switch are electrically coupled to the first input end of the amplifier and the output of the amplifier And the sampling switch selectively turns the first input end to the output end according to the second clock signal. The signal reading circuit of claim 1, further comprising a subtraction module, wherein the input end of the subtraction module is electrically coupled to the output end of the amplifier, and the output signal of the subtraction module is associated with the resistor Resistance and current flowing through the resistor. A signal reading circuit control method is applicable to a signal reading circuit having a first transistor, a second transistor, a resistor and an amplifier, the amplifier having a first input terminal, a second input end and an output end, the first transistor is electrically coupled to the first input end, the other end is configured to receive a first reference voltage, and one end of the second transistor is electrically coupled to the first input end a first input end, the other end is configured to receive a second reference voltage, and the two ends of the resistor are electrically coupled to the first input end and the output end respectively, the control method includes: operating the first transistor and the first a diode is in the linear region; a current value of the current flowing through the resistor is a difference between an on current of the first transistor and an on current of the second transistor; and a cross between the ends of the first transistor The pressure value is equal to the voltage across the two ends of the second transistor; Wherein, the voltage level of the output of the amplifier is related to the resistance of the resistor and the current flowing through the resistor. The control method of claim 8, wherein the step of making the voltage across the first transistor equal to the voltage across the second transistor includes providing a second reference voltage to the The second input terminal is the average of the first reference voltage and the second reference voltage. A pulse detector includes: a plurality of detection modules, each of the detection modules comprising: one of the signal reading circuits according to any one of claim 1 to claim 7; and a sensing unit The signal reading circuit is electrically coupled to the sensing unit, and the sensing unit is configured to generate the input voltage according to a pulse of a living body.