CN106411319A - Clock generation circuit for analog-to-digital converter - Google Patents
Clock generation circuit for analog-to-digital converter Download PDFInfo
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- CN106411319A CN106411319A CN201610825180.6A CN201610825180A CN106411319A CN 106411319 A CN106411319 A CN 106411319A CN 201610825180 A CN201610825180 A CN 201610825180A CN 106411319 A CN106411319 A CN 106411319A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
Abstract
The invention discloses a clock generation circuit for an analog-to-digital circuit, which comprises a clock stabilizing circuit and a two-phase non-overlapping clock generation circuit. The clock stabilizing circuit comprises a clock stabilizing loop and a feedback signal generation circuit. In the feedback signal generation circuit, a control signal is generated by an active low-pass filter to control an N tube current modulation inverter, the clock stabilizing loop is used for generating a stable clock signal, and by a filtering technology and a current modulation technology, accurate modulation on a feedback signal is implemented. In the clock stabilizing loop, by a loop structure, a duty ratio of an output clock can be reduced; under the regulation of the feedback signal, by pulling up a PMOS tube MP1, the duty ratio of the output clock is increased, and finally, the duty ratio of 50% of the output clock is achieved; and the clock is stabilized and vibration is reduced. According to the clock generation circuit disclosed by the invention, the clock stabilizing circuit can be integrated into an ADC circuit; and by adopting the structure disclosed by the invention, clock signal quality can be obviously improved, the strict requirement of an ADC for clock quality is reduced, and a signal-to-noise ratio of the ADC is improved.
Description
Technical field
The present invention relates to field of analog integrated circuit, can be used in digital and analog mixed signal circuit particularly to a kind of
Clock generation circuit structure.
Background technology
During human use's science and technology and wisdom are explored naturally, the signal of acquisition first is analog signal, and calculates
Machine can only process data signal.Need, by analog-digital converter, the analog signal being widely present in nature is quantized into numeral letter
Number be convenient for people to use computer disposal and transmission.Therefore analog-digital converter is the bridge linking up simulated world and digital world,
There is important use value and wide application prospect.
Constantly develop towards the direction of high-speed, high precision with ADC (analog-digital converter), the phase that sampling clock shake causes
Position noise is increasingly becoming the principal element that restriction ADC performance improves to the error that sampling hold circuit causes.Sampling clock
Shake causes the principle that ADC performance reduces as follows, and the shake of sampling clock is a short-term, non-accumulation property variable, represents number
The actual timing position of word signal and the time deviation of its ideal position.The shake that clock signal produces can make the inside electricity of ADC
Road is mistakenly triggered the sampling time, and result causes mistake sampling in amplitude for the analog input signal, thus deteriorating the noise of ADC
Than.Therefore in High Speed High Precision ADC application, stable clock signal is needed to reduce clock phase noise to ADC performance
Impact.
Content of the invention
The invention provides a kind of clock stable technology, by feeding back signal generating circuit, clock stable loop is carried out instead
Feedback is adjusted, and obtains the clock signal output stablizing dutycycle.Clock is realized by low pass filter and N tube current modulation inverter
The reduction of shake.The stable clock signal obtaining does not overlap circuit through two-phase and can obtain the overlapping clock signal of two-phase.
In order to solve above-mentioned technical problem, a kind of clock generation circuit for analog-digital converter proposed by the present invention, bag
Include Clock duty cycle stabilizer and two-phase not overlapping clock-generating circuit, described Clock duty cycle stabilizer includes clock stable loop and feedback
Signal generating circuit.Produce stable clock signal using clock stable loop, produce feedback by feeding back signal generating circuit
Signal is adjusted to clock stable loop, contains active low-pass filter and N tube current is adjusted in feedback signal generating circuit
Phase inverter processed.
Described clock stable loop includes pulling up PMOS MP1,1 two input nand gate NAND1 and 4 phase inverters, 4
Phase inverter is designated as phase inverter INV1, phase inverter INV2, phase inverter INV3 and phase inverter INV4 respectively, and wherein, phase inverter INV1 is defeated
Enter end and connect input clock signal, phase inverter INV1 output end connects an input of two input nand gate NAND1；Two inputs
The output end of NAND gate NAND1 connects the input of phase inverter INV2, and the output end of phase inverter INV2 connects pull-up PMOS MP1
Drain electrode and phase inverter INV3 input, pull-up PMOS MP1 source electrode connect power vd D, pull-up PMOS MP1 grid electricity
Pressure is from feedback signal generating circuit；The output end of phase inverter INV3 connects the input of phase inverter INV4, phase inverter INV4's
Output end connects another input of two input nand gate NAND1.
Described feedback signal generating circuit includes active low-pass filter, N tube current modulation inverter, 3 two inputs with
Not gate, 3 phase inverters and 1 d type flip flop DFF；This 3 NAND gates be designated as respectively two input nand gate NAND2, two input with non-
Door NAND3 and two input nand gate NAND4, this 3 phase inverters are designated as phase inverter INV5, phase inverter INV6 and phase inverter respectively
INV7.
Described active low-pass filter includes 1 operational amplifier A MP1,1 resistance R1 and 1 electric capacity C1；Resistance R1 mono-
End connects output end, resistance R1 other end concatenation operation amplifier AMP1 negative-phase input and the electric capacity C1 mono- of phase inverter INV5
End；The other end concatenation operation amplifier AMP1 output end of electric capacity C1 and NMOS tube MN1 grid；Operational amplifier normal phase input end
Connect reference voltage VREF, operational amplifier A MP1 negative-phase input connects one end of resistance R1 and electric capacity C1, operational amplifier
The output end of AMP1 connects to the other end of electric capacity C1.
Described N tube current modulation inverter includes NMOS tube MN1, NMOS tube MN2 and PMOS MP2, wherein NMOS tube MN2
Constitute phase inverter with PMOS MP2, NMOS tube MN1 is adjusted to the electric current of the N pipe flowing through phase inverter under grid voltage control
Section；PMOS MP2 source electrode connects power vd D, and PMOS MP2 grid connects two input nand gate NAND4 output ends, PMOS
MP2 drain electrode is connected simultaneously to the drain electrode of NMOS tube MN2 and the input stage of phase inverter INV6；The drain electrode of NMOS tube MN2 connects PMOS
The drain electrode of MP2, NMOS tube MN2 grid connects the output end of two input nand gate NAND4, and NMOS tube MN2 source electrode connects NMOS tube
The drain electrode of MN1；The drain electrode of NMOS tube MN1 connects the source electrode of NMOS tube MN2, the grid concatenation operation amplifier of NMOS tube MN1
The output end of AMP1, the source electrode of NMOS tube MN1 connects ground.
In the present invention, input of two input nand gate NAND2 connects the output end of phase inverter INV4, two inputs with
The output end of not gate NAND2 connects the data input pin D of d type flip flop DFF；The input end of clock CLK of d type flip flop DFF connects anti-
The output end of phase device INV1, the output end of d type flip flop DFF connects an input of two input nand gate NAND3, two inputs with
Another input of not gate NAND3 connects the output end of phase inverter INV1, and the output end of two input nand gate NAND3 connects instead
The input of phase device INV5；Two inputs of two input nand gate NAND4 connect phase inverter INV1 and phase inverter INV2 respectively
Output end；The output end of phase inverter INV6 connects the input of phase inverter INV7, and the output end connection two of phase inverter INV7 is defeated
Enter another input of NAND gate NAND2.
Overlapping clock-generating circuit does not include 2 two input nand gates and 5 phase inverters to described two-phase, and wherein, 2 two defeated
Enter NAND gate and be designated as two input nand gate NAND5 and two input nand gate NAND6 respectively, 5 phase inverters are designated as phase inverter respectively
INV8, phase inverter INV9, phase inverter INV10, phase inverter INV11 and phase inverter INV12, the input of phase inverter INV8 connects instead
The output end of phase device INV2, the output end of phase inverter INV8 connects an input of two input nand gate NAND5, two inputs with
Another input of not gate NAND5 connects the output end of phase inverter INV12, and the output end of two input nand gate NAND5 connects
The input of phase inverter INV9；The output end of phase inverter INV9 connects the input of phase inverter INV10, and phase inverter INV10's is defeated
Go out the input that end connects two input nand gate NAND6, another input connection of two input nand gate NAND6 is anti-phase
The output end of device INV2, the output end of two input nand gate NAND6 connects the input of phase inverter INV11；Phase inverter INV11's
Output end connects the input of phase inverter INV12.
Compared with prior art, the present invention is used for the clock generation circuit of analog-digital converter and includes clock stable loop, anti-
Feedback signal produces circuit, two-phase not overlapping clock-generating circuit totally 3 parts.Wherein the clock inputting is believed by clock stable loop
Number it is transformed into the clock signal of stable dutycycle, low jitter；Stable clock signal is not turned two-phase by overlapping clock-generating circuit
The two-phase becoming stable does not overlap clock；Feedback signal generating circuit passes through to gather the clock signal of input and output, is that circuit carries
For feedback adjustment signal, realize clock duty cycle and adjust and low jitter.
Clock duty cycle stabilizer proposed by the present invention can be integrated in adc circuit, vibrates with respect to using low phase noise
The mode of device, structure proposed by the present invention can adjust the input clock signal of optional frequency.Can be by ordinary clock be believed
Number by the circuit structure of the present invention, and then obtain stable, low jitter clock signal.By using knot proposed by the present invention
Structure, can significantly improve clock signal quality, reduce the rigors to clock quality for the ADC, improve ADC signal to noise ratio.
Brief description
Fig. 1 is Clock duty cycle stabilizer operation principle schematic diagram in the present invention；
Fig. 2 is clock stable loop circuit schematic diagram in the present invention；
Fig. 3 is that in the present invention, feedback signal produces circuit theory diagrams；
Fig. 4 is overall Clock duty cycle stabilizer schematic diagram in the present invention；
Fig. 5 is two-phase not overlapping clock-generating circuit in the present invention.
Specific embodiment
With reference to specific embodiment, the present invention is described in further detail.
As shown in figure 1, the mentality of designing of the present invention is, stable clock signal is produced by clock stable loop, use
Clock stable loop is realized reducing output clock signal clk _ OUT dutycycle self by NAND gate NAND1, by pulling up PMOS
Pipe MP1 realizes increasing output clock signal clk _ OUT dutycycle.Produce circuit part by feeding back signal, according to input clock
CLK and output clock CLK_OUT produces feedback signal A, realizes output clock duty cycle is adjusted and clock jitter eliminates.
As shown in figure 1, a kind of clock generation circuit for analog-digital converter proposed by the present invention, including clock stable electricity
Road and two-phase not overlapping clock-generating circuit, described Clock duty cycle stabilizer includes clock stable loop and feedback signal produces electricity
Road.Produce stable clock signal using clock stable loop, produce feedback signal to clock by feeding back signal generating circuit
Stablize loop to be adjusted, in feedback signal generating circuit, contain active low-pass filter and N tube current modulation inverter.
As shown in Fig. 2 in the present invention, described clock stable loop includes pulling up PMOS MP1,1 two input nand gate
NAND1 and 4 phase inverter, 4 phase inverters are designated as phase inverter INV1, phase inverter INV2, phase inverter INV3 and phase inverter respectively
INV4, wherein, phase inverter INV1 input connects input clock signal, and phase inverter INV1 output end connects two input nand gates
One input of NAND1；The output end of two input nand gate NAND1 connects the input of phase inverter INV2, phase inverter INV2
Output end connect the pull-up drain electrode of the PMOS MP1 and input of phase inverter INV3, the source electrode of pull-up PMOS MP1 connects electricity
Source VDD, pull-up PMOS MP1 grid voltage is derived from feedback signal generating circuit；The output end of phase inverter INV3 connects phase inverter
The input of INV4, the output end of phase inverter INV4 connects another input of two input nand gate NAND1.
As shown in figure 3, in the present invention, described feedback signal generating circuit includes active low-pass filter, and N tube current is modulated
Phase inverter, 3 two input nand gates, 3 phase inverters and 1 d type flip flop DFF；This 3 NAND gates be designated as respectively two inputs with non-
Door NAND2, two input nand gate NAND3 and two input nand gate NAND4, this 3 phase inverters are designated as phase inverter INV5, anti-respectively
Phase device INV6 and phase inverter INV7.
Described active low-pass filter includes 1 operational amplifier A MP1,1 resistance R1 and 1 electric capacity C1；Resistance R1 mono-
End connects output end, resistance R1 other end concatenation operation amplifier AMP1 negative-phase input and the electric capacity C1 mono- of phase inverter INV5
End；The other end concatenation operation amplifier AMP1 output end of electric capacity C1 and NMOS tube MN1 grid；Operational amplifier normal phase input end
Connect reference voltage VREF, operational amplifier A MP1 negative-phase input connects one end of resistance R1 and electric capacity C1, operational amplifier
The output end of AMP1 connects to the other end of electric capacity C1.
Described N tube current modulation inverter includes NMOS tube MN1, NMOS tube MN2 and PMOS MP2, wherein NMOS tube MN2
Constitute phase inverter with PMOS MP2, NMOS tube MN1 is adjusted to the electric current of the N pipe flowing through phase inverter under grid voltage control
Section；PMOS MP2 source electrode connects power vd D, and PMOS MP2 grid connects two input nand gate NAND4 output ends, PMOS
MP2 drain electrode is connected simultaneously to the drain electrode of NMOS tube MN2 and the input stage of phase inverter INV6；The drain electrode of NMOS tube MN2 connects PMOS
The drain electrode of MP2, NMOS tube MN2 grid connects the output end of two input nand gate NAND4, and NMOS tube MN2 source electrode connects NMOS tube
The drain electrode of MN1；The drain electrode of NMOS tube MN1 connects the source electrode of NMOS tube MN2, the grid concatenation operation amplifier of NMOS tube MN1
The output end of AMP1, the source electrode of NMOS tube MN1 connects ground.
As shown in figure 4, in described feedback signal generating circuit and clock stable loop, in described feedback signal generating circuit
One input of two input nand gate NAND2 connects the output end of phase inverter INV4 in clock stable loop, two inputs with non-
Door another input of NAND2 connects the output end of phase inverter INV7, and the output end of two input nand gate NAND2 connects D triggering
The data input pin D of device DFF.
The input end of clock CLK of d type flip flop DFF connects the output end of phase inverter INV1 in clock stable loop, d type flip flop
The output end of DFF connects an input of two input nand gate NAND3, another input of two input nand gate NAND3
Connect the output end of phase inverter INV1, the output end of two input nand gate NAND3 connects the input of phase inverter INV5, phase inverter
The output end of INV5 connects to resistance R1.
Two inputs of two input nand gate NAND4 connect phase inverter INV1 and the output end of phase inverter INV2 respectively；
The output end of phase inverter INV6 connects the input of phase inverter INV7, and the output end of two input nand gate NAND4 connects PMOS
MP2 and the grid of NMOS tube MN2.The output end of phase inverter INV7 connects another input of two input nand gate NAND2.
As shown in figure 5, described two-phase overlapping clock-generating circuit does not include 2 two input nand gates and 5 phase inverters, its
In, 2 two input nand gates are designated as two input nand gate NAND5 and two input nand gate NAND6 respectively, and 5 phase inverters are respectively
It is designated as phase inverter INV8, phase inverter INV9, phase inverter INV10, phase inverter INV11 and phase inverter INV12, phase inverter INV8's is defeated
Enter the output end that end connects phase inverter INV2, the output end of phase inverter INV8 connects an input of two input nand gate NAND5
End, another input of two input nand gate NAND5 connects the output end of phase inverter INV12, two input nand gate NAND5's
Output end connects the input of phase inverter INV9；The output end of phase inverter INV9 connects the input of phase inverter INV10, phase inverter
The output end of INV10 connects an input of two input nand gate NAND6, another input of two input nand gate NAND6
End connects the output end of phase inverter INV2, and the output end of two input nand gate NAND6 connects the input of phase inverter INV11；Instead
The output end of phase device INV11 connects the input of phase inverter INV12.
In the clock stable loop of the present invention, as shown in Fig. 2 when feeding back signal A for 1 (high point is put down), pulling up PMOS
Cut-off, output clock CLK_OUT enters NAND gate NAND1 input B after two phase inverters INV3, INV4.In node B
When being all 1 with CLKN, CLK_OUT is 1；When node B and CLKN has one to be 0, CLK_OUT is changed into 0, and clamps down on NAND1
Being output as 1, CLK_OUT self-locking is low level 0.When feeding back signal A for 0, pull-up PMOS MP1 conducting, CLK_OUT becomes high
Level 1.
The feedback signal generating circuit of the present invention as shown in figure 3, Clock duty cycle stabilizer integrated circuit such as Fig. 4, when output
When clock CLK_OUT dutycycle is more than 50%, Node B signal dutycycle, also greater than 50%, leads to node C signal dutycycle to be more than
50%, thus node D signal dutyfactor is more than 50%, node D is operational amplifier A MP1 negative-phase input, therefore amplifier AMP1
Output end node E voltage trends towards reducing.Node E controls NMOS tube modulation inverter, and the reduction of E point voltage leads to NMOS tube MN1
Electric current reduces, and then in the phase inverter of NMOS tube MN2 and PMOS MP2 composition, N tube current reduces, and that is, N pipe modulation inverter is defeated
Egress F voltage is difficult to step-down, leads to F point dutycycle to be more than 50%.Feedback signal A dutycycle is more than 50%, thus pulling up
PMOS ON time reduces, and output clock CLK_OUT high level time reduces, and dutycycle tends to 50%.Conversely, when output
When clock CLK_OUT dutycycle is less than 50%, Node B signal dutycycle is less than 50%, leads to node C signal dutycycle to be less than
50%, thus node D signal dutyfactor is less than 50%, node D is operational amplifier A MP1 negative-phase input, therefore amplifier AMP1
Output end node E voltage trends towards increasing.And then leading to NMOS tube MN1 electric current to increase, in N pipe modulation inverter, N tube current increases
Greatly, i.e. the easy step-down of N pipe modulation inverter output node F voltage, leads to F point dutycycle to diminish.Feedback signal A dutycycle is less than
50%, thus pull up PMOS ON time increasing, output clock CLK_OUT high level time increases, and dutycycle tends to 50%.
In the present invention, two-phase not overlapping clock-generating circuit as shown in figure 5, Clock duty cycle stabilizer output dutycycle
50%th, the clock signal clk _ OUT of low jitter is divided into two-way, and a road enters NAND gate NAND5 after phase inverter INV8 time delay,
Another road is directly entered phase inverter NAND6.NAND gate output signal 0 only when input signal is all 1, NAND gate input letter
One number is had to be output signal 1 when 0, using this characteristic and phase inverter time delay, when realizing output low level two-phase and not overlapping
Clock CLK_A and CLK_B.
Although above in conjunction with figure, invention has been described, the invention is not limited in above-mentioned specific embodiment party
Formula, above-mentioned specific embodiment is only schematically, rather than restricted, and those of ordinary skill in the art is at this
Under bright enlightenment, without deviating from the spirit of the invention, many variations can also be made, these belong to the guarantor of the present invention
Within shield.
Claims (2)
1. a kind of clock generation circuit for analog-digital converter is not it is characterised in that inclusion Clock duty cycle stabilizer and two-phase are handed over
Folded clock generation circuit, described Clock duty cycle stabilizer includes clock stable loop and feedback signal generating circuit；
Described clock stable loop includes pulling up PMOS MP1,1 two input nand gate NAND1 and 4 phase inverters, and 4 anti-phase
Device is designated as phase inverter INV1, phase inverter INV2, phase inverter INV3 and phase inverter INV4 respectively, wherein, phase inverter INV1 input
Connect input clock signal, phase inverter INV1 output end connects an input of two input nand gate NAND1；Two input with non-
The output end of door NAND1 connects the input of phase inverter INV2, and the output end of phase inverter INV2 connects the leakage of pull-up PMOS MP1
Pole and the input of phase inverter INV3, the source electrode of pull-up PMOS MP1 connects power vd D, and pull-up PMOS MP1 grid voltage comes
Self feed back signal generating circuit；The output end of phase inverter INV3 connects the input of phase inverter INV4, the output of phase inverter INV4
End connects another input of two input nand gate NAND1；
Described feedback signal generating circuit includes active low-pass filter, N tube current modulation inverter, 3 two input nand gates,
3 phase inverters and 1 d type flip flop DFF；This 3 NAND gates are designated as two input nand gate NAND2, two input nand gates respectively
NAND3 and two input nand gate NAND4, this 3 phase inverters are designated as phase inverter INV5, phase inverter INV6 and phase inverter respectively
INV7；
Described active low-pass filter includes 1 operational amplifier A MP1,1 resistance R1 and 1 electric capacity C1；Resistance R1 one end is even
Connect the output end of phase inverter INV5, resistance R1 other end concatenation operation amplifier AMP1 negative-phase input and electric capacity C1 one end；Electricity
Hold other end concatenation operation amplifier AMP1 output end and the NMOS tube MN1 grid of C1；Operational amplifier normal phase input end connects
Reference voltage VREF, operational amplifier A MP1 negative-phase input connects one end of resistance R1 and electric capacity C1, operational amplifier A MP1
Output end connect to the other end of electric capacity C1；
Described N tube current modulation inverter includes NMOS tube MN1, NMOS tube MN2 and PMOS MP2, wherein NMOS tube MN2 and
PMOS MP2 constitutes phase inverter, and NMOS tube MN1 is adjusted to the electric current of the N pipe flowing through phase inverter under grid voltage control；
PMOS MP2 source electrode connects power vd D, and PMOS MP2 grid connects two input nand gate NAND4 output ends, and PMOS MP2 is leaked
Pole is connected simultaneously to the drain electrode of NMOS tube MN2 and the input stage of phase inverter INV6；The drain electrode of NMOS tube MN2 connects PMOS MP2
Drain electrode, NMOS tube MN2 grid connects the output end of two input nand gate NAND4, and NMOS tube MN2 source electrode connects NMOS tube MN1
Drain electrode；The drain electrode of NMOS tube MN1 connects the source electrode of NMOS tube MN2, and the grid concatenation operation amplifier AMP1's of NMOS tube MN1 is defeated
Go out end, the source electrode of NMOS tube MN1 connects ground；
One input of two input nand gate NAND2 connects the output end of phase inverter INV4, and two input nand gate NAND2's is defeated
Go out the data input pin D that end connects d type flip flop DFF；The input end of clock CLK of d type flip flop DFF connects the output of phase inverter INV1
End, the output end of d type flip flop DFF connects an input of two input nand gate NAND3, and two input nand gate NAND3's is another
One input connects the output end of phase inverter INV1, and the output end of two input nand gate NAND3 connects the defeated of phase inverter INV5
Enter end；Two inputs of two input nand gate NAND4 connect phase inverter INV1 and the output end of phase inverter INV2 respectively；Anti-phase
The output end of device INV6 connects the input of phase inverter INV7, and the output end of phase inverter INV7 connects two input nand gate NAND2
Another input；
Overlapping clock-generating circuit does not include 2 two input nand gates and 5 phase inverters to described two-phase, wherein, 2 two input with
Not gate is designated as two input nand gate NAND5 and two input nand gate NAND6 respectively, 5 phase inverters be designated as respectively phase inverter INV8,
Phase inverter INV9, phase inverter INV10, phase inverter INV11 and phase inverter INV12, the input of phase inverter INV8 connects phase inverter
The output end of INV2, the output end of phase inverter INV8 connects an input of two input nand gate NAND5, two input nand gates
Another input of NAND5 connects the output end of phase inverter INV12, and the output end connection of two input nand gate NAND5 is anti-phase
The input of device INV9；The output end of phase inverter INV9 connects the input of phase inverter INV10, the output end of phase inverter INV10
Connect an input of two input nand gate NAND6, another input of two input nand gate NAND6 connects phase inverter
The output end of INV2, the output end of two input nand gate NAND6 connects the input of phase inverter INV11；Phase inverter INV11's is defeated
Go out the input that end connects phase inverter INV12.
2. according to claim 1 analog-digital converter clock generation circuit it is characterised in that using clock stable loop produce
Stable clock signal, is adjusted to clock stable loop by feeding back signal generating circuit generation feedback signal.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107870593A (en) * | 2017-11-24 | 2018-04-03 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high speed large dynamic range infrared simulation signal acquisition circuit |
| CN109302179A (en) * | 2018-09-03 | 2019-02-01 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sample logic Circuit with tolerance |
| US20230336182A1 (en) * | 2022-04-18 | 2023-10-19 | Analog Devices International Unlimited Company | Fractional divider with duty cycle regulation and low subharmonic content |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107870593A (en) * | 2017-11-24 | 2018-04-03 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high speed large dynamic range infrared simulation signal acquisition circuit |
| CN109302179A (en) * | 2018-09-03 | 2019-02-01 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sample logic Circuit with tolerance |
| CN109302179B (en) * | 2018-09-03 | 2022-04-19 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sampling logic tolerance circuit |
| US20230336182A1 (en) * | 2022-04-18 | 2023-10-19 | Analog Devices International Unlimited Company | Fractional divider with duty cycle regulation and low subharmonic content |
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| CN106411319B (en) | 2019-09-17 |
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