CN106409899A - Insulation gate bipolar transistor - Google Patents
Insulation gate bipolar transistor Download PDFInfo
- Publication number
- CN106409899A CN106409899A CN201611087110.1A CN201611087110A CN106409899A CN 106409899 A CN106409899 A CN 106409899A CN 201611087110 A CN201611087110 A CN 201611087110A CN 106409899 A CN106409899 A CN 106409899A
- Authority
- CN
- China
- Prior art keywords
- type
- super
- junction structure
- doping
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009413 insulation Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000969 carrier Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 description 20
- 230000000694 effects Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention discloses an insulation gate bipolar transistor. The insulation gate bipolar transistor comprises a substrate, a gate, an emitter, a collector, and a super-junction structure. The gate, the emitter and the collector are located on the substrate. The collector and the emitter are located on both ends of the substrate respectively. The super-junction structure is located on one side, which is close to the collector, of the substrate, and exhausts excess carriers accumulated on the collector side when the transistor is turned off. The technical problem of slow turn-off caused by slow carrier discharge in a non-depleted region in an insulation gate bipolar transistor in the prior art is solved. The trailing current time is effectively shortened, and the turn-off time is reduced.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, to a kind of igbt.
Background technology
Igbt (Insulated Gate Bipolar Transistor, IGBT) is with its low pass state pressure
Fall, high withstand voltage, drive control be simple, easily in parallel the advantages of be widely used in all kinds of power electronic systems, be current high pressure
One of power device field core devices.Its typical application is to control power conversion as power switch, therefore device needs
Meet switch power control ability under certain frequency.Preferably switching device is that requirement possesses the energy being instantaneously switched on or off
Power, but for actual power semiconductor, it is limited by device architecture characteristic, when inevitably presence is opened and turned off
Between, the operating frequency of impact device.
When IGBT device is operated in conducting state, a large amount of carriers of storage inside, to realize preferable conductance modulation effect
Should, reduce conduction voltage drop；In turn off process it is necessary to discharge rapidly the carrier of these storages, realize device off-state
High withstand voltage characteristic.So in turn off process, there is the process that a large amount of process carriers are discharged, in the presence of depletion layer, in a large number
Carrier shifts device onto close to bottom colelctor electrode position due to electric field action, as shown in figure 1, these are accumulated in non-depleted region
Carrier 101 can only be discharged by compound action, lead to IGBT turn off process to form more slow tail currents, have impact on
The turn-off time Tf of device, leads to the turn-off speed of IGBT device slack-off.
That is, IGBT device of the prior art, the carrier that there is non-depleted region is discharged slowly, therefore turn-off speed
Slow technical problem.
Content of the invention
The present invention passes through to provide a kind of igbt, solves IGBT device of the prior art, exists
The carrier of non-depleted region is discharged slowly, therefore the slow technical problem of turn-off speed.
On the one hand, for solving above-mentioned technical problem, the invention provides following technical scheme：
A kind of igbt, including：
Substrate；
Grid, emitter and collector positioned at substrate；Wherein, described colelctor electrode and described emitter stage are respectively positioned at described
The two ends of substrate；
Super-junction structure, near described colelctor electrode side on described substrate, with when described transistor turns off, by institute
State super-junction structure and exhaust the excess carriers being deposited in described colelctor electrode side.
Optionally, the thickness of described super-junction structure is 1/ of the drift region thickness between described colelctor electrode and described emitter stage
2 to 1/4.
Optionally, described super-junction structure is the many p-type columns and Duo Gen N-type column being arranged alternately；Wherein, often adjacent two
Region between root p-type column is a N-type column.
Optionally, the doping content of described p-type column is equal to the doping content of described N-type column.
Optionally, the width of described p-type column is equal to the width of described N-type column.
Optionally, described super-junction structure is connected with described colelctor electrode.
Optionally, the second well region that one end of described substrate is provided with the first well region and is located at described first well region surface；
Described second well region is emitter region；The other end of described substrate is provided with collector area；Described collector area and described first
The doping type of well region is the first doping type；The doping type of described second well region is different from described first doping type
The second doping type.
Optionally, described first doping type is N-type, and described second doping type is p-type；Or, described first doping
Type is p-type, and described second doping type is N-type.
Optionally, described second well region surface has emitter stage to contact；There is collector contact on described collector area surface.
The one or more technical schemes providing in the embodiment of the present application, at least have the following technical effect that or advantage：
The igbt that the embodiment of the present application provides, forms superjunction knot in the close colelctor electrode side of substrate
Structure, when transistor turns off, due to the broadening effect of depletion layer, a large amount of carriers are swept to rapidly described super under electric field action
Junction structure region, and logical super-junction structure quickly scans out device, effectively shortens the tail currents time, reduces the turn-off time.Further,
Because the flat field distribution of described super-junction structure is moreover it is possible to the voltage endurance of boost device, and will not be to device forward conduction pressure
Fall is negatively affected.In addition, described super-junction structure is formed at colelctor electrode side it is not necessary to run through whole device drift region,
It is also easy in technique realize.
Brief description
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, will make to required in embodiment description below
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only embodiments of the invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can also be obtained other according to the accompanying drawing providing
Accompanying drawing.
Fig. 1 is the structure chart of igbt in background technology；
Fig. 2 is the structure chart of igbt in the embodiment of the present application.
Specific embodiment
The embodiment of the present application is passed through to provide a kind of igbt, solves IGBT device of the prior art,
The carrier of the non-depleted region existing is discharged slowly, therefore the slow technical problem of turn-off speed.Achieve effective shortening tail currents
Time, reduce the technique effect of turn-off time.
For solving above-mentioned technical problem, the embodiment of the present application provides the general thought of technical scheme as follows：
The application provides a kind of igbt, including：
Substrate；
Grid, emitter and collector positioned at substrate；Wherein, described colelctor electrode and described emitter stage are respectively positioned at described
The two ends of substrate；
Super-junction structure, near described colelctor electrode side on described substrate, with when described transistor turns off, by institute
State super-junction structure and exhaust the excess carriers being deposited in described colelctor electrode side.
The igbt that the embodiment of the present application provides, forms superjunction knot in the close colelctor electrode side of substrate
Structure, when transistor turns off, due to the broadening effect of depletion layer, a large amount of carriers are swept to rapidly described super under electric field action
Junction structure region, and logical super-junction structure quickly scans out device, effectively shortens the tail currents time, reduces the turn-off time.Further,
Because the flat field distribution of described super-junction structure is moreover it is possible to the voltage endurance of boost device, and will not be to device forward conduction pressure
Fall is negatively affected.In addition, described super-junction structure is formed at colelctor electrode side it is not necessary to run through whole device drift region,
It is also easy in technique realize.
In order to be better understood from technique scheme, below in conjunction with specific embodiment, technique scheme is carried out
Describe in detail it should be understood that the specific features in the embodiment of the present invention and embodiment are detailed to technical scheme
Illustrate, rather than the restriction to technical scheme, in the case of not conflicting, in the embodiment of the present application and embodiment
Technical characteristic can be mutually combined.
In the present embodiment, there is provided a kind of igbt, refer to Fig. 2, as shown in Fig. 2 described crystal
Pipe includes：
Substrate 1；
Positioned at the grid 2 of substrate, emitter stage 3 and colelctor electrode 4；Wherein, described colelctor electrode 4 and described emitter stage 3 position respectively
Two ends in described substrate 1；
Super-junction structure 5, near described colelctor electrode 4 side on described substrate 1, when described transistor turns off, to lead to
Cross described super-junction structure 5 and exhaust the excess carriers being deposited in described colelctor electrode 4 side.
With reference to Fig. 2, the igbt introducing the present embodiment offer respectively improves device turn-off speed
Principle and structure.
First, introduce the principle that described igbt improves device turn-off speed.
When IGBT device is operated in conducting state, a large amount of carriers of storage inside, therefore in turn off process, will exist
The process that a large amount of carriers are discharged, in the presence of depletion layer broadening, a large amount of carriers are due to the round dot in electric field action such as Fig. 1
Shown, it is pulled to device close to bottom colelctor electrode 4 neighbouring position, the IGBT device in the application, define in colelctor electrode side super
Junction structure 5, due to charge balance concept, super-junction structure 5 longitudinally and is laterally forming depletion region extension simultaneously, so can be quick
Scan out the excess carriers being accumulated in device collector bottom, compare in traditional structure carrier this action time in bottom zone
The slow compound action in domain is very fast it is possible to effectively shorten the time of tail currents, reduces the turn-off time.
Next, introducing the structure of described igbt.
In the embodiment of the present application it is contemplated that the simplicity of technique realization, described super-junction structure 5 and described collection can be set
Electrode 4 connects, and forms described super-junction structure 5 in order to inject from colelctor electrode 4 side.
Specifically, due to IGBT device, this can increase field cut-off cushion (Field Stop, FS in processing technique
Layer) and the back side injection etc. multistep back process, so utilize device back side processing technique, increase superjunction preparation technology so that it may
To realize described super-junction structure 5.
Specifically, described super-junction structure 5 is the many p-type columns and Duo Gen N-type column being arranged alternately；Wherein, every phase
Region between adjacent two p-type columns is a N-type column.It may also be said that often the region between adjacent two N-type columns is one
Root p-type column.
Preferably, the doping content of described p-type column is equal to the doping content of described N-type column.The width of described p-type column
Degree is equal to the width of described N-type column.Equal with the electric field intensity in the guarantee each region of described super-junction structure 5, improve carrier row
While going out efficiency, do not affect device operational characteristics.
It should be noted that the doping content of super-junction structure 5 and superjunction post width, can carry out and device according to process condition
Part actual design size is selected, and can reach charge balance.In general, doping content turns off soon when high, but is easier to
Puncture, turn off relatively slow when doping content is low, but be difficult to puncture.
In the embodiment of the present application, due to usual IGBT device be operated in off-state bias voltage effect under when, emitter stage 3
About 2/3rds length of the drift region that the depletion layer broadening of side can exceed, therefore three in the drift region near colelctor electrode 4 side
Region about/mono- length, can accumulate substantial amounts of excess carrier because no depletion layer acts on.Therefore can arrange described
The thickness h of super-junction structure 5 is 1/2 to 1/4 of the drift region thickness between described colelctor electrode 4 and described emitter stage 3, to ensure
The excess carriers scanning out from depletion layer enter super-junction structure 5 region, and are realized the base of quick depletion action by super-junction structure 5
On plinth, it is to avoid realize the complexity of the manufacturing process of super-junction structure entirely running through, simultaneously also can effectively utilizes super-junction structure 5 fast
The characteristic that speed exhausts.
Preferably, the thickness h that can arrange described super-junction structure 5 is drift between described colelctor electrode 4 and described emitter stage 3
Move the 1/3 of area's thickness.
In the embodiment of the present application, as shown in Fig. 2 one end of described substrate 1 is provided with the first well region 6 and is located at described the
Second well region on one well region 6 surface；Described second well region is the region of emitter stage 3；
The other end of described substrate is provided with collector area；Described collector area and the doping type of described first well region 6
It is the first doping type；The doping type of described second well region is the second doping classes different from described first doping type
Type.
In specific implementation process, described first doping type is N-type, and described second doping type is p-type；Or, institute
Stating the first doping type is p-type, and described second doping type is N-type.
Further, there is emitter stage contact 7 on described second well region surface；There is collector contact 8 on described colelctor electrode 4 area surface.
Described emitter stage contact 7 and described collector contact 8 can be metal or polysilicon.
Specifically, described igbt passes through to arrange super-junction structure 5 in bottom colelctor electrode 4 side, using super
The rapidly depleting characteristic of junction structure, can close in device and have no progeny, will be deposited in the quick of the excess carriers of bottom colelctor electrode 4 side
Exhaust, realize the effect that IGBT device rapidly switches off.Meanwhile, the device realized using this structure, because only need to realize partly surpassing
Junction structure, without running through whole drift region, technique is realized relatively easy.Additionally, this transistor is being realized rapidly switching off effect
Meanwhile, its conduction voltage drop parameter is unaffected, does not need to sacrifice other parameters characteristic, and super-junction structure can also to improve it resistance to
Pressure energy power is it is achieved that the optimization of parametric synthesis performance.
Technical scheme in above-mentioned the embodiment of the present application, at least has the following technical effect that or advantage：
The igbt that the embodiment of the present application provides, forms superjunction knot in the close colelctor electrode side of substrate
Structure, when transistor turns off, due to the broadening effect of depletion layer, a large amount of carriers are swept to rapidly described super under electric field action
Junction structure region, and logical super-junction structure quickly scans out device, effectively shortens the tail currents time, reduces the turn-off time.Further,
Because the flat field distribution of described super-junction structure is moreover it is possible to the voltage endurance of boost device, and will not be to device forward conduction pressure
Fall is negatively affected.In addition, described super-junction structure is formed at colelctor electrode side it is not necessary to run through whole device drift region,
It is also easy in technique realize.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (9)
1. a kind of igbt is it is characterised in that include：
Substrate；
Grid, emitter and collector positioned at substrate；Wherein, described colelctor electrode and described emitter stage are located at described substrate respectively
Two ends；
Super-junction structure, near described colelctor electrode side on described substrate, with when described transistor turns off, by described super
Junction structure exhausts the excess carriers being deposited in described colelctor electrode side.
2. transistor as claimed in claim 1 is it is characterised in that the thickness of described super-junction structure is described colelctor electrode and described
1/2 to 1/4 of drift region thickness between emitter stage.
3. transistor as claimed in claim 1 is it is characterised in that described super-junction structure is many p-type columns being arranged alternately
With many N-type columns；Wherein, often the region between adjacent two p-type columns is a N-type column.
4. transistor as claimed in claim 3 is it is characterised in that the doping content of described p-type column is equal to described N-type column
Doping content.
5. transistor as claimed in claim 3 is it is characterised in that the width of described p-type column is equal to the width of described N-type column
Degree.
6. transistor as claimed in claim 1 is it is characterised in that described super-junction structure is connected with described colelctor electrode.
7. transistor as claimed in claim 1 it is characterised in that：
The second well region that one end of described substrate is provided with the first well region and is located at described first well region surface；Described second well region
For emitter region；
The other end of described substrate is provided with collector area；The doping type of described collector area and described first well region is the
One doping type；The doping type of described second well region is second doping types different from described first doping type.
8. transistor as claimed in claim 7 it is characterised in that described first doping type be N-type, described second doping class
Type is p-type；Or, described first doping type is p-type, and described second doping type is N-type.
9. transistor as claimed in claim 7 is it is characterised in that described second well region surface has emitter stage to contact；Described collection
There is collector contact on electrode district surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611087110.1A CN106409899A (en) | 2016-12-01 | 2016-12-01 | Insulation gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611087110.1A CN106409899A (en) | 2016-12-01 | 2016-12-01 | Insulation gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106409899A true CN106409899A (en) | 2017-02-15 |
Family
ID=58084773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611087110.1A Pending CN106409899A (en) | 2016-12-01 | 2016-12-01 | Insulation gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106409899A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449202A (en) * | 2018-10-30 | 2019-03-08 | 广州工商学院 | One kind is inverse to lead bipolar junction transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137679A (en) * | 2011-11-21 | 2013-06-05 | 上海华虹Nec电子有限公司 | Insulated gate bipolar transistor device structure and manufacture method thereof |
| CN104241126A (en) * | 2014-09-17 | 2014-12-24 | 中航（重庆）微电子有限公司 | Groove type IGBT and manufacturing method |
| US20150187869A1 (en) * | 2013-12-27 | 2015-07-02 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
| CN104882475A (en) * | 2015-05-25 | 2015-09-02 | 江苏物联网研究发展中心 | Double channel super junction IGBT (Insulated Gate Bipolar Translator) |
-
2016
- 2016-12-01 CN CN201611087110.1A patent/CN106409899A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137679A (en) * | 2011-11-21 | 2013-06-05 | 上海华虹Nec电子有限公司 | Insulated gate bipolar transistor device structure and manufacture method thereof |
| US20150187869A1 (en) * | 2013-12-27 | 2015-07-02 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
| CN104241126A (en) * | 2014-09-17 | 2014-12-24 | 中航（重庆）微电子有限公司 | Groove type IGBT and manufacturing method |
| CN104882475A (en) * | 2015-05-25 | 2015-09-02 | 江苏物联网研究发展中心 | Double channel super junction IGBT (Insulated Gate Bipolar Translator) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449202A (en) * | 2018-10-30 | 2019-03-08 | 广州工商学院 | One kind is inverse to lead bipolar junction transistor |
| CN109449202B (en) * | 2018-10-30 | 2021-10-22 | 广州工商学院 | Reverse conducting bipolar transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2365531B1 (en) | Semiconductor device and power conversion apparatus using the same | |
| US20140209972A1 (en) | Semiconductor device | |
| CN110767753B (en) | SiC power device | |
| CN104282759A (en) | Super junction MOSFET, method of manufacturing the same, and complex semiconductor device | |
| CN105122458A (en) | Semiconductor device and manufacturing method therefor | |
| CN102842609A (en) | Terminal extension structure and manufacturing method thereof | |
| JP2016162855A (en) | Semiconductor device and power conversion device using the same | |
| CN108574016A (en) | A kind of the silicon carbide DSRD devices and Pulsed power generator of super-junction structure | |
| CN102446966A (en) | IGBT ((Insulated Gate Bipolar Transistor) structure of integrated anti-parallel diode and manufacturing method thereof | |
| CN106920840B (en) | Method for eliminating tailing current of transverse insulated gate bipolar transistor | |
| CN102263125A (en) | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides | |
| CN106409899A (en) | Insulation gate bipolar transistor | |
| CN110518060B (en) | Lateral variable doped junction termination structure | |
| JP2007150121A (en) | Semiconductor device for power and power-conversion device using the same | |
| CN108598152B (en) | Super junction device terminal structure | |
| JP6318061B2 (en) | Semiconductor device | |
| US9306045B2 (en) | Semiconductor power device | |
| WO2023109124A1 (en) | Igbt device | |
| KR102585094B1 (en) | Separated Buffer Super Junction IGBT | |
| CN112466935B (en) | RC-IGBT device with polycrystalline silicon electronic channel of collector electrode | |
| CN103928508A (en) | Low-noise low-loss insulated gate bipolar transistor | |
| CN106783946A (en) | A kind of igbt | |
| US8716811B2 (en) | Semiconductor device | |
| CN107342286B (en) | Transverse RC-IGBT device with surface double-gate control | |
| Liu et al. | Development of 8-inch key processes for insulated-gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170215 |