CN106406745B - Method and device for maintaining Cache data consistency according to directory information - Google Patents
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- CN106406745B CN106406745B CN201510447072.5A CN201510447072A CN106406745B CN 106406745 B CN106406745 B CN 106406745B CN 201510447072 A CN201510447072 A CN 201510447072A CN 106406745 B CN106406745 B CN 106406745B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
Abstract
The invention discloses a method and a device for maintaining Cache data consistency according to directory information. The method comprises the following steps: receiving a data block state change request; determining a designated data block in a main memory system area according to the data block state change request; determining a target processor according to directory information stored in the main memory, wherein the target processor is a processor which stores a specified data block into a processor Cache; and sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the cached specified data block in the Cache of the target processor. By adopting the method and the device provided by the invention, the directory information is stored in the main memory, thereby avoiding using the directory memory space of the interconnection chip and reducing the difficulty of NUMA system design and realization.
Description
Technical Field
The invention relates to the field of data block processing, in particular to a method and a device for maintaining Cache data consistency according to directory information.
Background
A distributed shared memory multiprocessor system refers to a data block processing system composed of one common memory and a plurality of processors. Among many types of distributed shared memory multiprocessor systems, a Non-uniform memory Access Architecture (NUMA) system is the most commonly used distributed shared memory multiprocessor system due to its convenient programming environment and good expandability.
NUMA systems typically consist of multiple multiprocessor systems, where each subsystem may consist of a Main Memory (Main Memory) and several processors (processors), and the space of the Main Memory may be shared among the various sub-processing systems. Because each processor in the NUMA system shares the main memory, each processor may rewrite any data block in the main memory, and each processor Cache memory (Cache) may also Cache any data block in the main memory, so that a situation may occur that after a certain data block in the main memory is cached by the first processor Cache, the data block is rewritten by the second processor, resulting in inconsistency between data cached by the first processor Cache and data in the main memory. Since the greater the number of processors in a NUMA system, the greater the possibility that data cached by the processor Cache will be inconsistent with data in the main memory, the problem of processor Cache (Cache) data consistency becomes a critical issue that limits the size and scalability of the NUMA system.
In the prior art, NUMA systems generally utilize directory information stored on an interconnect chip to ensure consistency of Cache data. Specifically, an interconnection chip is usually provided in an existing NUMA system, and a directory storage space is opened in the interconnection chip, and the directory storage space is used for storing directory information, and the directory information is used for recording whether each data block in a main memory is cached by a processor Cache, which processor Cache is cached by, and the like. When a certain specified processor needs to modify a certain data block in a main memory, firstly, determining whether the data block is cached in the Cache of the processor according to directory information; when the data block cached in the Cache of the target processor is found, the designated processor can send a point-to-point message to the target processor so as to invalidate the cached data block in the Cache of the target processor, and after the point-to-point message is sent, the designated processor can modify the data block. By adopting the method, the data blocks cached in the caches of the processors in the system can be ensured to be consistent with the data blocks in the main memory, so that the problem of the consistency of the Cache data of the processors is solved.
When the directory information is used to ensure the consistency of Cache data of the processors, the data volume of the directory information is increased due to the expansion of the NUMA system and the increase of the number of the processors, and the storage space of the directory memory needs to be increased along with the increase of the data volume of the directory information. Therefore, the existing method is adopted to solve the problem of consistency of Cache data of the processor, when the NUMA system is large in scale, the interconnection chip needs to use a large directory memory space to store directory information and has large memory, and the increase of the directory memory space is accompanied by the cost of complicated interconnection chip structure and great increase of chip area. The complicated structure and the large increase of the chip area of the interconnected chip increase the difficulty of designing and implementing the NUMA system.
Disclosure of Invention
The embodiment of the invention provides a method and a device for maintaining Cache data consistency according to directory information, which can reduce the difficulty of NUMA system design and implementation.
In a first aspect, an embodiment of the present invention provides a method for maintaining Cache data consistency according to directory information, where the directory information is stored in a main memory, and the directory information is used to record a condition that a data block in a main memory system area is cached by a Cache memory of each processor, and the method includes: receiving a data block state change request; determining a designated data block in a main memory system area according to the data block state change request; determining a target processor according to directory information stored in the main memory, wherein the target processor is a processor which stores a specified data block into a processor Cache; and sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the cached specified data block in the Cache of the target processor.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the determining a target processor according to directory information stored in the main memory includes: detecting whether specified directory information corresponding to the specified data block exists in a directory area of the main memory, wherein the directory area of the main memory is used for storing the directory information; and when the specified directory information exists in the directory area of the main memory, determining the target processor according to the specified directory information.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the determining a target processor according to directory information stored in the main memory includes: detecting whether appointed directory information corresponding to the appointed data block exists in a directory cache of an interconnection chip; when the specified directory information does not exist in the directory cache of the interconnection chip, detecting whether the specified directory information corresponding to the specified data block exists in the directory area of the main memory; and when the specified directory information exists in the directory area of the main memory, determining the target processor according to the specified directory information.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the second aspect, the method further includes: and when the specified directory information exists in the directory cache of the interconnected chip, determining the target processor according to the specified directory information.
With reference to the second possible implementation manner of the first aspect, in a fourth possible implementation manner of the second aspect, the method further includes: and when the specified directory information does not exist in the directory cache of the interconnected chip, updating the directory information in the directory cache.
With reference to any one of the second to fourth possible implementation manners of the first aspect, in a fifth possible implementation manner of the second aspect, the directory information stored in the directory cache is generated by mapping the directory information in the directory area of the main memory in a multi-way set associative manner.
With reference to the first aspect or any one of the first to fifth possible implementation manners of the first aspect, in a sixth possible implementation manner of the first aspect, the sending a state change indication to the target processor includes: when the data block state change request is a data block rewriting request, sending a failure indication to the target processor, wherein the failure indication is used for indicating the target processor to fail the specified data block cached in the Cache of the target processor; or when the data block state change request is a data block sharing request, sending a sharing indication to the target processor, wherein the sharing indication is used for indicating the target processor to modify the specified data block cached in the Cache of the target processor into a sharing mode.
With reference to the first aspect or any one of the first to sixth possible implementation manners of the first aspect, in a seventh possible implementation manner of the first aspect, the directory information includes an access status field, an information status field, and a Cache indication field, where the access status field is used to indicate whether the directory information is being accessed, the information status field is used to indicate a status of the directory information, and the Cache indication field is used to indicate a status that a data block corresponding to the directory information is cached by a processor Cache.
In a second aspect, an embodiment of the present invention provides an apparatus for maintaining Cache data consistency according to directory information, where the directory information is stored in a main memory, and the directory information is used to record a condition that a data block in a main memory system area is cached by a Cache memory of each processor, and the apparatus includes: a receiving unit, configured to receive a data block state change request; a specified data block determination unit for determining a specified data block in the main memory system area according to the data block state change request; the target processor determining unit is used for determining a target processor according to the directory information stored in the main memory, wherein the target processor is a processor which stores the specified data block into a processor Cache; and the sending unit is used for sending a state change instruction to the target processor, and the data block state change request is used for requesting the target processor to change the state of the specified data block cached in the Cache of the target processor.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the target processor determining unit includes: a first detecting subunit, configured to detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory, where the directory area of the main memory is used to store the directory information; a first determining subunit, configured to determine the target processor according to the specified directory information when the specified directory information exists in the directory area of the main memory.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the target processor determining unit includes: the second detection subunit is used for detecting whether the directory cache of the interconnection chip has the specified directory information corresponding to the specified data block; a third detecting subunit, configured to detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory when the specified directory information does not exist in a directory cache of an interconnect chip; a second determining subunit, configured to determine the target processor according to the specified directory information when the specified directory information exists in the directory area of the main memory.
With reference to the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the second determining subunit is further configured to determine the target processor according to the specified directory information when the specified directory information exists in a directory cache of an interconnection chip.
With reference to the second possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the target processor determining unit further includes: an updating subunit, configured to update the directory information in the directory cache of the interconnection chip when the specified directory information does not exist in the directory cache
With reference to any one of the second to fourth possible implementation manners of the second aspect, in a fifth possible implementation manner of the second aspect, the directory information stored in the directory cache is generated by mapping the directory information in the directory area of the main memory in a multi-way set associative manner.
With reference to the second aspect or any one of the first to fifth possible implementation manners of the second aspect, in a sixth possible implementation manner of the second aspect, the sending unit is configured to send a failure indication to the target processor when the data block state change request is a data block rewrite request, where the failure indication is used to indicate the target processor to fail the specified data block cached in the target processor Cache; or, the shared instruction is used to instruct the target processor to modify the specified data block cached in the Cache of the target processor into a shared mode.
With reference to the second aspect or any one of the first to sixth possible implementation manners of the second aspect, in a seventh possible implementation manner of the second aspect, the directory information includes an access status field, an information status field, and a Cache indication field, where the access status field is used to indicate whether the directory information is being accessed, the information status field is used to indicate a status of the directory information, and the Cache indication field is used to indicate a status that a data block corresponding to the directory information is cached by a processor Cache.
In the embodiment of the invention, a data block state change request is received; determining a designated data block in a main memory system area according to the data block state change request; determining a target processor according to directory information stored in the main memory, wherein the directory information is used for recording the condition that data blocks in a main memory system area are cached by each processor Cache, and the target processor refers to a processor which stores specified data blocks into the processor caches; and sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the cached specified data block in the Cache of the target processor. By adopting the embodiment of the invention, the directory information is stored in the main memory, so that the directory storage space of the interconnection chip can be prevented from being used for storing the directory information, and the difficulty in designing and realizing the NUMA system is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a flowchart of an embodiment of a method for maintaining Cache data consistency according to directory information according to the present invention;
FIG. 2 is a diagram illustrating the structure of directory information according to the present invention;
FIG. 3 is a diagram illustrating an embodiment of an apparatus for maintaining Cache data consistency according to directory information according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the non-uniform Memory access architecture system of the present invention may be formed by at least one Multiprocessor system (Multiprocessor Systems), wherein each Multiprocessor system may include a Main Memory (Main Memory) and at least two processors, and directory information may be stored in the Main Memory. The main memory comprises a directory area and a system area, wherein the directory area is used for storing directory information, the system area is used for storing data blocks required to be stored in the main memory, and each directory area can be used for storing the directory information of the data blocks in the main memory system area to which the directory area belongs and can also be used for storing the directory information of the data blocks in other main memory system areas.
Referring to fig. 1, a schematic flow chart of an embodiment of the method for maintaining Cache data consistency according to directory information in the present invention is shown. The method comprises the following steps:
A processor in a NUMA system first receives a data block status change request, which may be sent by an application in the system. The data block state change request may be a data block rewriting request, a data block sharing request, or the like, where the data block rewriting request is used to request to rewrite a certain data block in the main memory, and the data block sharing request is used to request to share a certain data block in the main memory.
And 102, determining the specified data block in the main memory system area according to the data block state change request.
After receiving the data block state change request, the processor first determines which data block in the main memory system area needs to be rewritten according to the data block state change request.
For example, when the data block state change request carries an address range of a specified data block, the data block in the address range may be considered as the specified data block. When the data block state change request carries the start address of the specified data block and the size of the specified data block can be determined according to the data block state change request, the specified data block can be determined according to the start address of the specified data block and the size of the specified data block.
After the specified data block is determined, the processor may detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory; and when the specified directory information exists in the main memory directory area, determining the target processor according to the specified directory information.
Each piece of directory information in the main memory directory area may correspond to a data block with a fixed size in the main memory, and the size of the data block may be preset according to needs, for example, may be the same as the size of each Cache line (Cacheline) in the processor Cache.
The directory information in the directory area may be mapped in a multi-way set associative manner using locality principles. By adopting a locality principle and mapping and generating directory information in a multi-path group connection mode, only the directory information corresponding to the data blocks which are possibly cached by the Cache of the processor in the main memory can be generated, and the directory information corresponding to all the data blocks in the main memory does not need to be generated, so that the data volume of the directory information can be greatly reduced, and the space occupied by the directory area is reduced; and the information corresponding to the data block with the fixed address in the system area can be stored in the fixed address of the directory area, and the storage address of the directory information corresponding to the data block can be determined very tolerant according to the address of the data block, so that the searching speed of the directory information can be increased.
The structure of the directory information may be as shown in fig. 2, where the directory information includes an access status field, an information status field, and a Cache indication field, where the access status field is used to indicate whether the directory information is being accessed, the information status field is used to indicate the status of the directory information, and the Cache indication field is used to indicate a condition that a data block corresponding to the directory information is cached by a processor Cache. In general, the length of the access status field may be 1bit, the length of the information status field may be 3 bits, and the length of the cache indication field may be 4 bits. The condition that the data block corresponding to the directory information is cached by the processor Cache refers to whether the data block corresponding to the directory information is cached by the processor Cache, which processor Cache is cached by the processor Cache, and the like.
In order to speed up the processing speed of data block rewriting, the NUMA system may also include an interconnect chip, and the interconnect chip is provided with a directory cache for storing directory information in a directory area of the main memory in a cache manner. In order to reduce the space of the directory cache, the directory information stored in the directory cache is generated by mapping the directory information in the directory area of the main memory in a multi-way set associative manner.
Therefore, after the specified data block is determined, the processor may also detect whether specified directory information corresponding to the specified data block exists in a directory cache of the interconnection chip; and when the specified directory information exists in the directory cache of the interconnected chip, determining the target processor according to the specified directory information. When the specified directory information does not exist in the directory cache of the interconnection chip, the processor detects whether the specified directory information corresponding to the specified data block exists in the directory area of the main memory; and when the specified directory information exists in the main memory directory area, determining the target processor according to the specified directory information.
If the directory information comprises an access status field, an information status field and a cache indication field, when the target processor is determined according to the specified directory information, the content of the cache indication field of the specified directory information can be analyzed, and the target processor is determined according to the content of the cache indication field. For example, when it is determined that the specified data block is cached in the Cache of the first processor according to the Cache indication field, the first processor may be determined to be the target processor. When it is determined that the specified data block is cached in both the second processor Cache and the third processor Cache according to the Cache indication field, it may be determined that both the second processor and the third processor are the target processor.
If the directory Cache of the interconnection chip and the directory area of the main memory do not have the specified directory information, the specified data block is not considered to be cached by any processor Cache, and the processor can directly change the state of the specified data block according to the data block state change request.
And 104, sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the specified data block cached in the Cache of the target processor.
If the target processor is determined to exist according to the directory information, the processor can send a state change instruction to the target processor, and the data block state change request is used for requesting the target processor to change the state of the specified data block cached in the Cache of the target processor. The target processor can modify the state of the specified data block according to the data block state change request, so that the consistency of data in the caches of the processors can be ensured.
The status change indication may be different according to different types of the data block status change request. For example, when the data block state change request is a data block rewrite request, sending a failure indication to the target processor, where the failure indication is used to indicate the target processor to fail the specified data block cached in the Cache of the target processor; or when the data block state change request is a data block sharing request, sending a sharing indication to the target processor, wherein the sharing indication is used for indicating the target processor to modify the specified data block cached in the Cache of the target processor into a sharing mode.
The target processor, upon receiving the state change indication, may change the state of the specified data block in accordance with the state change indication. For example, when the target processor receives a failure indication, a specified data block corresponding to the failure indication in the Cache of the target processor may be failed; and when the target processor receives the sharing indication, the specified data block corresponding to the sharing indication in the Cache of the target processor can be shared.
In this embodiment, a data block status change request is received; determining a designated data block in a main memory system area according to the data block state change request; determining a target processor according to directory information stored in the main memory, wherein the directory information is used for recording the condition that data blocks in a main memory system area are cached by each processor Cache, and the target processor refers to a processor which stores specified data blocks into the processor caches; and sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the cached specified data block in the Cache of the target processor. By adopting the embodiment, the directory information is stored in the main memory, so that the directory storage space of the interconnection chip can be prevented from being used for storing the directory information, and the difficulty in designing and realizing the NUMA system is reduced.
Corresponding to the embodiment of the method for maintaining the consistency of the Cache data according to the directory information, the embodiment of the invention also provides an embodiment of a device for maintaining the consistency of the Cache data according to the directory information.
Referring to fig. 3, a schematic structural diagram of an embodiment of the apparatus for maintaining Cache data consistency according to directory information in the present invention is shown, where the directory information is stored in a main memory, and the directory information stored in the directory Cache is generated by mapping the directory information in a directory area of the main memory in a multi-way set associative manner. The device can be used for executing the method for maintaining the consistency of the Cache data according to the directory information in the embodiment.
As shown in fig. 3, the apparatus may include: a receiving unit 301, a specified data block determining unit 302, a target processor determining unit 303, and a transmitting unit 304.
The receiving unit 301 is configured to receive a data block state change request; a specified data block determination unit 302, configured to determine a specified data block in the main memory system area according to the data block state change request; a target processor determining unit 303, configured to determine a target processor according to directory information stored in the main memory, where the target processor is a processor that has stored a specified data block into a processor Cache; a sending unit 304, configured to send a state change indication to the target processor, where the data block state change request is used to request the target processor to change a state of the specified data block cached in the Cache of the target processor.
Optionally, the target processor determining unit 303 includes: a first detecting subunit, configured to detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory, where the directory area of the main memory is used to store the directory information; a first determining subunit, configured to determine the target processor according to the specified directory information when the specified directory information exists in the directory area of the main memory.
Optionally, the target processor determining unit 303 includes: the second detection subunit is used for detecting whether the directory cache of the interconnection chip has the specified directory information corresponding to the specified data block; a third detecting subunit, configured to detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory when the specified directory information does not exist in a directory cache of an interconnect chip; a second determining subunit, configured to determine the target processor according to the specified directory information when the specified directory information exists in the directory area of the main memory. The second determining subunit may be further configured to determine the target processor according to the specified directory information when the specified directory information exists in a directory cache of an interconnect chip. The target processor determining unit 303 may further include: and the updating subunit is used for updating the directory information in the directory cache when the specified directory information does not exist in the directory cache of the interconnected chip.
Optionally, the sending unit 304 is configured to send a failure indication to the target processor when the data block state change request is a data block rewrite request, where the failure indication is used to indicate that the target processor fails the specified data block cached in the target processor Cache; or, the shared instruction is used to instruct the target processor to modify the specified data block cached in the Cache of the target processor into a shared mode. The directory information may include an access status field, an information status field, and a Cache indication field, where the access status field is used to indicate whether the directory information is being accessed, the information status field is used to indicate a status of the directory information, and the Cache indication field is used to indicate a status that a data block corresponding to the directory information is cached by a processor Cache.
In this embodiment, the apparatus for maintaining the consistency of Cache data according to directory information includes: a receiving unit, configured to receive a data block state change request; a specified data block determination unit for determining a specified data block in the main memory system area according to the data block state change request; a target processor determining unit configured to determine a target processor based on the directory information stored in the main memory, and a transmitting unit configured to transmit a state change instruction to the target processor. By adopting the embodiment, the directory information is stored in the main memory, so that the directory storage space of the interconnection chip can be prevented from being used for storing the directory information, and the difficulty in designing and realizing the NUMA system is reduced.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above-described embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A method for maintaining Cache data consistency of a Cache memory according to directory information, wherein the directory information is stored in a main memory, and the directory information is used for recording the condition that a data block in a system area of the main memory is cached by a Cache memory of each processor, the method comprising:
receiving a data block state change request;
determining a designated data block in a main memory system area according to the data block state change request;
determining a target processor according to directory information stored in the main memory, wherein the target processor is a processor which stores a specified data block into a processor Cache;
sending a state change instruction to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the cached specified data block in the Cache of the target processor;
wherein said determining a target processor based on directory information stored in said main memory comprises:
detecting whether appointed directory information corresponding to the appointed data block exists in a directory cache of an interconnection chip;
when the specified directory information does not exist in the directory cache of the interconnection chip, detecting whether the specified directory information corresponding to the specified data block exists in the directory area of the main memory;
and when the specified directory information exists in the directory area of the main memory, determining the target processor according to the specified directory information.
2. The method of claim 1, wherein the method further comprises:
and when the specified directory information exists in the directory cache of the interconnected chip, determining the target processor according to the specified directory information.
3. The method of claim 1, wherein the method further comprises:
and when the specified directory information does not exist in the directory cache of the interconnected chip, updating the directory information in the directory cache.
4. The method according to any one of claims 1 to 3,
the directory information stored in the directory cache is generated by mapping the directory information in the directory area of the main memory in a multi-way set associative manner.
5. The method of any of claims 1 to 3, wherein sending a state change indication to the target processor comprises:
when the data block state change request is a data block rewriting request, sending a failure indication to the target processor, wherein the failure indication is used for indicating the target processor to fail the specified data block cached in the Cache of the target processor; alternatively, the first and second electrodes may be,
and when the data block state change request is a data block sharing request, sending a sharing indication to the target processor, wherein the sharing indication is used for indicating the target processor to modify the specified data block cached in the Cache of the target processor into a sharing mode.
6. The method according to any one of claims 1 to 3,
the directory information comprises an access state field, an information state field and a Cache indication field, wherein the access state field is used for indicating whether the directory information is being accessed, the information state field is used for indicating the state of the directory information, and the Cache indication field is used for indicating the condition that a data block corresponding to the directory information is cached by a processor Cache.
7. An apparatus for maintaining Cache data consistency according to directory information, wherein the directory information is stored in a main memory, and the directory information is used for recording the condition that a data block in a main memory system area is cached by each processor Cache, the apparatus comprises:
a receiving unit, configured to receive a data block state change request;
a specified data block determination unit for determining a specified data block in the main memory system area according to the data block state change request;
the target processor determining unit is used for determining a target processor according to the directory information stored in the main memory, wherein the target processor is a processor which stores the specified data block into a processor Cache;
a sending unit, configured to send a state change instruction to the target processor, where the data block state change request is used to request the target processor to change a state of the specified data block cached in the Cache of the target processor;
wherein the target processor determining unit includes:
the second detection subunit is used for detecting whether the directory cache of the interconnection chip has the specified directory information corresponding to the specified data block;
a third detecting subunit, configured to detect whether specified directory information corresponding to the specified data block exists in a directory area of the main memory when the specified directory information does not exist in a directory cache of an interconnect chip;
a second determining subunit, configured to determine the target processor according to the specified directory information when the specified directory information exists in the directory area of the main memory.
8. The apparatus of claim 7,
the second determining subunit is further configured to determine the target processor according to the specified directory information when the specified directory information exists in a directory cache of an interconnect chip.
9. The apparatus of claim 7, wherein the target processor determination unit further comprises:
and the updating subunit is used for updating the directory information in the directory cache when the specified directory information does not exist in the directory cache of the interconnected chip.
10. The device according to any of the claims 7 to 9,
the directory information stored in the directory cache is generated by mapping the directory information in the directory area of the main memory in a multi-way set associative manner.
11. The device according to any of the claims 7 to 9,
the sending unit is configured to send a failure indication to the target processor when the data block state change request is a data block rewrite request, where the failure indication is used to indicate the target processor to fail the specified data block cached in the target processor Cache; or, the shared instruction is used to instruct the target processor to modify the specified data block cached in the Cache of the target processor into a shared mode.
12. The device according to any of the claims 7 to 9,
the directory information comprises an access state field, an information state field and a Cache indication field, wherein the access state field is used for indicating whether the directory information is being accessed, the information state field is used for indicating the state of the directory information, and the Cache indication field is used for indicating the condition that a data block corresponding to the directory information is cached by a processor Cache.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510447072.5A CN106406745B (en) | 2015-07-27 | 2015-07-27 | Method and device for maintaining Cache data consistency according to directory information |
| PCT/CN2016/090778 WO2017016427A1 (en) | 2015-07-27 | 2016-07-20 | Method and device for maintaining cache data consistency according to directory information |
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| CN108664417B (en) * | 2017-03-31 | 2022-10-25 | 华为技术有限公司 | Directory updating method and device |
| CN113703958B (en) * | 2021-07-15 | 2024-03-29 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and storage medium for accessing data among multi-architecture processors |
| CN114238165B (en) * | 2021-12-21 | 2023-03-24 | 海光信息技术股份有限公司 | Data processing method, data processing apparatus, and storage medium |
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| CN101706755A (en) * | 2009-11-24 | 2010-05-12 | 中国科学技术大学苏州研究院 | Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof |
| CN102063406A (en) * | 2010-12-21 | 2011-05-18 | 清华大学 | Network shared Cache for multi-core processor and directory control method thereof |
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| US8606997B2 (en) * | 2008-12-23 | 2013-12-10 | Oracle America, Inc. | Cache hierarchy with bounds on levels accessed |
| US9135175B2 (en) * | 2012-12-21 | 2015-09-15 | Oracle International Corporation | Distributed cache coherency directory with failure redundancy |
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| CN101706755A (en) * | 2009-11-24 | 2010-05-12 | 中国科学技术大学苏州研究院 | Caching collaboration system of on-chip multi-core processor and cooperative processing method thereof |
| CN102063406A (en) * | 2010-12-21 | 2011-05-18 | 清华大学 | Network shared Cache for multi-core processor and directory control method thereof |
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