CN114238165B

CN114238165B - Data processing method, data processing apparatus, and storage medium

Info

Publication number: CN114238165B
Application number: CN202111568891.7A
Authority: CN
Inventors: 杨凯歌; 林江; 曹俊
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2023-03-24
Anticipated expiration: 2041-12-21
Also published as: CN114238165A

Abstract

A data processing method, a data processing apparatus, and a storage medium. The data processing method comprises the following steps: receiving data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory; and responding to the idle storage units in the storage group corresponding to the data addresses in the directory memory, and storing the data information to be stored in the idle storage units. The data information is stored through the directory memory for storing the directory information, so that the utilization rate of the directory memory is improved, and the processor can quickly find and read the data information stored in the directory memory, so that the overall performance of the system is improved.

Description

Data processing method, data processing apparatus, and storage medium

Technical Field

Embodiments of the present disclosure relate to a data processing method, a data processing apparatus, and a storage medium.

Background

Currently, for a computer system with multiple processors and multiple Cache memories (caches), a Cache may Cache a large amount of data, which may be exclusive or may store copies of data at the same address in different caches. When different caches operate on cached data of the same address, coherency problems arise. To address this problem, many techniques have emerged to maintain data consistency. For example, when a processor wants to modify data stored in a cache when multiple caches store identical copies of the data, the copies of the data in other caches are marked as invalid to avoid consistency errors.

Disclosure of Invention

At least one embodiment of the present disclosure provides a data processing method applied to an electronic device, where the electronic device includes a directory memory and multiple caches used by multiple processors, the directory memory is used to store directory information corresponding to data information stored in the multiple caches, the directory memory includes multiple storage groups, each storage group includes at least one storage unit, and the data processing method includes: receiving data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory; and responding to the free storage unit in the storage group corresponding to the data address in the directory memory, and storing the data information to be stored in the free storage unit.

For example, the data processing method provided by at least one embodiment of the present disclosure further includes: in response to no free memory cell in the memory bank corresponding to the data address in the directory memory and at least one data information stored therein: and determining selected data information in the at least one piece of data information, moving the selected data information out of a storage unit for storing the selected data information according to the data state of the selected data information, and storing the data information to be stored in the storage unit.

For example, in a data processing method provided by at least one embodiment of the present disclosure, the moving the selected data information out of a storage unit for storing the selected data information according to the data state of the selected data information includes: in response to the data state of the selected data information indicating that the selected data information has been modified, writing the selected data information into the system memory before moving the selected data information out of the memory cell for storing the selected data information; in response to the data state of the selected data information indicating that the selected data information is not modified, directly moving the selected data information out of the storage unit for storing the selected data information.

For example, the data processing method provided by at least one embodiment of the present disclosure further includes: acquiring to-be-stored directory information needing to be stored in the directory memory, and responding to the fact that no free storage space exists in a storage group of the directory memory corresponding to the to-be-stored directory information: determining a selected storage unit in a storage group corresponding to the directory information to be stored; moving at least part of the information stored in the selected memory cell out of the selected memory cell; and storing the directory information to be stored into the selected storage unit.

For example, in a data processing method provided by at least one embodiment of the present disclosure, the selected storage unit is used for storing data information or at least one directory information.

For example, in a data processing method provided in at least one embodiment of the present disclosure, the data information to be stored is data information read from the data address of the system memory, or the data information to be stored is data information written to the data address of the system memory.

For example, the data processing method provided by at least one embodiment of the present disclosure further includes: setting a data state of the data information to be stored, wherein the setting of the data state of the data information to be stored comprises: setting the data state of the data information to be stored to be a first state in response to the data information to be stored in at least one of the plurality of caches having been modified, and setting the data state of the data information to be stored to be a second state in response to the data information to be stored in at least one of the plurality of caches not having been modified.

For example, in a data processing method provided in at least one embodiment of the present disclosure, the free storage unit includes: storing a flag bit, an address bit, a status bit and a data bit, and storing the data information to be stored in the idle storage unit, including: setting the storage zone bit as a data mark; storing at least a portion of the data address in the address bits; storing the data state corresponding to the data information to be stored in the state bit; and storing the data information to be stored in the data bits.

For example, in a data processing method provided in at least one embodiment of the present disclosure, the selected storage unit includes: storing a flag bit, an address bit and a status bit, and storing the directory information to be stored in the selected storage unit, including: setting the storage flag bit as a directory flag; storing the directory address in the directory information to be stored in the address bit; and storing the cache state in the directory information to be stored in the state bit.

At least one embodiment of the present disclosure provides a data processing apparatus applied to an electronic device, where the electronic device includes a directory memory and a plurality of caches used by a plurality of processors, the directory memory is configured to store directory information corresponding to data information stored in the caches, the directory memory includes a plurality of storage groups, each storage group includes at least one storage unit, and the data processing apparatus includes: the data receiving module is configured to receive data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory; and the first data operation module is configured to respond to the existence of a free storage unit in a storage group corresponding to the data address in the directory memory, and store the data information to be stored in the free storage unit.

For example, in a data processing apparatus provided by at least one embodiment of the present disclosure, the first data operation module is further configured to, in response to that there is no free storage unit in the storage group corresponding to the data address in the directory memory and at least one piece of data information is stored: and determining selected data information in the at least one piece of data information, moving the selected data information out of a storage unit for storing the selected data information according to the data state of the selected data information, and storing the data information to be stored in the storage unit.

For example, at least one embodiment of the present disclosure provides a data processing apparatus further including: a second data manipulation module configured to: acquiring to-be-stored directory information needing to be stored in the directory memory, and responding to the fact that no free storage space exists in a storage group of the directory memory corresponding to the to-be-stored directory information: determining a selected storage unit in a storage group corresponding to the directory information to be stored, and moving at least part of information stored in the selected storage unit out of the selected storage unit; and storing the directory information to be stored into the selected storage unit.

For example, at least one embodiment of the present disclosure provides a data processing apparatus further including: a data state setting module configured to set a data state of the data information to be stored, wherein, when an operation of setting the data state of the data information to be stored is performed, the data state setting module is configured to: setting the data state of the data information to be stored to be a first state in response to the data information to be stored in at least one of the plurality of caches being modified, and setting the data state of the data information to be stored to be a second state in response to the data information to be stored in at least one of the plurality of caches not being modified.

For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the free storage unit includes: storing flag bits, address bits, status bits, and data bits, the first data manipulation module comprising: a first storage flag operating unit configured to set the storage flag bit to a data flag; a first address bit operation unit configured to store at least a portion of the data address in the address bits; a first state bit operation unit configured to store a data state corresponding to the data information to be stored in the state bit; a first data bit operation unit configured to store the data information to be stored in the data bits.

For example, in a data processing apparatus provided in at least one embodiment of the present disclosure, the selected storage unit includes: storing flag bits, address bits and status bits, the second data manipulation module comprising: a second storage flag operating unit configured to set the storage flag bit to a directory flag; a second address bit operation unit configured to store a directory address in the directory information to be stored in the address bit; and the second state bit operation unit is configured to store the cache state in the directory information to be stored in the state bit.

At least one embodiment of the present disclosure provides a data processing apparatus including: a memory for non-transitory storage of computer-executable instructions; and a processor for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, perform a data processing method according to any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure provides a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform a data processing method according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a schematic diagram of an electronic device provided in some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of a directory memory according to some embodiments of the present disclosure;

fig. 3 is a schematic diagram of a data processing method according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of the step of "storing the data information to be stored in the free storage unit or storing the data information to be stored in the storage unit" in FIG. 3;

FIG. 5 is a schematic illustration of the step of FIG. 3 of "moving selected data information out of a storage location for storing selected data information according to the data state of the selected data information";

fig. 6 is a schematic diagram of a data processing method according to some embodiments of the disclosure;

FIG. 7 is a schematic diagram of the "store directory information to be stored in selected memory location" step of FIG. 6;

fig. 8 is a schematic diagram of a data processing apparatus according to some embodiments of the present disclosure;

FIG. 9 is a diagram of a first data manipulation module of FIG. 8;

FIG. 10 is a diagram of a second data manipulation module of FIG. 8;

fig. 11 is a schematic diagram of a data processing apparatus provided in some embodiments of the present disclosure; and

fig. 12 is a schematic diagram of a non-transitory storage medium according to some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.

In a computer system having multiple processors, data consistency maintenance may be performed using techniques such as snoop filtering in order to increase the efficiency of the data consistency maintenance. Snoop filtering may help track the caching status of data in multiple caches, e.g., there is only a single copy of data in a cache, there are multiple copies, or the data is only present in system memory (e.g., main memory), etc.

In computer systems with multiple processors and multiple caches, some directory-based coherency systems currently track the cache state of data through a directory and store the tracked cache state of data in the directory, i.e., the directory may be used to maintain data coherency. When the coherency agent snoops the bus to discover coherency transactions, it queries the directory-traced information and sends a probe response to complete coherency maintenance. When using the directory for consistency maintenance, the server multi-core computer system includes an independent storage module for storing the directory, so as to reduce the number of transmission communications among the modules in the computer system. However, the memory module will occupy a certain circuit resource, which increases the resource consumption of the circuit.

At least one embodiment of the present disclosure provides a data processing method, a data processing apparatus, and a storage medium. The data processing method is applied to electronic equipment, the electronic equipment comprises a directory memory and a plurality of caches used by a plurality of processors, the directory memory is used for storing directory information corresponding to data information stored in the caches, the directory memory comprises a plurality of storage groups, each storage group comprises at least one storage unit, and the data processing method comprises the following steps: receiving data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory; and responding to the idle storage units in the storage group corresponding to the data addresses in the directory memory, and storing the data information to be stored in the idle storage units.

In the embodiment of the disclosure, the data information is stored by the directory memory for storing the directory information, so that the utilization rate of the directory memory is improved, and the processor can quickly find and read the data information stored by the directory memory, so that the overall performance of the system is improved.

Fig. 1 is a schematic view of an electronic device according to some embodiments of the present disclosure.

As shown in FIG. 1, electronic device 100 includes at least one directory storage 101, a plurality of caches 106 (cache 1061-cache 1065), at least one system memory 105, and a coherency maintenance module 102.

The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), wearable electronic devices, and the like, and fixed terminals such as digital TVs, desktop computers, smart home devices, and the like.

For example, each of the plurality of caches 106 is configured to store data storage information corresponding to at least one data information, the data storage information corresponding to each data information includes the data information, a data status corresponding to the data information, and data address information, and the data address information may be at least a portion of a data address corresponding to the data information. The consistency maintenance module 102 is configured to maintain consistency of data information corresponding to all data storage information stored in the plurality of caches 106, that is, to maintain consistency of all data information stored in the plurality of caches 106.

For example, directory memory 101 may be implemented in a different implementation than caching. The disclosure is not limited thereto, and in other embodiments, the directory memory 101 may be implemented in the same implementation as the cache, for example, the cache 1065 of the caches 106 shown in fig. 1 may also be an example of the directory memory 101. For example, directory memory 101 may be a directory snoop filter to maintain coherency of all data information stored in multiple caches 106.

In the embodiment of the present disclosure, the directory memory 101 is configured to store directory information corresponding to data information stored in the plurality of caches 106, and the directory memory 101 is further configured to store at least one piece of data information, that is, the directory memory 101 represents a memory that can store the directory information and the data information at the same time, where the directory information is used to implement consistency maintenance of the data information, and the directory information may also be called as consistency directory information; the data information indicates data stored in a storage location pointed to by a data address corresponding to the data information in the system memory 105 (described later).

For example, the data information stored in the directory memory 101 may not store the directory information corresponding to the data information, for example, when the data information is stored only on the directory memory 101, the directory information corresponding to the data information may not be stored.

For example, if the data information is not only stored in the directory memory 101 but also exists in at least one of the plurality of caches 106 at the same time, the directory information corresponding to the data information may be stored, and at this time, consistency maintenance may be performed on the data information, for example, consistency maintenance may be performed on the data information in at least one of the plurality of caches 106 and the directory memory 101.

In this disclosure, "maintaining consistency of all data information stored in the plurality of caches 106" generally refers to probe-based maintenance of the state of the data and the passing of the data, and the update mechanism of the corresponding directory information, but may also include consistency maintenance of other aspects of the data.

For example, in some embodiments, directory memory 101 and cache 106 may be implemented as cache memories, which are comprised of static memory chips (SRAMs). In a hierarchy of computer storage systems, a cache memory is a high-speed, small-capacity memory that is interposed between a central processor and a system memory. Because the directory memory 101 is a cache and is used as a read-write cache, the read-write delay of the system to data is reduced, and the overall performance of the computer system is improved.

In the embodiment of the present disclosure, the description is made taking the example in which the directory memory 101 is implemented as a cache memory.

Fig. 2 is a schematic structural diagram of a directory memory according to some embodiments of the present disclosure.

For the cache, in order to facilitate fast query of the content stored in the cache, each cache may be divided into a plurality of storage groups, and each storage group includes at least one storage unit (which may also be called a storage block). For example, each storage unit in the cache 106 is used for storing data storage information corresponding to one data information, and each storage unit in the directory memory 101 is used for storing a plurality of directory information or data storage information corresponding to one data information.

For example, as shown in fig. 2, the directory memory 101 may include a plurality of memory groups C1 to Cn (fig. 2 shows three memory groups, i.e., memory group C1, memory group C2, memory group Cn), each including at least one memory cell B1 to Bm (fig. 2 shows memory cell B1, memory cell B2, memory cell B (m-1), and memory cell Bm), n and m each being a positive integer greater than 1.

It should be noted that each storage group in the plurality of storage groups may be configured to store data information and directory information corresponding to the data information.

For example, the number of the plurality of storage units corresponding to the plurality of storage groups may be different from each other, or may be at least partially the same, and the storage units may be specifically designed according to actual design requirements. The number of memory cells corresponding to a memory group indicates the number of memory cells included in the memory group. In the example shown in fig. 2, the number of memory cells corresponding to each memory group is m, that is, each memory group includes m memory cells.

For example, an address of data information in a system memory storing the data information includes a first address portion and a second address portion, the first address portion is used to represent data address information corresponding to the data information, that is, the data address information may be the first address portion; the second address part is used for determining a memory group in the cache for storing the data information, i.e. when the data information is stored to the cache, the second address part is used for realizing mapping of the memory group in the cache.

For example, the first address portion may also indicate a directory address in directory information corresponding to the data information, that is, the directory address in the directory information may be the first address portion; the second address part can also be used for determining a storage group for storing the directory information corresponding to the data information in the directory memory, or for determining a storage group for storing the data information in the directory memory, that is, when the directory information or the data information is stored in the directory memory, the second address part is used for mapping the storage group in the directory memory. It should be noted that, a specific mapping relationship between the second address portion and the storage group may be set according to an actual situation, and this is not specifically limited by the embodiment of the present disclosure.

It should be noted that, the present disclosure is not limited with respect to the manner in which the first address part and the second address part are divided.

It should be noted that, in the electronic device 100, the structural hierarchy of the cache may be set according to practical situations, and is not limited to the structure shown in fig. 1, for example, in some embodiments, the structure of the cache may be an interconnection topology.

For example, as shown in fig. 2, in the directory memory 101, each storage unit of each storage group includes a storage flag bit for indicating whether the information stored by the storage unit belongs to directory information or data information.

For example, in the directory memory 101, when the storage flag bit of a memory cell indicates a directory flag, the memory cell stores directory information corresponding to data information. As shown in fig. 2, for the storage unit B1 in the storage group C1, the content stored by the storage unit B1 in the storage group C1 may include a directory flag and a plurality of directory information. Each directory information may include a directory address and a cache state, the directory address indicates a first address portion of the data information corresponding to the directory information, the cache state indicates caches storing the data information corresponding to the directory information, that is, indicates which caches store the data information, and the directory flag is used to indicate that the content stored in the storage unit B1 in the storage group C1 is the directory information. For example, in the example shown in fig. 2, the memory cell B1 in the memory group C1 may store two directory information, directory address 0 and cache state 0 and directory address 1 and cache state 1, respectively.

For example, in the directory memory 101, a plurality of data information are usually stored in a group-associative manner, in order to quickly search for a certain data information, a part (for example, the second address part) of an address corresponding to the data information in the system memory for storing the data information is usually mapped as a group-associative address mapping relationship, and the remaining part (for example, the first address part) of the address corresponding to the data information, and a data state corresponding to the data information are stored in a certain storage unit of a corresponding storage group in the directory memory 101 as data storage information corresponding to the data information. A data state generally indicates whether the data information is "clean" or "dirty" indicating whether the data information has been overwritten, and when the data state is "dirty", indicating that the data information has been overwritten; when the data state is "clean", it indicates that the data information is not rewritten.

For example, the directory memory 101 may store a plurality of directory information in a group-associative manner. For example, the storage group corresponding to the directory information on the directory memory 101 may be determined by a directory address of the directory information, for example, the directory address of the directory information may correspond to a part (for example, the first address part) of an address corresponding to data information corresponding to the directory information in the system memory for storing the data information, and for example, the storage group corresponding to the directory information on the directory memory 101 may be determined by mapping a part (for example, the second address part) of an address corresponding to data information corresponding to the directory information in the system memory for storing the data information as a group-associative address mapping relationship.

For example, the storage group corresponding to the data information in the directory memory 101 may be determined by a part (e.g., the second address part) of the address of the data information in the system memory, for example, by group association.

It should be noted that although the address mapping may be performed in a "group association" manner in the present disclosure, it should be understood that the address mapping manner is not limited to group association, and may be implemented in any suitable manner, for example, in a fully-associated manner or a one-to-one mapping manner.

For example, in the directory memory 101, when a storage flag bit of a memory cell indicates a data flag, the memory cell stores data information. As shown in fig. 2, for the memory cell B2 in the memory group C1, the content stored by the memory cell B2 may include a data flag and data storage information corresponding to the data information, where the data storage information includes the data information, a data state corresponding to the data information, and data address information. The data flag is used to indicate that the content stored in the storage unit B2 in the storage group C1 is data storage information. For example, in the example shown in fig. 2, the content stored by the memory cell B2 in the memory group C1 includes data information 0, data address information 0, and data state 0.

It should be noted that the directory information and the data storage information are not limited to the specific contents shown in fig. 2, and may also have other information, and the specific contents included in the directory information and the specific contents included in the data storage information may be set according to practical situations, which is not limited in this disclosure. Since the bit widths of the directory information and the data storage information are not necessarily the same, fig. 2 shows a case where the storage unit storing two directory information may store one data storage information, but the present disclosure is not limited thereto, and may be various ratios (e.g., 1 (data storage signal): 10 (directory information)) or non-storage manners thereto in practice.

For example, in the directory memory 101, each storage unit can store only one type of information, that is, can store only directory information or data information. Each storage group may store both directory information and data information, i.e., some storage units in the storage group store directory information and other storage units in the storage group store data information.

For example, as shown in fig. 1, the electronic device 100 further includes a plurality of processors 103 (processor 1031 and processor 1032), the plurality of caches 106 includes a plurality of dedicated caches used by the plurality of processors 103, and in some embodiments, the plurality of caches 106 may further include at least one shared cache shared by the plurality of processors 103. In some embodiments, as shown in fig. 1, the at least one shared cache includes cache 1065, i.e., cache 1065 is a shared cache and may be shared by multiple processors 103. In other embodiments, cache 1065 may be a private cache. The present disclosure is not particularly limited thereto.

It should be noted that, in the embodiments of the present disclosure, a dedicated cache of a processor represents a cache that can be accessed only by the processor, and a shared cache can be accessed by a plurality of processors.

Each processor 103 may use at least one private cache and in some embodiments, each processor 103 may also use at least one shared cache, e.g., cache 1061 and cache 1062 shown in fig. 1 may be private caches used by processor 1031, cache 1063 and cache 1064 shown in fig. 1 may be private caches used by processor 1032, and cache 1065 shown in fig. 1 may be a shared cache shared by processor 1031 and processor 1032. For example, cache 1061 and 1063 may be level one (L1) caches, and cache 1062 and 1064 may be level two (L2) caches. Cache 1065 may be a level three cache (L3), and directory memory 101 may be a system level cache (SLC, which generally refers to a cache in a computer system that is distributed between system memory and caches (L1, L2, L3, etc.)).

For example, for a current processor of the plurality of processors 103 that needs to access the cache, the current processor first accesses at least one private cache used by the current processor, then accesses at least one cache of the at least one shared cache, and finally accesses the directory memory. For example, the current processor may be the processor 1031, when the processor 1031 issues a read request to read data information, the processor 1031 may access the cache, and at this time, the processor 1031 first accesses at least one dedicated cache used by the processor 1031, namely, the cache 1061 and the cache 1062, and in the designed process, an access order may be set for the access of the dedicated cache, for example, the processor 1031 may first access the cache 1061, and when data that the processor 1031 needs to read is not stored in the cache 1061, the processor 1031 then accesses the cache 1062; when the dedicated cache is accessed completely, that is, neither the cache 1061 nor the cache 1062 stores the data that needs to be read by the processor 1031, the processor 1031 may continue to access at least one shared cache used by the processor 1031, that is, the cache 1065 shown in fig. 1, and in the designed process, the access sequence of the shared cache may also be set; when the access to the private cache and the shared cache is completed, that is, none of the cache 1061, the cache 1062, and the cache 1065 stores data that the processor 1031 needs to read, the processor 1031 may continue to access the directory memory 101. When the directory memory 101 does not store the data that the processor 1031 needs to read, the processor 1031 may continue to access the system memory 105.

It should be noted that, in the example shown in fig. 1, only one directory memory 101, one system memory 105, five caches 106 (the caches 1061 to 1065), and two processors 103 (the processors 1031 and the processors 1032) are shown, however, the embodiment of the present disclosure is not limited thereto, and the electronic device 100 may include more directory memories, may also include more or less caches, and may also include more processors.

For example, each cache has a cache control module that can access each storage unit in the cache to read the content stored in the storage unit and then parse the stored content. When determining whether the data to be read in the read request issued by the processor 103 is stored in a certain cache, the cache control module in the cache performs the determination process, that is, the cache control module reads and parses the content in the storage unit, and compares the parsed content with the data to be read determined based on the read request, thereby determining whether the data stored in the storage unit is consistent with the data to be read. The cache control module can read the contents stored in all the storage units in one storage group at a time and perform comparison in parallel.

As shown in fig. 2, when the directory memory 101 is implemented as a cache, the directory memory 101 includes a cache control module 101A, and the cache control module 101A can implement not only comparison between data information but also comparison between addresses. For example, when the processor 103 issues a read request and the read request is transmitted to the directory memory 101, the cache control module 101A may parse the read request and obtain data information that needs to be read by the processor 103 and a data address (address on the system memory) corresponding to the data information, and the cache control module 101A may read and parse contents in each storage unit in the directory memory 101 and compare the parsed contents with the data information that needs to be read and the data address corresponding to the data information. It should be noted that the comparison process of directory information (i.e., the comparison process of addresses) and the comparison process of data information are independent of each other.

For example, as shown in fig. 1, according to the logical order of accessing the cache, the cache 1061 is closest to the processor 1031, and the directory memory 101 is farthest from the processor 1031, that is, the processor 1031 accesses the cache 1061 first and accesses the directory memory 101 last; similarly, cache 1063 is closest to processor 1032 and directory memory 101 is furthest away from processor 1032.

For example, in some embodiments, as shown in FIG. 1, the consistency maintenance module 102 is coupled to the directory store 101 (e.g., directly coupled, thereby increasing the speed at which the consistency maintenance module 102 accesses the directory store 101) to directly access the directory store 101.

For example, as shown in FIG. 1, electronic device 100 also includes coherency interconnect bus 104, coherency interconnect bus 104 being coupled directly to cache 1065 and also coupled directly to coherency maintenance module 102. The coherent interconnect bus 104 is a common communication trunk for information transmission, and for example, the coherent interconnect bus 104 is a transmission line bundle composed of electronic components such as wires.

For example, as shown in fig. 1, the directory memory 101 is configured to be able to store directory information corresponding to at least a part of all data information stored in the at least one system memory 105.

For example, the system memory 105 may be a main memory, or may be a memory externally connected to the electronic device 101, such as a hard disk, a floppy disk, an optical disk, and a usb disk.

For example, as shown in FIG. 1, the consistency maintenance module 102 is coupled to the system memory 105, e.g., directly coupled, i.e., the consistency maintenance module 102 may directly access the system memory 105 to which it is coupled, thereby achieving maintaining consistency of the data information stored in the system memory 105.

It should be noted that in this disclosure, two devices are "coupled" to indicate that one device can access the other device in a logical relationship.

For example, as shown in fig. 1, when the processor 1031 needs to read data information, if all caches (i.e. the cache 1061, the cache 1062, and the cache 1065) used by the processor 1031 do not store the data information, and at the same time, the directory memory 101 does not store the data information, the data information may be read from the system memory 105 and fed back to the processor 1031. Depending on the logical order in which the caches are accessed, cache 1061 and cache 1062 are furthest away from system memory 105, while directory memory 101 is closest to system memory 105.

For example, in some embodiments, each system memory 105 may include a directory storage space, where the directory storage space is used to store directory information in an extended manner, and the extended storage of the directory information into the system memory has little impact on the system memory, and at the same time, the storage capacity for storing the directory information is increased, the probability of occurrence of degradation is reduced, and the performance of the system as a whole is improved. The directory storage space is used for storing directory information corresponding to at least part of all data information stored in the plurality of caches 106. The directory information stored in the directory storage space may be partially the same as or completely different from the directory information stored in the directory memory 101.

For example, the directory storage space may include a plurality of extended storage groups corresponding to a plurality of storage groups in the directory storage one to one, and when some directory information needs to be stored in a certain storage group in the directory storage and the storage group has no storage space to store the directory information, the directory information may be stored in the extended storage group corresponding to the storage group in the directory storage space to implement extended storage of the directory information, and to facilitate subsequent query of the directory information.

It should be noted that, with respect to the directory storage space in the system memory 105, the determination of the directory information stored in the directory storage space is implemented by the consistency maintenance module 102.

Fig. 3 is a schematic diagram of a data processing method according to some embodiments of the present disclosure.

For example, the data processing method may be applied to an electronic device provided by an embodiment of the present disclosure, for example, the electronic device 100 described above.

As shown in fig. 3, in some embodiments of the present disclosure, a data processing method includes at least the following steps S101-S102.

Step S101, receiving data information to be stored.

In the case that the to-be-stored data information is received and it is determined that the to-be-stored data information needs to be stored in the directory memory, it may be determined whether there is a free storage unit in the storage group corresponding to the data address in the directory memory, and in response to that there is a free storage unit in the storage group corresponding to the data address in the directory memory, step S102 is executed to store the to-be-stored data information in the free storage unit.

For example, in some embodiments, as shown in fig. 1, the electronic device 100 includes a directory memory 101, a system memory 105, and a plurality of caches 106 used by the plurality of processors 103, the directory memory 101 is configured to store directory information corresponding to data information stored in the plurality of caches 106, and the directory memory 101 includes a plurality of storage groups, each storage group including at least one storage unit.

For example, as shown in fig. 1, in step S101, the data information to be stored corresponds to a location indicated by a data address in the system memory 105, for example, the data information to be stored may be data information read by the processor 103 from the location indicated by the data address in the system memory 105, or the data information to be stored may also be data information written by the processor 103 to the data address of the system memory 105, and the type of the data information is not limited by the embodiments of the present disclosure. That is, when the processor needs to read the data information of a certain address, if there is a free storage unit in the storage group corresponding to the address in the directory memory, the data information in the address in the system memory can be stored in the storage unit in the space of the directory memory; when the processor needs to write some data information into the system memory, the data information can also be directly written into the corresponding free storage unit of the directory memory.

For example, in step S102, after the data information to be stored is stored in the directory memory, when the data information to be stored needs to be read again in the system, the data information to be stored may be directly read from the directory memory and cached.

For example, in some embodiments, the free memory locations of the memory banks on directory memory 101 may include storage flag bits, address bits, status bits, and data bits, as shown in FIG. 2, and memory location B2 may be an example of a free memory location. For example, the storage flag bits, the address bits, the status bits, the data bits, and the like are merely schematic divisions, and not actual structural differences, the size of each memory cell may be fixed, and the above-mentioned division of the storage flag bits, the address bits, the status bits, the data bits, and the like may be divided according to the information stored in the memory cell.

Fig. 4 is a schematic diagram of the step of "storing the data information to be stored in the free storage unit or storing the data information to be stored in the storage unit" in fig. 3.

As shown in FIG. 4, in some embodiments, step S102 may include the following four steps S401-S404.

Step S401, setting the storage flag bit as the data flag.

Step S402, at least one part of the data address corresponding to the data information to be stored is stored in the address bit.

Step S403, storing the data state corresponding to the data information to be stored in the state bit.

And step S404, storing the data information to be stored in the data bit.

For example, step S401 may include: a storage Flag bit (Flag) set in the storage unit for indicating the type of data stored in the storage unit (for example, the type of data includes data information and directory information) is set as a Flag indicating the data information, that is, set as a data Flag. For example, a binary number "0" may be used to indicate a flag of the data information, that is, when a storage flag bit in a storage unit is set to "0", the content stored in the storage unit is the data information.

For example, in step S402, the data address information corresponding to the data information is at least a part of the data address. The address bits in step S402 may be adjusted according to an address format corresponding to the actual data information and a size of the data address corresponding to the data information, for example, a size of a storage space specifically occupied by the address bits may be adjusted, which is not limited in this disclosure. For example, the data address may be an address of data information corresponding to the data address in the system memory, and at least a part of the data address stored in the address bit may be the first address portion.

For example, in step S403, the data status may be "clean" or "dirty" status, i.e. indicating whether the data information is rewritten, and when the data status is "dirty" status, indicating that the data information has been rewritten; when the data state is "clean", it indicates that the data information is not rewritten. The status bit in step S403 may be adaptively adjusted according to the characteristics of the format of the actual data status, and the like, which is not limited in this disclosure.

For example, the data bits in step S404 may be adaptively adjusted according to the size and type of the actual data information, which is not limited in this disclosure.

It should be noted that, in the embodiment of the present disclosure, a "free storage unit" indicates a storage unit in the directory memory that does not store any information.

As shown in fig. 3, in other embodiments of the present disclosure, in response to that there is no free storage unit in the storage group corresponding to the data address in the directory memory, it is determined whether the directory memory stores at least one piece of data information, and in response to that the directory memory stores at least one piece of data information, the data processing method further includes the following steps S103 to S105.

Step S103, determining selected data information in the at least one data information.

Step S104, the selected data information is moved out of the storage unit for storing the selected data information according to the data state of the selected data information.

Step S105, storing the data information to be stored into a storage unit.

For example, step S103 may include determining the selected data information in the at Least one data information in a random manner, a Least Recently Used (LRU) manner, and the like, which is not limited by the present disclosure.

For example, when there is no free storage unit in the storage group corresponding to the data address in the directory memory and no data information is stored, it indicates that all the storage units stored in the storage group corresponding to the data address in the directory memory are directory information, and at this time, any directory information in the storage group cannot be replaced by data information, that is, in this case, the data information to be stored cannot be stored in the directory memory. At this time, according to the exchange rule, a certain data information stored in the plurality of caches may be removed, and the data information to be stored may be stored in the storage unit for storing the removed data information in the cache.

Fig. 5 is a schematic diagram of the step of "moving selected data information out of a storage unit for storing the selected data information according to the data state of the selected data information" in fig. 3.

For example, in some embodiments, as shown in FIG. 5, step S104 may include the following two substeps S301-S302.

Firstly, judging whether the data state of the selected data information indicates that the selected data information is modified or not, responding to the data state of the selected data information indicating that the selected data information is modified, executing step S301, firstly writing the selected data information into a system memory, and then moving the selected data information out of a storage unit for storing the selected data information; in response to the data status of the selected data information indicating that the selected data information is not modified, step S302 is performed to directly move the selected data information out of the storage unit for storing the selected data information.

For example, after the selected data information has been modified, the data state of the selected data information may be a "dirty" state; the data state of the selected data information may be a "clean" state if the selected data information is not modified.

For example, in some embodiments, the selected data information may be stored only in the directory memory; in other embodiments, the selected data information is stored not only in the directory memory, but also in at least one cache.

The specific process of step S105 may refer to the specific process of step S102, and is not described herein again.

For example, after the data information to be stored is stored in the free storage unit of the directory memory, the data state of the data information to be stored needs to be set or updated accordingly. As shown in fig. 3, in other embodiments of the present disclosure, the data processing method further includes step S106 of setting a data state of the data information to be stored.

For example, in some embodiments, the data information to be stored is also stored in at least one cache, at this time, step S106 may include: setting a data state of data information to be stored to a first state in response to the data information to be stored in at least one of the plurality of caches having been modified; and in response to the data information to be stored in at least one of the plurality of caches not being modified, setting the data state of the data information to be stored to a second state.

For example, in some embodiments, all caches of the electronic device do not store the to-be-stored data information, in this case, step S106 may include: and setting the data state of the data information to be stored as a second state.

For example, after the data information to be stored is stored in the storage unit (the free storage unit or the storage unit storing the selected data information) in the directory memory, the data processing method further sets the data state corresponding to the data information to be stored, for example, in step S106, the data state of the data information to be stored may be set according to whether the data information to be stored is modified. For example, when the data information to be stored is modified, the data state of the data information to be stored is set to a first state (for example, "dirty" state), and when the data information to be stored is not modified, the data state of the data information to be stored is set to a second state (for example, "clean" state), that is, in this application, the first state represents "dirty" state, and the second state represents "clean" state.

Fig. 6 is a schematic diagram of a data processing method according to some embodiments of the disclosure.

For example, the data processing method provided by some embodiments of the present disclosure may further include various steps of the data processing method shown in fig. 6. As shown in fig. 6, in other embodiments of the present disclosure, the data processing method further includes steps S201 to S204.

Step S201, obtaining the directory information to be stored that needs to be stored in the directory memory.

After the directory information to be stored is acquired, whether a free storage space exists in the storage group of the directory memory corresponding to the directory information to be stored is judged, and in response to the fact that no free storage space exists in the storage group of the directory memory corresponding to the directory information to be stored, steps S202 to S204 are executed.

Step S202, the selected storage unit in the storage group corresponding to the directory information to be stored is determined.

Step S203, at least part of the information stored in the selected storage unit is moved out of the selected storage unit.

Step S204, storing the catalog information to be stored into the selected storage unit.

For example, the free storage space may be the entire storage unit, or may be a storage area in the storage unit, in which one directory information can be stored.

For example, in step S202, the selected storage unit in the storage group corresponding to the directory information to be stored may be determined in a random manner, a Least Recently Used (LRU) manner, and the like, which is not limited by the present disclosure. For example, if the storage group corresponding to the directory information to be stored stores data information, one storage unit may be selected as the selected storage unit from one or more storage units storing the data information randomly or based on an LRU manner; if the storage group corresponding to the directory information to be stored does not store data information, one storage unit can be selected from a plurality of storage units included in the storage group as the selected storage unit randomly or based on an LRU mode.

For example, in step S203, the selected storage unit may store data information or may store at least one directory information. When the data information is stored in the selected storage unit, whether the data state of the data information is a clean state or a dirty state needs to be judged before the data information is removed, when the data state is the dirty state, the data information needs to be written into a system memory firstly and then removed from the selected storage unit, and when the data state is clean, the data information is directly removed from the storage space; when the selected storage unit stores the directory information, it may be determined whether the data information corresponding to the directory information needs to be removed, and if the corresponding data information needs to be removed, the method for removing the data information may refer to the method for removing the data information, and then the directory information is removed from the selected storage unit. When a plurality of directory information are stored in the selected storage unit, only one directory storage may be removed, and a plurality of directory information may also be removed, which is not limited in the present disclosure.

For example, when there is a free storage space in the storage group of the directory memory corresponding to the directory information to be stored, the directory information to be stored that needs to be stored in the directory memory may be directly stored in the free storage space.

For example, in some embodiments, the selected memory cells of the memory banks on the directory memory may include a storage flag bit, an address bit, a status bit, as shown in FIG. 2, and memory cell B1 may be an example of a selected memory cell. For example, the storage flag bits, the address bits, the status bits, and the like are merely exemplary partitions, not actual structural differences, the size of each memory cell may be fixed, and the storage flag bits, the address bits, the status bits, and the like may be partitioned according to the information stored in the memory cells.

Fig. 7 is a schematic diagram of the step of "storing directory information to be stored in a selected storage unit" in fig. 6.

As shown in fig. 7, the "storing directory information to be stored in the selected storage unit" in step S204 may include the following three steps S501 to S503.

Step S501, set the storage flag bit as the directory flag.

Step S502, store the directory address in the directory information to be stored in the address bit.

Step S503, storing the cache state in the directory information to be stored in the state bit.

For example, step S501 may include: the storage Flag bit (Flag) set in the selected storage unit for indicating the data type stored in the selected storage unit (for example, the data type includes data information and directory information) is set as a Flag indicating directory information, that is, set as a directory Flag. For example, a binary number "1" may be used to indicate the flag of the directory information, that is, when the storage flag bit of the storage unit is set to "1", the content stored by the storage unit is the directory information.

For example, the address bits in step S502 may be adjusted according to the format, size, and the like of the actual directory address, which is not limited by this disclosure.

For example, in step S503, the cache status may be used to indicate a storage status of the data information corresponding to the directory information in the plurality of caches. The status bit in step S503 may be adaptively adjusted according to the characteristics of the format of the actual buffer status, and the like, which is not limited in this disclosure.

Some embodiments of the present disclosure also provide a data processing apparatus applied to an electronic device, where the electronic device includes a directory memory and a plurality of caches used by the plurality of processors, the directory memory is configured to store directory information corresponding to data information stored in the plurality of caches, the directory memory includes a plurality of storage groups, each storage group includes at least one storage unit, and the data processing apparatus includes: the data receiving module is configured to receive data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in the system memory; and the first data operation module is configured to respond to the existence of a free storage unit in a storage group corresponding to the data address in the directory memory, and store the data information to be stored in the free storage unit.

The technical effect of the data processing apparatus is the same as that of the data processing method provided by the present disclosure, and is not described herein again.

Fig. 8 is a schematic diagram of a data processing apparatus according to some embodiments of the present disclosure.

For example, the data processing apparatus may be applied to an electronic device provided in an embodiment of the present disclosure, for example, the electronic device 100 described above. The data processing device can be used for executing the data processing method provided by the embodiment of the disclosure.

As shown in fig. 8, in some embodiments of the present disclosure, the data processing apparatus 300 includes at least a data receiving module 310 and a first data operating module 320. For example, in other embodiments of the present disclosure, the data processing apparatus 300 may further include a second data operation module 330 and a data state setting module 340.

The data receiving module 310 is configured to receive data information to be stored, wherein the data information to be stored corresponds to a location in the system memory indicated by the data address. The data receiving module 310 may be configured to implement step S101 in the data processing method shown in fig. 3, and reference may be made to the description of step S101 in the above-mentioned embodiment of the data processing method for specific description of functions that the data receiving module 310 may implement.

The first data operation module 320 is configured to store the data information to be stored in a free storage unit in response to the free storage unit existing in the storage group corresponding to the data address in the directory memory. The first data operation module 320 may be configured to implement step S102 in the data processing method shown in fig. 3, and reference may be made to the description of step S102 in the above-mentioned embodiment of the data processing method for specific description of functions that the first data operation module 320 may implement.

The first data operation module 320 is further configured to determine selected data information in the at least one data information in response to that there is no free storage unit and at least one data information is stored in a storage group corresponding to the data address in the directory memory, move the selected data information out of the storage unit for storing the selected data information according to the data state of the selected data information, and store the data information to be stored in the storage unit for storing the selected data information. The first data operation module 320 may be further configured to implement steps S103 to S105 in the data processing method shown in fig. 3, and for a specific description of functions that the first data operation module 320 may further implement, reference may be made to the description of steps S103 to S105 in the above-described embodiment of the data processing method.

The second data operation module 330 is configured to obtain directory information to be stored in the directory memory, determine, in response to that no free storage space exists in a storage group of the directory memory corresponding to the directory information to be stored, a selected storage unit in the storage group corresponding to the directory information to be stored, and move at least part of information stored in the selected storage unit out of the selected storage unit; and storing the directory information to be stored into the selected storage unit. The second data manipulation module 330 may be configured to implement steps S201 to S204 in the data processing method shown in fig. 6, and for specific description of functions that the second data manipulation module 330 may implement, reference may be made to the description of steps S201 to S204 in the above-described embodiment of the data processing method.

The data state setting module 340 is configured to set a data state of data information to be stored. The data state setting module 340 may be configured to implement step S106 in the data processing method shown in fig. 3, and reference may be made to the description of step S106 in the above-mentioned embodiment of the data processing method for specific description of functions that the data state setting module 340 may implement.

Fig. 9 is a schematic diagram of the first data operation module in fig. 8 according to some embodiments of the present disclosure.

As shown in fig. 9, in some embodiments of the present disclosure, the first data operation module 320 may include a first storage flag operation unit 321, a first address bit operation unit 322, a first status bit operation unit 323, and a first data bit operation unit 324.

The first storage flag operating unit 321 is configured to set a storage flag bit to a data flag. The first storage flag operating unit 321 may be used to implement step S401 in the data processing method shown in fig. 4, and specific description on the functions that the first storage flag operating unit 321 may implement may refer to the description on step S401 in the above-described embodiment of the data processing method.

The first address bit operation unit 322 is configured to store at least a portion of a data address corresponding to data information to be stored in address bits. The first address bit operation unit 322 may be used to implement step S402 in the data processing method shown in fig. 4, and specific description about functions that the first address bit operation unit 322 may implement may refer to the description about step S402 in the above-described embodiment of the data processing method.

The first state bit operation unit 323 is configured to store a data state corresponding to data information to be stored in a state bit. The first status bit operation unit 323 may be used to implement step S403 in the data processing method shown in fig. 4, and specific description about the functions that the first status bit operation unit 323 may implement may refer to the description about step S403 in the above-described embodiment of the data processing method.

The first data bit operation unit 324 is configured to store data information to be stored in data bits. The first data bit operation unit 324 may be used to implement step S404 in the data processing method shown in fig. 4, and reference may be made to the description of step S404 in the above-mentioned embodiment of the data processing method for specific description of the functions that the first data bit operation unit 324 may implement.

Fig. 10 is a schematic diagram of the second data operation module in fig. 8 according to some embodiments of the present disclosure.

As shown in fig. 10, in some embodiments of the present disclosure, the second data operation module 330 may include a second storage flag operation unit 331, a second address bit operation unit 332, and a second status bit operation unit 333.

The second storage flag operating unit 331 is configured to set the storage flag bit to the directory flag. The second storage flag operating unit 331 can be used to implement step S501 in the data processing method shown in fig. 7, and specific description of functions that the second storage flag operating unit 331 can implement can refer to the description of step S501 in the above-described embodiment of the data processing method.

The second address bit operation unit 332 is configured to store a directory address in directory information to be stored in address bits. The second address bit operation unit 332 can be used to implement step S502 in the data processing method shown in fig. 7, and specific description of functions that the second address bit operation unit 332 can implement can refer to the description of step S502 in the above-described embodiment of the data processing method.

The second state bit operating unit 333 is configured to store the cache state in the directory information to be stored in the state bit. The second status bit operation unit 333 may be used to implement step S503 in the data processing method shown in fig. 7, and for a specific description of the functions that the second status bit operation unit 333 may implement, reference may be made to the description of step S503 in the above-mentioned embodiments of the data processing method.

For example, data transmission may be implemented between the data receiving module 310, the first data manipulation module 320, the second data manipulation module 330, and the data state setting module 340.

For example, the data receiving module 310, the first data manipulation module 320, the second data manipulation module 330, and the data state setting module 340 may be implemented in hardware, software, firmware, or any feasible combination thereof.

For example, the components such as the data receiving module 310, the first data operating module 320, the second data operating module 330, and the data state setting module 340 may communicate in a wired or wireless manner, for example, the components such as the data receiving module 310, the first data operating module 320, the second data operating module 330, and the data state setting module 340 may be interconnected through a bus to implement communication, or the components such as the data receiving module 310, the first data operating module 320, the second data operating module 330, and the data state setting module 340 may also communicate through a network, which is not limited in this embodiment of the disclosure.

Fig. 11 is a schematic diagram of a data processing apparatus according to some embodiments of the present disclosure.

As shown in fig. 11, a data processing apparatus 400 according to an embodiment of the present disclosure may include a processor 401 and a memory 402, which may be interconnected by a bus 403. It should be noted that the components of the data processing apparatus 400 shown in fig. 11 are only exemplary and not limiting, and the data processing apparatus 400 may also have other components according to the actual application requirements.

The processor 401 may perform various actions and processes according to programs or codes stored in the memory 402. In particular, the processor 401 may be an integrated circuit chip having signal processing capabilities. For example, the processor 401 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, flows, and logic blocks disclosed in the embodiments of the disclosure may be implemented or performed. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, either of the X86 architecture or the ARM architecture or the like.

The memory 402 is used for non-transitory storage of computer-executable instructions and the processor 401 is used for execution of the computer-executable instructions. The computer-executable instructions, when executed by the processor 401, implement the data processing methods provided by at least one embodiment of the present disclosure.

For example, the memory 402 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.

The technical effect of the data processing apparatus shown in fig. 11 is the same as that of the data processing method provided by the present disclosure, and is not described herein again.

Embodiments of the present disclosure also provide a non-transitory storage medium, which may be a computer-readable storage medium, for non-transitory storage of computer-executable instructions that, when executed by a computer, implement the data processing methods provided by some embodiments of the present disclosure.

As shown in fig. 12, the non-transitory storage medium 500 may store, non-transitory, computer-executable instructions 510, the computer-executable instructions 510 implementing the data processing method provided by any embodiment of the present disclosure when executed by a computer.

Similarly, computer-readable storage media in embodiments of the disclosure may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.

Embodiments of the present disclosure also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data processing method according to the embodiment of the disclosure.

The technical effects of the data processing apparatus and the storage medium are the same as those of the data processing method, and are not described herein again.

It is to be noted that the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises at least one executable instruction for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In general, the various example embodiments of this disclosure may be implemented in hardware or special purpose circuits, software, firmware, logic or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of embodiments of the disclosure have been illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

For the present disclosure, there are also the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) In the drawings used to describe embodiments of the present disclosure, the thickness and size of layers or structures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A data processing method is applied to electronic equipment, wherein the electronic equipment comprises a directory memory and a plurality of caches used by a plurality of processors, the directory memory is used for storing directory information corresponding to data information stored in the caches, the directory memory comprises a plurality of memory groups, each memory group comprises at least one memory unit,

the data processing method comprises the following steps:

receiving data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory;

responding to the free storage unit in the storage group corresponding to the data address in the directory memory, storing the data information to be stored in the free storage unit,

wherein the data information to be stored is data information read from the data address of the system memory, or the data information to be stored is data information written to the data address of the system memory.

2. The method of claim 1, further comprising:

in response to no free memory cell in the memory bank corresponding to the data address in the directory memory and at least one data information stored therein:

determining selected data information of the at least one data information,

moving the selected data information out of a storage unit for storing the selected data information according to the data state of the selected data information,

and storing the data information to be stored into the storage unit.

3. The method of claim 2, wherein said moving the selected data information out of the storage location for storing the selected data information according to the data state of the selected data information comprises:

in response to the data state of the selected data information indicating that the selected data information has been modified, writing the selected data information to the system memory before moving the selected data information out of the memory cell for storing the selected data information;

in response to the data state of the selected data information indicating that the selected data information is not modified, directly moving the selected data information out of the storage unit for storing the selected data information.

4. The method of claim 1, further comprising:

acquiring the directory information to be stored which needs to be stored in the directory memory,

in response to no free storage space in a storage group of the directory memory corresponding to the to-be-stored directory information:

determining a selected storage unit in a storage group corresponding to the directory information to be stored;

moving at least part of the information stored in the selected memory cell out of the selected memory cell;

and storing the directory information to be stored into the selected storage unit.

5. The method of claim 4, wherein the selected storage unit is for storing data information or at least one directory information.

6. The method of claim 1, further comprising: setting the data state of the data information to be stored,

wherein, setting the data state of the data information to be stored comprises:

setting a data state of the data information to be stored to a first state in response to the data information to be stored in at least one of the plurality of caches having been modified,

setting the data state of the data information to be stored to a second state in response to the data information to be stored in at least one of the plurality of caches not being modified.

7. The method of any of claims 1-6, wherein the free memory location comprises: storing flag bits, address bits, status bits and data bits,

storing the data information to be stored in the idle storage unit, including:

setting the storage zone bit as a data mark;

storing at least a portion of the data address in the address bits;

storing the data state corresponding to the data information to be stored in the state bit;

and storing the data information to be stored in the data bits.

8. The method of claim 4 or 5, wherein the selected memory cell comprises: storing a flag bit, an address bit and a status bit,

storing the directory information to be stored in the selected storage unit, including:

setting the storage flag bit as a directory flag;

storing the directory address in the directory information to be stored in the address bit;

and storing the cache state in the directory information to be stored in the state bit.

9. A data processing device is applied to an electronic device, wherein the electronic device comprises a directory memory and a plurality of caches used by a plurality of processors, the directory memory is used for storing directory information corresponding to data information stored in the caches, the directory memory comprises a plurality of storage groups, each storage group comprises at least one storage unit,

the data processing apparatus includes:

the data receiving module is configured to receive data information to be stored, wherein the data information to be stored corresponds to a position indicated by a data address in a system memory;

a first data operation module configured to respond to a free storage unit existing in a storage group corresponding to the data address in the directory memory, store the data information to be stored in the free storage unit,

10. The data processing apparatus of claim 9,

the first data operation module is further configured to respond to that no free storage unit exists in the storage group corresponding to the data address in the directory memory and at least one piece of data information is stored:

determining selected data information of the at least one data information,

and storing the data information to be stored into the storage unit.

11. The data processing apparatus of claim 9, further comprising:

a second data manipulation module configured to:

acquiring to-be-stored directory information needing to be stored in the directory memory, and responding to the fact that no free storage space exists in a storage group of the directory memory corresponding to the to-be-stored directory information:

determining a selected storage unit in a storage group corresponding to the directory information to be stored,

12. The data processing apparatus of claim 9, further comprising: a data state setting module configured to set a data state of the data information to be stored, wherein,

when performing an operation of setting a data state of the data information to be stored, the data state setting module is configured to:

13. The data processing apparatus according to any of claims 9-12, wherein the free memory unit comprises: storing flag bits, address bits, status bits, and data bits, the first data manipulation module comprising:

a first storage flag operating unit configured to set the storage flag bit to a data flag;

a first address bit operation unit configured to store at least a portion of the data address in the address bits;

a first state bit operation unit configured to store a data state corresponding to the data information to be stored in the state bit;

a first data bit operation unit configured to store the data information to be stored in the data bits.

14. The apparatus of claim 11, wherein the selected memory cell comprises:

storing flag bits, address bits and status bits, the second data manipulation module comprising:

a second storage flag operating unit configured to set the storage flag bit to a directory flag;

a second address bit operation unit configured to store a directory address in the directory information to be stored in the address bit;

and the second state bit operation unit is configured to store the cache state in the directory information to be stored in the state bit.

15. A data processing apparatus comprising:

a memory for non-transitory storage of computer-executable instructions; and

a processor for executing the computer-executable instructions,

wherein the computer-executable instructions, when executed by the processor, perform a data processing method according to any one of claims 1 to 8.

16. A non-transitory storage medium storing, non-transitory, computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform the data processing method of any one of claims 1-8.