CN106406745A - Method and device for maintaining Cache data uniformity according to directory information - Google Patents
Method and device for maintaining Cache data uniformity according to directory information Download PDFInfo
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- CN106406745A CN106406745A CN201510447072.5A CN201510447072A CN106406745A CN 106406745 A CN106406745 A CN 106406745A CN 201510447072 A CN201510447072 A CN 201510447072A CN 106406745 A CN106406745 A CN 106406745A
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- caching
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
Abstract
The invention discloses a method and device for maintaining the Cache data uniformity according to directory information. The method includes: receiving a data block state change request; determining a designated data block in a main memory system area according to the data block state change request; determining a target processor according to directory information saved in a main memory, wherein the target processor has stored the designated data block in a processor Cache; and sending a state change instruct to the target processor, wherein the data block state change request is used for requesting the target processor to change the state of the designated data block saved in the target processor Cache. According to the method and the device, the directory information is stored in the main memory, use of a directory memory space of an interconnected chip can be avoided, and the difficulty of an NUMA system and implementation can be reduced.
Description
Technical field
The present invention relates to data block process field, the method more particularly, to Cache data consistency being safeguarded according to directory information
And device.
Background technology
Distributed shared memory multicomputer system refers at the data block that is made up of a common storage and multiple processor
Reason system.In many eurypalynous Distributed shared memory multicomputer systems, Non Uniform Memory Access framework (Non Uniform
Memory Access Architecture, abbreviation NUMA) system with its convenient programmed environment and preferable extensibility,
Become the most frequently used Distributed shared memory multicomputer system.
NUMA system is generally made up of multiple multicomputer systems, can be by main storage in each of which subsystem
(Main Memory) and some processors (Processer) are constituted, and can share main memory between each subprocessing system
The space of reservoir.Due to each processor shared main storage in NUMA system, each processor can rewrite primary storage
Arbitrary data block in device, and each processor high speed buffer storage (Cache) can also cache appointing in main storage
Meaning data block, consequently, it is possible to after occurring that first processor Cache has cached certain data block in main storage, this data
The situation that block is rewritten by second processing device again, leads to the number in data that first processor Cache cached and main storage
According to inconsistent.Because the quantity of processor is more in NUMA system, data and master that processor Cache is cached occur
The inconsistent probability of data in memorizer is bigger, and therefore processor high speed buffer storage (Cache) data is consistent
Sex chromosome mosaicism, becomes the key issue limiting NUMA system scale and extensibility.
In prior art, NUMA system would generally ensure Cache data using the directory information being saved on interconnection die
Concordance.Specifically, an interconnection die would generally be provided with existing NUMA system, open up in this interconnection die
Catalogue memory space, this catalogue memory space is used for the information of saving contents, and described directory information is used for recording in main storage
Whether each data block is cached by processor Cache, and is cached by which processor Cache.When certain refers to
Determine processor need change main storage in certain data block when, first processor is determined whether according to directory information
This data block buffered in Cache；When finding to be cached with this data block in target processor Cache, this is specified
Processor can to this target processor send point-to-point message so that in its target processor Cache caching should
Data block lost efficacy, and after having sent described point-to-point message, described given processor could change this data block.Using
This mode it can be ensured that in each processor Cache in system the data block of caching consistent with data block in main storage,
Thus solving the consistency problem of processor Cache data.
When ensureing the concordance of processor Cache data using directory information, the extension of NUMA system and processor are individual
The increase of number can lead to the data volume of directory information to increase therewith, and the memory space of catalog memory is also required to believe with catalogue
Breath the increase of data volume and increase.Therefore, the consistency problem of processor Cache data is solved using existing method,
Have it is therefore desirable to carry out storage catalogue information interconnection chip using catalogue memory space relatively when NUMA system is larger
Larger storage, and the adjoint cost of catalogue memory space increasing is interconnection die complex structure and chip area is significantly increased.
And interconnection die complex structure and chip area are significantly increased, then can increase NUMA system design and the difficulty realized.
Content of the invention
Embodiments provide the method and device safeguarding Cache data consistency according to directory information, can reduce
NUMA system design and the difficulty realized.
In a first aspect, embodiments providing a kind of method that Cache data consistency is safeguarded according to directory information,
Directory information is saved in main storage, and described directory information is used for recording in main memory system region data block by each
The situation that processor high speed buffer storage is cached, methods described includes：The change request of receiving data bulk state；According to
Described data block status change request determines the specified data block in main memory system region；According to being saved in described main memory
Directory information in reservoir determines target processor, wherein, described target processor refer to by specified data block store to
Processor in processor Cache；Send Status Change instruction, described data block status change to described target processor
Ask to have cached the state of described specified data block for asking described target processor to change in target processor Cache.
In conjunction with a first aspect, in the first possible implementation in first aspect, described basis is saved in described primary storage
Directory information in device determines that target processor includes：Detect in the directory area of described main storage whether there is with described
Specified data block corresponding assigned catalogue information, the directory area of described main storage is used for preserving described directory information；When
When there is described assigned catalogue information in the directory area of described main storage, according to described assigned catalogue information determines
Target processor.
In conjunction with a first aspect, in the possible implementation of first aspect second, described basis is saved in described primary storage
Directory information in device determines that target processor includes：Specify with the presence or absence of with described in the Directory caching of detection interconnection die
Data block corresponding assigned catalogue information；When there is not described assigned catalogue information in the Directory caching of interconnection die, inspection
Survey the assigned catalogue information corresponding with described specified data block that whether there is in the directory area of described main storage；When described
When there is described assigned catalogue information in the directory area of main storage, described target is determined according to described assigned catalogue information
Processor.
In conjunction with the possible implementation of first aspect second, in the third possible implementation in second aspect, described
Method also includes：When there is described assigned catalogue information in the Directory caching of interconnection die, believed according to described assigned catalogue
Breath determines described target processor.
In conjunction with the possible implementation of first aspect second, in the 4th kind of possible implementation of second aspect, described
Method also includes：When there is not described assigned catalogue information in the Directory caching of interconnection die, update described Directory caching
In directory information.
In conjunction with the second to four kind of possible implementation of first aspect any one, in the 5th kind of possible reality of second aspect
In existing mode, the directory information preserving in described Directory caching is by the directory information in described main storage directory area with many
The road group mode of being connected maps generation.
In conjunction with the possible implementation of first aspect or the first to five kind of first aspect any one, in first aspect the 6th
Plant in possible implementation it is characterised in that described send Status Change instruction inclusion to target processor：When described
When data block status change request is for data block overwrite request, send Indication of Losing Efficacy, described inefficacy to described target processor
Indicate the described specified data block for indicating caching in described target processor faulty target processor Cache；Or,
When the change request of described data block status is for data block sharing request, send shared instruction, institute to described target processor
State shared instruction for indicating that the described specified data block of caching in target processor Cache is repaiied by described target processor
It is changed to shared model.
In conjunction with the possible implementation of first aspect or the first to six kind of first aspect any one, in first aspect the 7th
Plant in possible implementation, described directory information includes access state field, information state field and caching indication field,
Wherein said access state field is used for indicating whether described directory information is accessed, and described information mode field is used for
Indicate the state of described directory information, described caching indication field is used for indicating that corresponding to described directory information, data block is located
The situation that reason device Cache is cached.
Second aspect, embodiments provides a kind of device safeguarding Cache data consistency according to directory information,
Directory information is saved in main storage, and described directory information is used for recording in main memory system region data block by each
The situation that processor high speed buffer storage is cached, described device includes：Receiving unit, for receiving data bulk state
Change request；Specified data block determining unit, for determining main memory system according to the change request of described data block status
Specified data block in region；Target processor determining unit, for according to the catalogue letter being saved in described main storage
Breath determines target processor, and wherein, described target processor refers to store specified data block to processor Cache
Processor；Transmitting element, for sending Status Change instruction, described data block status change to described target processor
Ask to have cached the state of described specified data block for asking described target processor to change in target processor Cache.
In conjunction with second aspect, in the first possible implementation in second aspect, described target processor determining unit,
Including：First detection sub-unit, for detect in the directory area of described main storage with the presence or absence of and described specified data
Block corresponding assigned catalogue information, the directory area of described main storage is used for preserving described directory information；First determines son
Unit, during for there is described assigned catalogue information in the directory area of described main storage, according to described assigned catalogue
Information determines described target processor.
In conjunction with second aspect, in the possible implementation of second aspect second, described target processor determining unit,
Including：Second detection sub-unit, for detect in the Directory caching of interconnection die with the presence or absence of and described specified data block pair
The assigned catalogue information answered；, for there is not described specified mesh in the Directory caching of interconnection die in the 3rd detection sub-unit
During record information, detect and in the directory area of described main storage, whether there is assigned catalogue corresponding with described specified data block
Information；Second determination subelement, during for there is described assigned catalogue information in the directory area of described main storage,
Described target processor is determined according to described assigned catalogue information.
In conjunction with the possible implementation of second aspect second, in the third possible implementation in second aspect, described
Second determination subelement, when being additionally operable to exist described assigned catalogue information in the Directory caching of interconnection die, according to described
Assigned catalogue information determines described target processor.
In conjunction with the possible implementation of second aspect second, in the 4th kind of possible implementation of second aspect, described
Target processor determining unit, also includes：Update subelement, described for not existing in the Directory caching of interconnection die
During assigned catalogue information, update the directory information in described Directory caching
In conjunction with the second to four kind of possible implementation of second aspect any one, in the 5th kind of possible reality of second aspect
In existing mode, the directory information preserving in described Directory caching is by the directory information in described main storage directory area with many
The road group mode of being connected maps generation.
In conjunction with the possible implementation of second aspect or the first to five kind of second aspect any one, in second aspect the 6th
Plant in possible implementation, described transmitting element, please for rewriting for data block when the change request of described data block status
When asking, send Indication of Losing Efficacy to described target processor, described Indication of Losing Efficacy is used for indicating described target processor inefficacy mesh
Mark the described specified data block of caching in processor Cache；Or, for when the change request of described data block status being
During data block sharing request, send shared instruction to described target processor, described shared indicate for indicating described target
The described specified data block of caching in target processor Cache is revised as shared model by processor.
In conjunction with the possible implementation of second aspect or the first to six kind of second aspect any one, in second aspect the 7th
Plant in possible implementation, described directory information includes access state field, information state field and caching indication field,
Wherein said access state field is used for indicating whether described directory information is accessed, and described information mode field is used for
Indicate the state of described directory information, described caching indication field is used for indicating that corresponding to described directory information, data block is located
The situation that reason device Cache is cached.
In embodiments of the present invention, receiving data bulk state change request；Determined according to the change request of described data block status
Specified data block in main memory system region；Directory information according to being saved in described main storage determines at target
Reason device, wherein, described directory information is used for recording in main memory system region data block by each processor Cache institute
The situation of caching, described target processor refers to specified data block be stored the processor to processor Cache；To
Described target processor sends Status Change instruction, and described data block status change request is used for asking described target processor
The state of described specified data block has been cached in change target processor Cache.Using the embodiment of the present invention, directory information
It is stored in main storage, such that it is able to avoid carrying out storage catalogue information using the catalogue memory space of interconnection chip, reduce
NUMA system design and the difficulty realized.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Technology description in required use accompanying drawing be briefly described it should be apparent that, for those of ordinary skill in the art
Speech, without having to pay creative labor, can also obtain other accompanying drawings according to these accompanying drawings.
The flow chart that Fig. 1 safeguards one embodiment of method of Cache data consistency for the present invention according to directory information；
Fig. 2 is the structural representation of directory information of the present invention；
Fig. 3 safeguards the schematic diagram of one embodiment of device of Cache data consistency for the present invention according to directory information.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Description it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiment.Base
Embodiment in the present invention, it is all that those of ordinary skill in the art are obtained under the premise of not making creative work
Other embodiment, broadly falls into the scope of protection of the invention.
Here, can be by least one many places it should be noted that this non-uniform internal storage access architecture system of its present invention
Reason device system (Multiprocessor Systems) is constituted, and each of which multicomputer system can comprise primary storage
Device (Main Memory) and at least two processors, directory information can be saved in main storage.Wherein, primary storage
Device comprises directory area and system realm, is used for, in described directory area, the information of saving contents, and system realm is used for preserving
The required data block preserving of main storage, each directory area both can be used for storing its affiliated main memory system region
The directory information of middle data block is it is also possible to be used for storing the directory information of data block in other main memory system regions.
Referring to Fig. 1, it is the flow process of one embodiment of method that the present invention safeguards Cache data consistency according to directory information
Schematic diagram.The method comprises the steps：
Step 101, the change request of receiving data bulk state.
The receiving data bulk state change request first of processor in NUMA system, wherein said data block status change request
Can be sent by the application in system.Wherein, described data block status change request can be data block overwrite request, number
According to block sharing request etc., wherein, data block overwrite request is used for certain data block that request is rewritten in main storage, and data
Block sharing request is used for asking certain data block in shared main storage.
Step 102, determines the specified data block in main memory system region according to the change request of described data block status.
Processor, after receiving data block status change request, determines needs according to the change request of this data block status first
Rewritten which data block in main memory system region.
For example, when described data block status change the address realm carrying specified data block in request it is believed that being somebody's turn to do
Data block in address realm is specified data block.Carry specified data block in the change request of described data block status
Initial address, and can according to data block status change request determine specified data block size when, can be according to described
The size of the initial address of specified data block and specified data block determines specified data block.
Step 103, the directory information according to being saved in described main storage determines target processor, wherein, described mesh
Record information is used for recording the situation that in main memory system region, data block is cached by each processor Cache, described mesh
Mark processor refers to specified data block be stored the processor to processor Cache.
After specified data block is determined, processor can detect in the directory area of described main storage with the presence or absence of with
The corresponding assigned catalogue information of described specified data block；Believe when there is described assigned catalogue in described main storage directory area
During breath, described target processor is determined according to described assigned catalogue information.
In described main storage directory area, each directory information can be with the data of a fixed size in main storage
Block is corresponding, and the size of this data block can pre-set as needed, for example, it is possible to each with processor Cache
The size of individual cache lines (Cacheline) is identical.
Directory information in directory area can be to adopt principle of locality to map generation in the multichannel group mode of being connected.Using local
Property principle, and map generation directory information in the way of multichannel group is connected, can only generate in main storage and may be processed
The corresponding directory information of data block of device Cache caching, without the corresponding catalogue of data blocks all in generation main storage
Information, such that it is able to greatly reduce the data volume of directory information, reduces the space shared by directory area；And system area
In domain, the corresponding information of the data block of fixing address can be stored in the fixing address of directory area, according to the address of data block
The preservation address determining the corresponding directory information of this data block can be tolerated very much, such that it is able to accelerate the lookup speed of directory information.
Wherein, the structure of described directory information can be as shown in Fig. 2 described directory information includes access state field, letter
Breath mode field, caching indication field, wherein said access state field be used for indicating described directory information whether by
Access, described information mode field is used for indicating the state of described directory information, described caching indication field is used for indicating institute
State the situation that data block corresponding to directory information is cached by processor Cache.Under normal circumstances, described access state word
The length of section can be 1bit, and the length of described information mode field can be 3bit, and the length caching indication field can
Think 4bit.Wherein, the situation that data block corresponding to described directory information is cached by processor Cache refers to, described
Whether the corresponding data block of directory information is cached and cached by which processor Cache by processor Cache.
For accelerating the processing speed that data block is rewritten, described NUMA system can also include an interconnection die, this interconnection
It is provided with Directory caching, this Directory caching is used for directory information in cache way storage main storage directory area on chip.
For reducing the space of Directory caching, the directory information preserving in described Directory caching is by described main storage directory area
Directory information maps generation in the multichannel group mode of being connected.
Therefore after specified data block determination, processor can also first detect in the Directory caching of interconnection die and whether there is
Assigned catalogue information corresponding with described specified data block；Believe when there is described assigned catalogue in the Directory caching of interconnection die
During breath, described target processor is determined according to described assigned catalogue information.When there is not institute in the Directory caching of interconnection die
When stating assigned catalogue information, processor detect again in the directory area of described main storage with the presence or absence of and described specified data
Block corresponding assigned catalogue information；When there is described assigned catalogue information in described main storage directory area, according to institute
State assigned catalogue information and determine described target processor.
If described directory information includes access state field, information state field, caching indication field, according to specified
The content of the caching indication field of described assigned catalogue information when directory information determines target processor, can be analyzed, according to
The content of caching indication field determines target processor.For example, first processor Cache is being determined according to caching indication field
In be cached with during this specified data block it may be determined that first processor is target processor.True according to caching indication field
Determine all to be cached with second processing device Cache and the 3rd processor Cache during this specified data block it may be determined that at second
Reason device and the 3rd processor are target processor.
If all there is not assigned catalogue information in the Directory caching of interconnection die and described main storage directory area, can
To think that specified data block do not cache by any one processor Cache, processor can be according to described data block status
The state of described specified data block is directly changed in change request.
Step 104, sends Status Change instruction to described target processor, described data block status change request is used for please
Seek the state having cached described specified data block in described target processor change target processor Cache.
If determining there is target processor according to described directory information, then processor can be sent out to described target processor
Status Change is sent to indicate, described data block status change request is used for asking described target processor change target processor
The state of described specified data block has been cached in Cache.Target processor can change request according to described data block status
Change the state of described specified data block, thereby may be ensured that the concordance of data in each processor Cache.
Change the difference of request type according to data block status, what described Status Change indicated can differ.For example, when
When described data block status change request is for data block overwrite request, send Indication of Losing Efficacy to described target processor, described
Indication of Losing Efficacy is used for indicating the described specified data block of caching in described target processor faulty target processor Cache；
Or, when the change request of described data block status is for data block sharing request, send shared finger to described target processor
Show, described shared indicate for indicating described target processor by the described specified number of caching in target processor Cache
It is revised as shared model according to block.
Target processor, after receiving described Status Change instruction, can change according to Status Change instruction and specify data
The state of block.For example, when target processor receives Indication of Losing Efficacy, this inefficacy in target processor Cache can be made
Indicate that corresponding specified data block lost efficacy；And when target processor receives shared instruction, then can share target and process
This corresponding specified data block of shared instruction in device Cache.
In the present embodiment, receiving data bulk state change request；Determined according to the change request of described data block status and host
Specified data block in reservoir system region；Directory information according to being saved in described main storage determines target processor,
Wherein, described directory information is used for recording what data block in main memory system region was cached by each processor Cache
Situation, described target processor refers to specified data block be stored the processor to processor Cache；To described mesh
Mark processor sends Status Change instruction, and described data block status change request is used for asking described target processor change mesh
The state of described specified data block has been cached in mark processor Cache.Using the present embodiment, directory information is stored in main memory
In reservoir, such that it is able to avoid carrying out storage catalogue information using the catalogue memory space of interconnection chip, reduce NUMA system and set
Meter and the difficulty realized.
Corresponding with the embodiment of the method safeguarding Cache data consistency according to directory information, the embodiment of the present invention also carries
Supply the embodiment of the device safeguarding Cache data consistency according to directory information.
Referring to Fig. 3, it is the structure of one embodiment of device that the present invention safeguards Cache data consistency according to directory information
Schematic diagram, wherein, directory information is saved in main storage, and the directory information preserving in described Directory caching is by described master
Directory information in memorizer directory area maps generation in the multichannel group mode of being connected.This device can be used for executing aforementioned reality
Apply the method in example, Cache data consistency being safeguarded according to directory information.
As shown in figure 3, described device can include：Receiving unit 301 is it is intended that data block determining unit 302, target
Processor determining unit 303 and transmitting element 304.
Wherein, receiving unit 301, change request for receiving data bulk state；Specified data block determining unit 302,
For the specified data block in main memory system region is determined according to the change request of described data block status；Target processor
Determining unit 303, for target processor is determined according to the directory information being saved in described main storage, wherein, institute
State target processor to refer to specified data block be stored the processor to processor Cache；Transmitting element 304, uses
In sending Status Change instruction to described target processor, described data block status change request is used for asking at described target
Reason device changes the state having cached described specified data block in target processor Cache.
Optionally, described target processor determining unit 303, including：First detection sub-unit, for detecting described master
Whether there is assigned catalogue information corresponding with described specified data block in the directory area of memorizer, described main storage
Directory area is used for preserving described directory information；First determination subelement, in the directory area of described main storage
When there is described assigned catalogue information, described target processor is determined according to described assigned catalogue information.
Optionally, described target processor determining unit 303, including：Second detection sub-unit, for detection interconnection core
Whether there is assigned catalogue information corresponding with described specified data block in the Directory caching of piece；3rd detection sub-unit, uses
When there is not described assigned catalogue information in the Directory caching of interconnection die, detect the directory area of described main storage
In whether there is assigned catalogue information corresponding with described specified data block；Second determination subelement, in described main memory
When there is described assigned catalogue information in the directory area of reservoir, determine that described target is processed according to described assigned catalogue information
Device.Wherein, described second determination subelement, can be also used for there is described specified mesh in the Directory caching of interconnection die
During record information, described target processor is determined according to described assigned catalogue information.Described target processor determining unit 303,
Can also include：Update subelement, during for there is not described assigned catalogue information in the Directory caching of interconnection die,
Update the directory information in described Directory caching.
Optionally, described transmitting element 304, for when described data block status change request for data block overwrite request when,
Send Indication of Losing Efficacy to described target processor, described Indication of Losing Efficacy is used for indicating that described target processor faulty target is processed
The described specified data block of caching in device Cache；Or, for being data block when the change request of described data block status
During sharing request, send shared instruction to described target processor, described shared indicate for indicating described target processor
The described specified data block of caching in target processor Cache is revised as shared model.Wherein, described directory information
Access state field, information state field and caching indication field can be included, wherein said access state field is used for referring to
Show whether described directory information is accessed, described information mode field is used for indicating the state of described directory information, institute
State caching indication field to be used for indicating the situation that data block corresponding to described directory information is cached by processor Cache.
In the present embodiment, included according to the device that directory information safeguards Cache data consistency：Receiving unit, is used for
The change request of receiving data bulk state；Specified data block determining unit, for according to the change request of described data block status really
Determine the specified data block in main memory system region；Target processor determining unit, is saved in described main memory for basis
Directory information in reservoir determines target processor, transmitting element, refers to for sending Status Change to described target processor
Show.Using the present embodiment, directory information is stored in main storage, such that it is able to avoid depositing using the catalogue of interconnection chip
Storage catalogue information is carried out in storage space, reduces NUMA system design and the difficulty realized.
Those skilled in the art can be understood that technology in the embodiment of the present invention can be by software plus necessary
The mode of general hardware platform is realizing.Based on such understanding, the technical scheme in the embodiment of the present invention substantially or
Say that what prior art was contributed partly can be embodied in the form of software product, this computer software product is permissible
It is stored in storage medium, such as ROM/RAM, magnetic disc, CD etc., including some instructions with so that a computer sets
Standby (can be personal computer, server, or network equipment etc.) execution each embodiment of the present invention or embodiment
Some partly described methods.
Each embodiment in this specification is all described by the way of going forward one by one, identical similar part between each embodiment
Mutually referring to what each embodiment stressed is the difference with other embodiment.Especially for device
For embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, referring to method in place of correlation
The part of embodiment illustrates.
Invention described above embodiment, does not constitute limiting the scope of the present invention.Any the present invention's
Modification, equivalent and improvement made within spirit and principle etc., should be included within the scope of the present invention.
Claims (16)
1. a kind of according to directory information safeguard cache memory Cache data consistency method it is characterised in that
Directory information is saved in main storage, and described directory information is used for recording in main memory system region data block by each
The situation that processor high speed buffer storage is cached, methods described includes：
The change request of receiving data bulk state；
Specified data block in main memory system region is determined according to the change request of described data block status；
Directory information according to being saved in described main storage determines target processor, and wherein, described target processor is
Refer to specified data block be stored the processor to processor Cache；
Send Status Change instruction to described target processor, described data block status change request is used for asking described target
Processor changes the state having cached described specified data block in target processor Cache.
2. the method for claim 1 is it is characterised in that described basis is saved in the catalogue in described main storage
Information determines that target processor includes：
Detect in the directory area of described main storage and whether there is assigned catalogue information corresponding with described specified data block,
The directory area of described main storage is used for preserving described directory information；
When there is described assigned catalogue information in the directory area of described main storage, true according to described assigned catalogue information
Fixed described target processor.
3. the method for claim 1 is it is characterised in that described basis is saved in the catalogue in described main storage
Information determines that target processor includes：
Whether there is assigned catalogue information corresponding with described specified data block in the Directory caching of detection interconnection die；
When there is not described assigned catalogue information in the Directory caching of interconnection die, detect the directory area of described main storage
Whether there is assigned catalogue information corresponding with described specified data block in domain；
When there is described assigned catalogue information in the directory area of described main storage, true according to described assigned catalogue information
Fixed described target processor.
4. method as claimed in claim 3 is it is characterised in that methods described also includes：
When there is described assigned catalogue information in the Directory caching of interconnection die, institute is determined according to described assigned catalogue information
State target processor.
5. method as claimed in claim 3 is it is characterised in that methods described also includes：
When there is not described assigned catalogue information in the Directory caching of interconnection die, update the catalogue in described Directory caching
Information.
6. the method as described in any one of claim 3 to 5 it is characterised in that
The directory information preserving in described Directory caching is by the directory information in described main storage directory area with multichannel group phase
Connection mode maps generation.
7. the method as described in any one of claim 1 to 6 is it is characterised in that described send state to target processor
Change instruction includes：
When the change request of described data block status is for data block overwrite request, send Indication of Losing Efficacy to described target processor,
Described Indication of Losing Efficacy is used for indicating the described specified data of caching in described target processor faulty target processor Cache
Block；Or,
When the change request of described data block status is for data block sharing request, send shared instruction to described target processor,
Described shared indicate for indicating described target processor by the described specified data block of caching in target processor Cache
It is revised as shared model.
8. the method as described in claim 1 to 7 any one it is characterised in that
Described directory information includes access state field, information state field and caching indication field, wherein said access shape
State field is used for indicating whether described directory information is accessed, and described information mode field is used for indicating described catalogue letter
The state of breath, described caching indication field is used for indicating that corresponding to described directory information, data block is delayed by processor Cache
The situation deposited.
9. a kind of according to directory information safeguard cache memory Cache data consistency device it is characterised in that
Directory information is saved in main storage, and described directory information is used for recording in main memory system region data block by each
The situation that processor high speed buffer storage is cached, described device includes：
Receiving unit, changes request for receiving data bulk state；
Specified data block determining unit, for determining in main memory system region according to the change request of described data block status
Specified data block；
Target processor determining unit, for target processor is determined according to the directory information being saved in described main storage,
Wherein, described target processor refers to specified data block be stored the processor to processor Cache；
Transmitting element, for sending Status Change instruction to described target processor, described data block status change request is used
Change the state having cached described specified data block in target processor Cache in the described target processor of request.
10. device as claimed in claim 9 is it is characterised in that described target processor determining unit, including：
First detection sub-unit, for detect in the directory area of described main storage with the presence or absence of and described specified data block
Corresponding assigned catalogue information, the directory area of described main storage is used for preserving described directory information；
First determination subelement, during for there is described assigned catalogue information in the directory area of described main storage, root
Determine described target processor according to described assigned catalogue information.
11. devices as claimed in claim 9 it is characterised in that described target processor determining unit, including：
Second detection sub-unit, for detecting in the Directory caching of interconnection die with the presence or absence of corresponding with described specified data block
Assigned catalogue information；
3rd detection sub-unit, during for there is not described assigned catalogue information in the Directory caching of interconnection die, detection
Whether there is assigned catalogue information corresponding with described specified data block in the directory area of described main storage；
Second determination subelement, during for there is described assigned catalogue information in the directory area of described main storage, root
Determine described target processor according to described assigned catalogue information.
12. devices as claimed in claim 11 it is characterised in that
Described second determination subelement, when being additionally operable to exist described assigned catalogue information in the Directory caching of interconnection die,
Described target processor is determined according to described assigned catalogue information.
13. devices as claimed in claim 11, it is characterised in that described target processor determining unit, also include：
Updating subelement, during for there is not described assigned catalogue information in the Directory caching of interconnection die, updating described
Directory information in Directory caching.
14. devices as described in any one of claim 11 to 13 it is characterised in that
The directory information preserving in described Directory caching is by the directory information in described main storage directory area with multichannel group phase
Connection mode maps generation.
15. devices as described in any one of claim 9 to 14 it is characterised in that
Described transmitting element, for when the change request of described data block status is for data block overwrite request, to described target
Processor sends Indication of Losing Efficacy, and described Indication of Losing Efficacy is used for indicating in described target processor faulty target processor Cache
The described specified data block of caching；Or, for when described data block status change request for data block sharing request when,
Send shared instruction to described target processor, described shared indicate for indicating described target processor by target processor
In Cache, the described specified data block of caching is revised as shared model.
16. devices as described in any one of claim 9 to 15 it is characterised in that
Described directory information includes access state field, information state field and caching indication field, wherein said access shape
State field is used for indicating whether described directory information is accessed, and described information mode field is used for indicating described catalogue letter
The state of breath, described caching indication field is used for indicating that corresponding to described directory information, data block is delayed by processor Cache
The situation deposited.
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| CN201510447072.5A CN106406745B (en) | 2015-07-27 | 2015-07-27 | Method and device for maintaining Cache data consistency according to directory information |
| PCT/CN2016/090778 WO2017016427A1 (en) | 2015-07-27 | 2016-07-20 | Method and device for maintaining cache data consistency according to directory information |
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| CN201510447072.5A CN106406745B (en) | 2015-07-27 | 2015-07-27 | Method and device for maintaining Cache data consistency according to directory information |
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| CN113703958A (en) * | 2021-07-15 | 2021-11-26 | 山东云海国创云计算装备产业创新中心有限公司 | Data access method, device, equipment and storage medium among multi-architecture processors |
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| CN106406745B (en) | 2020-06-09 |
| WO2017016427A1 (en) | 2017-02-02 |
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