KR101303079B1 - Apparatus and method for controlling cache coherence in virtualized environment based on multi-core - Google Patents

Abstract

The present invention relates to an apparatus, a method for controlling cache coherence in a multi-core based virtualization environment, and a recording medium recording the method. The cache coherence control method according to the present invention includes a virtual processor of a virtual machine and the cores. Generates the status information indicating whether the mapping information and the page is shared, and if the occurrence of the cache miss is detected, the mapping information and the status information is used to check whether the page is shared by the virtual machine for the cache miss detected. As a result, virtual processors belonging to the same virtual machine selectively transmit a consistency message considering the mapped core.

Description

Apparatus and method for controlling cache coherence in virtualized environment based on multi-core}

The present invention relates to a multi-core system in which a virtualization environment is implemented, and more particularly, a communication amount due to unnecessary coherency message transmission between cores by controlling cache coherency in consideration of characteristics of a virtualization environment in a system having a plurality of cores. The present invention relates to a cache coherence control apparatus and method for reducing the number of times, and a recording medium recording the method.

Virtualization is the art of abstraction of computer resources and separating them from physical resources. Conventionally, physical computing resources such as a central processing unit (CPU) and a memory are connected to an operating system (OS) to form a single computing system. That is, only one computing system could be configured in one hardware set. However, virtualization breaks this conventional concept and makes it possible to build multiple operating systems and a computing system based thereon on one physical hardware. In particular, among the various virtualization technologies, server virtualization technology allows users or companies to use multiple PCs as if they had one PC or server.

In the meantime, single-thread-based single-core technology has reached the limit of performance improvement due to excessive power consumption. In order to overcome this problem, researches on the construction of a multi-core system having a plurality of cores in one CPU have been actively conducted. Most large data processing systems are currently using multi-core systems, resulting in a relatively good performance improvement compared to using one core. In particular, these multi-core systems show greater benefits and performance improvements when dealing with parallelized tasks. In addition, the number of cores per central processing unit is expected to increase in the future as semiconductor directivity improves.

In a multi-core system, there is a local cache for faster data access for each core, and if these cores use the same shared memory, communication between the cores is needed to ensure consistency between caches. Can be. For example, assume a situation where a first core loads a variable x into its local cache, and a second core also loads a variable x into its local cache. If the second core changes the value of the variable x, a cache miss occurs due to writing, and the value recognized by the first core and the value recognized by the second core are different for the same variable x. A problem arises. This situation is called a cache coherence problem, and various techniques have been introduced to solve this problem.

The technical problem to be solved by the present invention is to overcome the limitation that the conventional virtualization technology does not deviate from the single-core base, and unnecessary communication occurs due to the coherency message transmitted to maintain cache coherency in the multi-core based virtualization environment The present invention provides a cache coherence control device and method that can solve the problem of deteriorating system performance and increasing power consumption due to such unnecessary communication.

In order to solve the above technical problem, a method of controlling cache coherence in a virtualization environment in which a plurality of virtual machines share a plurality of cores according to the present invention, mapping information between a virtual processor and the cores of the virtual machine Generating status information indicating whether a page is shared; If the occurrence of a cache miss is detected, checking whether the page is shared by the virtual machine with respect to the data where the cache miss is detected, using the generated mapping information and the generated state information; And selectively transmitting a consistency message in consideration of the mapped cores of the virtual processors belonging to the same virtual machine according to the check result.

In this case, the state information may include a virtual machine private state indicating that the page is not shared by a plurality of virtual machines, the page is shared by a plurality of virtual machines, and each of the virtual machines is shared. Read-write shared state indicating that a page can be read and written and read indicating that the page is shared by a plurality of virtual machines and each of the virtual machines can only read a shared page One of the read-only shared states.

In order to solve the above technical problem, a method for controlling cache coherence in a virtualization environment in which a plurality of virtual machines share a plurality of cores according to the present invention may include generating mapping information between a virtual processor of the virtual machine and the cores. Storing in a virtual processor map register; Generating state information indicating whether a page is shared and storing the state information in a shadow page table; And detecting occurrence of a cache miss, checking whether the cache miss is shared by the virtual machine with respect to the data detected by the cache miss, using the stored mapping information and the stored state information, thereby making it consistent only with a selected core among the plurality of cores. Sending a message.

The method of controlling cache coherency may include calculating and storing a residence counter indicating a number of data of a virtual machine loaded in a local cache of a corresponding core for each of the plurality of cores. It includes more.

Furthermore, the following provides a computer-readable recording medium having recorded thereon a program for executing a method for controlling cache coherence in a virtualization environment in which a plurality of virtual machines share a plurality of cores described above.

In order to solve the above technical problem, an apparatus for controlling cache coherence in a virtualization environment in which a plurality of virtual machines share a plurality of cores according to the present invention may generate mapping information between a virtual processor of the virtual machine and the cores. A monitoring unit for storing in a virtual processor map register and generating state information indicating whether a page is shared, and storing the state information in a shadow page table; A sharing checker that checks whether a page is shared by the virtual machine with respect to the data on which the cache miss is detected, using the stored mapping information and the stored state information when a cache miss is detected; And a processor configured to selectively transmit a consistency message in consideration of cores to which virtual processors belonging to the same virtual machine are mapped according to the check result.

At this time, the state information may include a virtual machine exclusive state indicating that the page is not shared by a plurality of virtual machines, the page is shared by a plurality of virtual machines, and each of the virtual machines reads and shares a shared page. A read-write shared state indicating that write is possible, and a read-only sharing state indicating that the page is shared by a plurality of virtual machines and that each of the virtual machines can only read a shared page, and the monitoring unit Map the page and state information of the page and store it in the shadow page table, and the shared checker checks whether the page is shared by referring to the shadow page table and a translation lookaside buffer (TLB) when data is accessed. do.

In order to solve the above technical problem, an apparatus for controlling cache coherence in a virtualization environment in which a plurality of virtual machines share a plurality of cores according to the present invention may generate mapping information between a virtual processor of the virtual machine and the cores. A residence counter indicating the number of virtual machine data loaded in a local cache of the core for each of the plurality of cores; Monitoring unit for calculating and storing; And detecting occurrence of a cache miss, checking whether the cache miss is shared by the virtual machine with respect to the data detected by the cache miss, using the stored mapping information and the stored state information, thereby making it consistent only with a selected core among the plurality of cores. It includes a processing unit for transmitting a message.

Further, in the cache coherency control apparatus described above, the monitoring unit maps the virtual processors allocated to the plurality of virtual machines and stores the virtual processors in the virtual processor map register as a snoop domain.

The present invention extends and applies virtualization technology to a multi-core based system by proposing a technique of selectively transmitting a coherency message to cores by using mapping information between virtual processors and cores and state information indicating whether a page is shared. It can improve the performance of the system by reducing the traffic according to the coherency message transmitted to maintain cache coherency under the multi-core based virtualization environment, and the power consumption can be minimized due to the reduced traffic.

1 is a diagram illustrating a basic idea of the present invention for controlling cache coherency in a virtualization environment in which a plurality of virtual machines share a plurality of cores.
2 is a diagram illustrating a process of relocation of a virtual machine in a virtualization environment according to an embodiment of the present invention.
3 is a flowchart illustrating a method of controlling cache coherency in a virtualization environment according to an embodiment of the present invention.
4 is a flowchart illustrating the cache coherency control method of FIG. 3 according to an embodiment of the present invention in more detail.
FIG. 5 illustrates an example of a method of controlling cache coherency when a cache miss page is in a read-only shared state in a virtualization environment according to an embodiment of the present invention.
6 is a diagram illustrating a process of updating a snoop domain of a virtual processor map register by using a residence counter according to another embodiment of the present invention.
7 is a block diagram illustrating an apparatus for controlling cache coherency in a virtualization environment according to an embodiment of the present invention.

Before describing embodiments of the present invention, an overview of related technologies for controlling cache coherence and problem situations when a plurality of virtual machines share a plurality of cores in a virtualized environment in which embodiments of the present invention are implemented I'll do it.

In general, to solve the cache coherence problem, the protocol must maintain consistency between caches so that all local caches always return the latest values. Also, when a cache miss occurs due to a read from the local cache, if the data exists in the local cache of another core, the data is not retrieved from memory such as RAM having a high latency time. It's a good idea to get the data from the local cache on another core. The cache coherence protocol is also used for this process. The two basic methods for cache coherence are known as snoop and directory.

First, the snoop method sends a message requested from a core where a cache miss occurs directly to all cores to solve a cache coherency problem. This snoop method provides fast cache data transfer without any delay, but if the number of cores is large, there is a problem in that the traffic volume increases rapidly because a message must be sent to all cores.

Secondly, the directory method keeps track of which data is loaded in the local cache of a core with a separate directory and sends a message only to the core. For this purpose, each data has a core called a home node, which is different according to a physical address, and the home node maintains and provides information on which core the data is loaded in the local cache. Therefore, when a cache miss occurs, a message is first generated from a core where a cache miss occurs to a home node, and a message is sent only to the corresponding cores based on information on shared cores provided by the home node. Through the above process, the directory method can reduce the traffic, but it requires an additional process to go to the home node and a separate space and process to maintain information about the shared cores, which increases complexity and costs. Done.

Because of this complexity and cost, many systems now use snoop, but the problem can arise when the number of multi-cores increases. The snoop method guarantees a certain level of performance in a multi-core system with four cores. However, if the number of multi-cores increases such as 8, 16, 32, 64, 128, a coherent message is generated. The transmission causes a rapid increase in the traffic volume. Since the increase in the amount of traffic will inevitably lead to deterioration of the system and excessive power consumption, efforts to reduce such unnecessary amount of traffic are required.

Meanwhile, as cloud computing becomes an issue in recent years, by implementing a plurality of virtual machines on one physical machine, virtualization is performed through each virtual machine as if there are separate hardware resources. Virtualization technology is attracting attention. This virtualization technology has the advantages of high resource utilization, high fault tolerance and portability, and excellent manageability.

However, when the virtualization technology is applied to a multi-core system environment, not only a plurality of physical machines (or cores) exist, but also a plurality of virtual machines exist. That is, each virtual machine has a virtual processor (vCPU), and the virtual processors are mapped to a plurality of physical cores to use cores. In this environment, virtual machines use different address memory areas, so communication between virtual machines is unnecessary except for data sharing between virtual machines and virtual machine monitor areas. However, in current multi-core systems, there is no consideration of virtual machines in the communication between cores, so that a considerable amount of unnecessary communication occurs. Therefore, considering a virtualization environment in a multi-core system, a traffic reduction scheme for maintaining cache coherency suitable for this is required.

In the following, embodiments of the present invention will be described in more detail with reference to the related drawings. Like reference numerals in the drawings refer to like elements.

1 is a diagram illustrating a basic idea of the present invention for controlling cache coherency in a virtualization environment in which a plurality of virtual machines share a plurality of cores. The cache coherency control device 100 may include a plurality of cores 50 and a corresponding cache (L2 cache is illustrated), as well as a virtual processor map register 13 and a shadow page table. shadow page table 15).

The virtual processor map register 13 maps and manages a virtual machine and a core allocated thereto. That is, the virtual processor map register 13 preferably manages the virtual machine identifier (VMID) by linking the core list. In FIG. 1, four cores P0, P1, P2, and P4 are mapped to one virtual machine VM1.

The shadow page table 15 maps and manages a state of a page and each page. That is, the shadow page table 15 may be managed by linking a page address paddr and a page status to form a table. In FIG. 1, three different states (VM-private, RW-shared, and RO-shared) are recorded for three pages. Each state information will be described in detail later with reference to FIG. 3.

Virtualization technology provides an independent computing environment for each virtual machine. By default, each virtual machine uses a separate virtual processor and memory area. Each virtual machine's virtual processors (vCPUs) are mapped to different physical cores and run. In this case, if there is no memory sharing between virtual machines, different virtual machines do not need to match the local caches of mapped physical cores, and virtual processors belonging to the same virtual machine are cached only between local caches between mapped cores. You need to be consistent.

Accordingly, embodiments of the present invention described below track the information on which cores the virtual processors of each virtual machine are mapped to and use this information to reduce the amount of communication between caches using this feature of virtualization. Currently, virtual processors belonging to the same virtual machine are sent a message for cache consistency only to the mapped cores. That is, the basic idea of the embodiments of the present invention is to propose a coherence control technique that can reduce the amount of communication that occurs to maintain consistency between cores in consideration of the characteristics of virtualization in a multi-core system having a virtualization environment.

However, there may be a shared area between the virtual machines, and the virtual machine monitor area may be called by all virtual machines so that data may be loaded in the local cache of any physical core, and thus the type may vary depending on the nature of the data. It is necessary to separate the processing of consistency between cache misses for each type. To this end, various embodiments of the present invention store the shared state information for each page in the page table (which may be the shadow page table 15 in FIG. 1). Check if the page is shared by the machine.

More specifically, in order to maintain the above consistency, the data of each virtual machine should be tracked in which local cache currently exists, and information about the tracked cores should be stored in the data structure. . This information is loaded into the virtual processor map register 13 when a virtual machine is newly scheduled on a core. The loaded virtual processor map register 13 is always referenced when a cache miss occurs in the core and a consistency message needs to be sent.

Now, a method of selecting a destination to transmit a consistency message will be described. Consistency messages should only be sent to the cores that hold the data of the virtual machine at the time of the cache miss. To do this, it is necessary to first check whether the page is shared by the virtual machine for the data detected by the cache miss. In FIG. 1, in a multi-core system 100 in which a virtualization environment is implemented, the shared information for each page is recorded in a shadow page table 15 that converts a virtual address into a real physical address, thereby ensuring consistency when a cache miss occurs. Before sending the message, refer to the shared information recorded in the shadow page table 15.

If the current cache missed data is not included in the shared page, the consistency message may be transmitted only to the cores referred to through the virtual processor map register 13. On the other hand, if the data that caused the current cache miss is included in a page shared by another virtual machine or by another virtual machine monitor, then the cores that hold data from other virtual machines are likely to have the same data. Sending a consistency message only to the cores that hold the virtual machine's data is not enough to maintain cache consistency. The method of maintaining consistency in this case will be described in detail later with reference to FIG. 4.

FIG. 2 is a diagram illustrating a process of relocating a virtual machine in a virtual environment according to an embodiment of the present invention, and illustrates a situation in which a virtual processor of the virtual machine is not fixed and moves to increase the utilization of the core. .

In case of a cache miss in FIG. 2, it is necessary to properly add a newly used core to the snoop domain in order to correctly send a consistency message to all cores having data of the virtual machine. If the virtual machine uses a new core that is not in the virtual processor map register, the newly used core must be added to the virtual processor map register before loading data into the new local cache. In addition, each virtual processor map register must be updated by transmitting an update message to the virtual processor map registers of all cores that are loading mapping information of the virtual machine as well as the virtual processor map registers of the newly used cores. The value of this updated virtual processor map register is then stored in a data structure representing the snoop domain of each virtual machine. With this process, you can send a consistency message to all cores that hold the data of the virtual machine, but if virtual processor relocation continues to increase the entries in the virtual processor map registers, the number of virtual processors The number of cores may be included in the snoop domain even if the number of cores is less than or equal to the number of cores.

3 is a flowchart illustrating a method of controlling cache coherency in a virtualization environment according to an embodiment of the present invention, and includes the following steps. In this case, the virtualization environment of FIG. 3 refers to an environment in which a plurality of virtual machines share a plurality of cores.

In step 310, mapping information between virtual processors and cores of the virtual machine and state information indicating whether a page is shared are generated. Here, the mapping information refers to information generated by recording a tracked core by tracking which page unit data used by the virtual processor of the virtual machine exists in the local cache of which cores.

When the generation of the cache miss is detected in step 320, the mapping information and the state information generated in step 310 are used to check whether a page is shared by the virtual machine with respect to the detected data.

In step 330, the virtual processors belonging to the same virtual machine may selectively transmit a consistency message in consideration of the mapped cores according to the sharing test result of step 320. More specifically, the process of transmitting a consistency message is as follows.

First, it detects the occurrence of a cache miss. This sensing process is a configuration that is essentially used in the process of implementing a conventional multi-core system, so a detailed description thereof will be omitted. Next, the state information generated in operation 310 is used to check whether the page is shared by the virtual machine with respect to the data detected by the cache miss. Whether or not to share the page may be performed by referring to page state information recorded in the shadow page table. Based on the inspection result, the virtual machine monitor selects the core mapped to the virtual machine by referring to the mapping information generated in step 310. The selected core may be determined according to the type of page sharing, and more specific types and selection methods will be described later with reference to FIG. 4. Now, the consistency message is sent to the core selected above.

FIG. 4 is a flowchart illustrating the cache coherency control method of FIG. 3 according to an embodiment of the present invention in detail, and illustrates three methods of transmitting coherency messages according to page sharing type.

In step 410, the mapping information and the state information are first generated and stored. That is, mapping information between virtual processors and cores of the virtual machine is generated and stored in the virtual processor map register, and state information indicating whether a page is shared is generated and stored in the shadow page table.

In step 420, it is detected whether a cache miss has occurred. This detection is performed when data access occurs on each core, and the procedure ends if no cache miss occurs. On the other hand, if a cache miss occurs, a process proceeds to step 430 to maintain cache coherency.

In step 430, the page is shared. In this case, the page sharing is determined by referring to the shadow page table and the translation lookaside buffer (TLB) to determine whether the page is shared. To this end, embodiments of the present invention divided the page sharing state into at least three types as follows.

First, the virtual machine private state, which indicates that a page is not shared by multiple virtual machines, is sortable.

Second, a read-write shared state, which indicates that a page is shared by a plurality of virtual machines and that each of the virtual machines can read and write to the shared page, can be classified.

Third, a read-only shared state, which indicates that a page is shared by a plurality of virtual machines and that each of the virtual machines can only read a shared page, is sortable.

In the embodiments of the present invention, a read-write share in which the shared data may exist in the local cache included in the snoop domain of another virtual machine without being in the snoop domain of the non-shared virtual machine and the current virtual machine. And a delimiter (meaning page sharing status information) to distinguish a total of three types, including the type of read-only sharing. In terms of implementation, this state information can be displayed using additional two bits in the shadow page table entry and the entry in the translation index buffer.

If it is determined in step 430 that the page is not a shared page (i.e., it is a virtual machine exclusive state (step 440)), the process proceeds to step 445. In step 445, only the cores included in the read snoop domain are selected by referring to the virtual processor map register, and a consistency message is transmitted only to the selected cores.

On the other hand, if the page is a shared page and the read-write sharing state (step 450) proceeds to step 455. In step 455, a consistency message is broadcast to all cores. For example, suppose a cache miss occurs in the data of a virtual machine monitor, which is a representative read-write shared data. Since the virtual machine monitor area can be called by any virtual machine, the data of the virtual machine monitor can be easily loaded into the local cache of any physical core. Therefore, broadcasting is more effective than tracking which core the page is on.

On the other hand, if the page is a shared page, read-only sharing proceeds to step 465. In step 465, the broadcast may be broadcast, such as read-write sharing, but another approach may be used for more efficient message transmission. Of course, consistency messages for read-only pages can be solved simply by using broadcasting as read-write-enabled pages, but if more pages are shared between virtual machines, this also causes a lot of traffic to match the consistency of each local cache. There is a concern. Accordingly, embodiments of the present invention introduce at least three optimization techniques, each of which is a memory-direct method, an intra-VM method, and a friend virtual machine method. (friend-VM method).

The reason why a different approach is needed for the processing of read-only shared data is as follows. A typical case of a read-only shared page may be a page shared by a content-based sharing technique, which is a technique used for memory saving in a virtualized environment. Such a read-only share is a copy on write when a write operation occurs first, so that a new page is allocated to a new physical address, and there is no need for a separate cache coherency for the existing shared page. Thus, for communication for read-only shared page consistency, you only need to consider read operations, which do not necessarily send a consistency message to all local caches that are loading data, such as write operations. This is because the correct data can be retrieved from memory at any time. If data exists in the local cache of another core, but the consistency message is not sent to the cache, the desired data can be retrieved from memory even if the data cannot be retrieved from the cache. Thus, further improvements are possible to reduce the number of consistency messages. Hereinafter, three improvement methods are proposed to reduce the consistency message of the read-only page.

First, the direct memory method reads cache missed data directly from memory. More specifically, the memory direct method sends a request message to memory unconditionally without generating a coherency message when a cache miss occurs due to a read operation on a read-only page. However, this method can reduce the traffic caused by cache coherence, but if the data exists in the local cache of another core, the data is retrieved from memory even though the data can be retrieved from the cache. There is a risk of loss in terms of. Therefore, the following other methods can be used to get more opportunities to retrieve data from the cache.

Second, the internal virtual machine method requests the data that is cache missed simultaneously to the core and the memory mapped to the virtual machine where the cache miss occurs using the mapping information. In other words, the internal virtual machine method is a method in which the virtual machine that caused the current cache miss simultaneously sends data requests to the cores and the memory recorded in the entry of the virtual processor map register. Using this method, the data traffic due to the coherency message is relatively higher than the direct memory method, but by sending data requests to the cores involved, it increases the probability of getting data from the cache compared to the increasing traffic.

Third, the friend virtual machine method pre-sets virtual machines that are frequently shared by a plurality of virtual machines as a friend virtual machine, and uses the mapping information to map cores and friend virtual machines mapped to the virtual machine where the cache miss occurs. Cache missed data at the same time to the core and memory. In other words, the friend virtual machine method sets virtual machines that share a lot of virtual machines as friend virtual machines, so that the snoop domain of the virtual machine that caused the cache miss when the data request is made, the snoop domain of the friend virtual machine, and the memory. At the same time, it sends data requests. This method increases the traffic by a little more than the methods introduced above, but it can increase the active rate from which data can be retrieved from the cache. To do this, the virtual machine monitor needs to know the degree of sharing between each virtual machine and set up a friend virtual machine according to the degree of sharing. The method of controlling cache coherency by setting a friend virtual machine will be described again with reference to the following example of FIG. 5.

FIG. 5 is a diagram illustrating an example of a method of controlling cache coherency when a cache missed page is in a read-only shared state in a virtualization environment according to an embodiment of the present invention. Each of the virtual machines 510 and 520 is illustrated in FIG. 530 illustrates that four cores have been assigned to the snoop domain.

5 illustrates that the configuration information 550 of the Fred virtual machine is maintained for each of the virtual machines 510, 520, and 530. As shown, virtual machine VM1 shares 40% of pages with virtual machine VM2, so VM1 and VM2 are configured as friend virtual machines by the virtual machine monitor. On the other hand, virtual machine VM1 shares 1% of pages with virtual machine VM3, so it is not configured as a friend virtual machine.

Now assume that virtual machine VM1 caused a cache miss due to a read operation on a read-only shared page on its core P0. In this situation, according to the friend virtual machine method, a coherence message is transmitted to snoop domains of the virtual machine VM1 and the virtual machine VM2, and at the same time, a data request is transmitted to the memory. On the other hand, since the virtual machine VM3 is not a friend virtual machine of the virtual machine VM1, the consistency message is not transmitted.

FIG. 6 is a diagram illustrating a process of updating a snoop domain of the virtual processor map register 13 using the residence counter 17 according to another embodiment of the present invention. The residence counter 17 representing the number of data of the virtual machine loaded in the local cache 55 of the core 50 is calculated and stored.

More specifically, when the data of a virtual machine is newly loaded in the local cache 55 of the core 50 using the residence counter 17 for each core 50, the counter is incremented by 1 and stored. If the replacement of data occurs, decrement the counter by 1 and store it. That is, the number of data currently loaded in the local cache 55 of the core 50 may be indicated through a counter for each virtual machine. Therefore, when the residence counter 17 becomes 0, by removing the core from the snoop domain of the virtual machine, unnecessary cores that are no longer monitored can be removed from the snoop domain. To this end, in the embodiment of the present invention, when the residence counter 17 corresponding to a certain core 50 is 0, the corresponding core is deleted from the snoop domain of the mapping information stored in the virtual processor map register 13.

6 illustrates a case in which the counter value of the virtual machine VM1 becomes 0 while the data of the virtual machine VM1 is replaced in the residence counter 17 corresponding to the core P0 50. The virtual processor map register 13 then removes P0 from the snoop domain of the virtual machine VM1.

According to various embodiments of the present invention described above, a virtualization technology may be multiplied by proposing a technique of selectively transmitting a consistency message to cores by using mapping information between a virtual processor and cores and state information indicating whether a page is shared. Extends to core-based systems, improves system performance by reducing traffic based on coherency messages sent to maintain cache coherency under multi-core-based virtualization environments, and reduces power The consumption can be minimized.

Meanwhile, the present invention can be embodied in computer readable code on a computer readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and also a carrier wave (for example, transmission via the Internet) . In addition, the computer-readable recording medium may be distributed over network-connected computer systems so that computer readable codes can be stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present invention can be easily deduced by programmers skilled in the art to which the present invention belongs.

FIG. 7 is a block diagram illustrating an apparatus 100 for controlling cache coherency in a virtualization environment according to an embodiment of the present invention, and includes a monitoring unit 10, a shared inspection unit 20, and a processing unit 30. In addition, as the present embodiment assumes, a plurality of virtual machines share a plurality of cores 50, and each core 50 has a cache. Each configuration illustrated in FIG. 7 corresponds to each step of the cache coherency control method introduced in detail with reference to FIGS. 3 and 4, and detailed descriptions thereof are omitted here.

The monitoring unit 10 generates mapping information between virtual processors and cores of the virtual machine, stores the mapping information in the virtual processor map register 13, and generates state information indicating whether a page is shared, thereby generating a shadow page table 15. ). Here, the status information means any one of a virtual machine exclusive state, a read-write shared state, and a read-only shared state. In addition, the monitoring unit 10 maps the virtual processors allocated to the plurality of virtual machines and stores the virtual processors in the virtual processor map register 13 as snoop domains.

Meanwhile, the monitoring unit 10 may calculate and store the residence counter 17 indicating the number of data of the virtual machine loaded in the local cache of the corresponding core for each of the plurality of cores, and the residence counter corresponding to a certain core is 0. In this case, the monitoring unit 10 removes the core from the monitoring target by deleting the core from the snoop domain of the mapping information.

When the occurrence of a cache miss is detected, the shared checker 20 uses the mapping information stored in the virtual processor map register 13 and the state information stored in the shadow page table 15 to inform the virtual machine of the data where the cache miss is detected. Check page sharing by The sharing checker 20 checks whether a page is shared by referring to the shadow page table 15 and the translation index buffer 25 when data is accessed.

The processor 30 selectively transmits a coherency message in consideration of the core to which virtual processors belonging to the same virtual machine are mapped according to the check result by the shared checker 20.

The present invention has been described above with reference to various embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

100: cache coherency control unit
10: monitoring unit 13: virtual processor map register
15: Shadow Page Table 17: Residence Counter
20: shared checker 25: conversion index buffer
30: processing unit
50: core 55: cache
510, 520, 530: virtual machine 550: friend machine configuration information

Claims (18)

A method of controlling cache coference in a virtualization environment in which a plurality of virtual machines share a plurality of cores,
Generating mapping information between a virtual processor of the virtual machine and the cores and state information indicating whether a page is shared;
If the occurrence of a cache miss is detected, checking whether the page is shared by the virtual machine with respect to the data where the cache miss is detected, using the generated mapping information and the generated state information; And
And optionally transmitting a consistency message in consideration of the mapped cores of the virtual processors belonging to the same virtual machine according to the check result.
The transmitting of the consistency message may include:
Detecting the occurrence of the cache miss;
Checking whether the page miss is shared by the virtual machine with respect to the data detected by the cache miss using the generated state information;
Selecting, by a virtual machine monitor, a core mapped to the virtual machine based on the generated mapping information based on the inspection result; And
Sending a consistency message to the selected core. delete The method of claim 1,
The status information may include:
A virtual machine private state indicating that the page is not shared by multiple virtual machines,
A read-write shared state indicating that the page is shared by a plurality of virtual machines and each of the virtual machines is capable of reading and writing to a shared page; and
And wherein the page is shared by a plurality of virtual machines and each of the virtual machines is in a read-only shared state indicating that only the read of a shared page is possible. The method of claim 1,
If the check result is a virtual machine exclusive state indicating that the page is not shared by a plurality of virtual machines,
The transmitting of the coherency message may include transmitting a coherency message only to cores included in a snoop domain read by referring to a virtual processor map register storing the mapping information. Way. The method of claim 1,
The check result indicates that the page is shared by a plurality of virtual machines and each of the virtual machines is in a read-write shared state indicating that the shared pages can be read and written to the shared page,
Sending the consistency message is to broadcast a consistency message to all cores. The method of claim 1,
The check result indicates that the page is shared by a plurality of virtual machines and each of the virtual machines is in a read-only shared state indicating that only the shared page can be read;
The transmitting of the coherency message may include at least one of a broadcasting method, a memory-direct method, an intra-VM method, and a friend-VM method. Characterized in that it is carried out. The method according to claim 6,
And the memory direct method reads the cache missed data directly from the memory. The method according to claim 6,
The internal virtual machine method may use the mapping information to request cache missed data simultaneously to a core and a memory mapped to a virtual machine where the cache miss occurs. The method according to claim 6,
The friend virtual machine method,
Pre-set virtual machines that frequently share for each of the plurality of virtual machines as a friend virtual machine,
And using the mapping information to request cache missed data simultaneously to a core mapped to the virtual machine where the cache miss occurred, the core mapped to the set friend virtual machine, and a memory. A method of controlling cache coherency in a virtualization environment in which a plurality of virtual machines share a plurality of cores,
Generating mapping information between the virtual processor and the cores of the virtual machine and storing the mapping information in a virtual processor map register;
Generating state information indicating whether a page is shared and storing the state information in a shadow page table; And
When the occurrence of a cache miss is detected, a consistency message is selected only among cores selected from the plurality of cores by checking whether the cache miss is shared by the virtual machine based on the stored mapping information and the stored state information. Transmitting a step. 11. The method of claim 10,
And calculating and storing a residence counter indicating the number of data of a virtual machine loaded in a local cache of a corresponding core for each of the plurality of cores. The method of claim 11,
And when the residence counter corresponding to a predetermined core is 0, deleting the predetermined core from the snoop domain of the stored mapping information. A computer-readable recording medium having recorded thereon a program for executing the method of any one of claims 1 and 3 to a computer. An apparatus for controlling cache coherency in a virtualization environment in which a plurality of virtual machines share a plurality of cores,
A monitoring unit generating mapping information between the virtual processor and the cores of the virtual machine and storing the mapping information in a virtual processor map register, and generating state information indicating whether a page is shared and storing the state information in a shadow page table;
A sharing checker that checks whether a page is shared by the virtual machine with respect to the data on which the cache miss is detected, using the stored mapping information and the stored state information when a cache miss is detected; And
The processor may include a processor configured to selectively transmit a consistency message in consideration of the mapped cores of the virtual processors belonging to the same virtual machine according to the check result.
Wherein,
Detect the occurrence of the cache miss,
Using the generated state information, checks whether the page is shared by the virtual machine on the detected data of the cache miss;
A virtual machine monitor selects a core mapped to the virtual machine based on the generated mapping information based on the inspection result,
And send a consistency message to the selected core. 15. The method of claim 14,
The state information includes a virtual machine exclusive state indicating that the page is not shared by a plurality of virtual machines, the page is shared by a plurality of virtual machines, and each of the virtual machines can read and write to the shared page. Any one of a read-write shared state indicating a read-write shared state and a read-only shared state indicating that the page is shared by a plurality of virtual machines and each of the virtual machines can only read a shared page,
The monitoring unit maps the page and state information of the page and stores the page in the shadow page table.
And the sharing checker checks whether the page is shared by referring to the shadow page table and translation lookaside buffer (TLB) when data is accessed. An apparatus for controlling cache coherency in a virtualization environment in which a plurality of virtual machines share a plurality of cores,
Generates mapping information between the virtual processor of the virtual machine and the cores and stores the mapping information in a virtual processor map register, generates state information indicating whether a page is shared, and stores the shadow information in a shadow page table. A monitoring unit for calculating and storing a residence counter indicating the number of data of the virtual machine loaded in the local cache; And
When the occurrence of a cache miss is detected, a consistency message is selected only among cores selected from the plurality of cores by checking whether the cache miss is shared by the virtual machine based on the stored mapping information and the stored state information. Apparatus comprising a processing unit for transmitting the. 17. The method of claim 16,
And the monitoring unit maps the virtual processors allocated to the plurality of virtual machines and stores the virtual processors in the virtual processor map register as a snoop domain. 17. The method of claim 16,
And when the residence counter corresponding to a predetermined core is 0, the monitoring unit deletes the predetermined core from the snoop domain of the stored mapping information.

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