CN106405372A - Defect detection method avoiding arc discharge in electron beam scanning process - Google Patents
Defect detection method avoiding arc discharge in electron beam scanning process Download PDFInfo
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- CN106405372A CN106405372A CN201610703019.1A CN201610703019A CN106405372A CN 106405372 A CN106405372 A CN 106405372A CN 201610703019 A CN201610703019 A CN 201610703019A CN 106405372 A CN106405372 A CN 106405372A
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- scanning
- defect
- potential
- crystal column
- column surface
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/305—Contactless testing using electron beams
- G01R31/307—Contactless testing using electron beams of integrated circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Analysing Materials By The Use Of Radiation (AREA)
Abstract
The invention discloses a defect detection method avoiding arc discharge in the electron beam scanning process. The method comprises that a wafer etched with a connecting hole is provided, transmitted to a scanning cavity of an electron beam scanner, and aligned; a defect scanning condition which enables a stable potential at the wafer surface is determined via test; the wafer surface is pre-scanned, the formed stable potential is applied to the wafer surface, the potential of the wafer surface is improved, and the potential difference between wafer surface and an electrode plate of the electron beam scanner is reduced; and a scanning area is selected, and defect detection is carried out under the condition that the stable potential is maintained in the wafer surface. According to the invention, the potential of the wafer surface is improved via pre-scanning, the potential difference between the wafer surface and the electrode plate is reduced, an effect that lots of charges are aggregated at the wafer surface can be alleviated, generation of arc discharge is avoided effectively, a circuit breaker defect of the connecting hole can be detected smoothly, and effective guarantee is provided for online manufacture of semiconductors and improvement of the yield rate.
Description
Technical field
The present invention relates to integrated circuit defect detecting technique field, it is being attached hole etching more particularly, to one kind
The defect inspection method of arc discharge effect is produced during electron beam scanning can be avoided during not enough defects detection.
Background technology
With the development of integrated circuit technology, semiconductor technology also becomes increasingly complex, and increasing new technology is introduced into,
Such as metal barrier layer process.And the introducing of new technology also brings new problem simultaneously, such as metal barrier layer process is related
The not enough defect of connecting hole etching one of be exactly.In order to detect such defect it is necessary to applying electronic beam scanning instrument is swept
Retouch.
Refer to Fig. 1, Fig. 1 is the electric capacity schematic diagram that metal barrier layer process is formed after connecting hole etching.As Fig. 1 institute
Show, when carrying out metal barrier layer process to wafer 10, metal barrier 11 is formed with IMD (inter-level dielectric) 12 and front layer metal 13
Capacity effect, wafer will be made during Defect Scanning, a large amount of electric charge of surface aggregation and produce arc discharge effect.
Arc discharge will lead to wafer to damage.As shown in Fig. 2 a- Fig. 2 b, electric arc in its difference reading beam scanning process
Discharge the defect map produced by destruction to wafer and defect picture.
Refer to Fig. 3, Fig. 3 is to lead to high potential difference schematic diagram between the e-beam scanners of arc discharge and wafer.As Fig. 3
Shown, occur arc discharge the reason be, the electrical potential difference (0- between the battery lead plate 15 of e-beam scanners 14 and wafer 10 surface
U) excessive.By capacitance equation：
Q=UC (1)
It is inferred that under the conditions of larger electric capacity C, voltage U is bigger, then amount of charge Q that crystal column surface can be assembled
More.Once and it exceeds certain level, then the electric arc of crystal column surface will occur arc discharge effect.
If this problem cannot solve, not only can't detect corresponding defect problem, more wafer can be produced and destroy
Effect.But the traditional method of application cannot overcome this problem it is necessary to be innovated.
Content of the invention
It is an object of the invention to the drawbacks described above overcoming prior art to exist, one kind is provided to avoid electron beam scanning process
The middle defect inspection method producing arc discharge, needs after can avoiding connecting hole etching technics to carry out electron beam scanning and produces
Arc discharge effect it is possible to effective detection connecting hole open defect, be that Yield lmproved sets up data target.
For achieving the above object, technical scheme is as follows：
A kind of avoid producing the defect inspection method of arc discharge during electron beam scanning, comprise the following steps：
Step S01：Wafer after connecting hole etching is provided, described wafer is sent to the scanning chamber of e-beam scanners
In body, and it is aligned；
Step S02：It is determined by the Defect Scanning condition making crystal column surface keep during stabilizing potential；
Step S03：Prescan is carried out to crystal column surface, and applies to form stabilizing potential, to lift the potential of crystal column surface,
Reduce the electrical potential difference between crystal column surface and e-beam scanners battery lead plate；
Step S04：Select scanning area, keep carrying out defects detection under stabilizing potential state in crystal column surface.
Preferably, in step S01, described crystal column surface has metal barrier, the layer forming capacity effect from top to bottom
Between medium and front layer metal.
Preferably, in step S02, the described Defect Scanning condition making during crystal column surface holding stabilizing potential is to make wafer table
Face overall image keeps corresponding scanning energy during uniform and stable state.
Preferably, for the wafer of specific products and special process layer, need to test its surface potential respectively when stablizing
Scanning energy.
Preferably, in step S03, during prescan required energy scale be to maintain crystal column surface potential stable, that is, protect
Demonstrate,prove the uniform and stable of crystal column surface image.
Preferably, in step S03, when carrying out prescan, in the state of making wafer keep stabilizing potential, lacked by adjustment
The sunken condition of scanning, to determine optimized Defect Scanning condition.
Preferably, when carrying out prescan, after stabilizing potential is applied to wafer, with described optimized Defect Scanning condition
It is carried out with Defect Scanning, checks that crystal column surface image produces the time point of deviation, and record, stable electricity is kept with test wafer
The time of gesture.
Preferably, in step S03 and step S04, when crystal column surface occurs potential unstable, by prescan step
Repeat so as to reach stable state again.
Preferably, also include step S05：The connecting hole etching defect finding is observed.
From technique scheme as can be seen that the present invention is by being carried crystal column surface potential using prescan mode
Rise, to reduce the electrical potential difference between crystal column surface and scanner battery lead plate during Defect Scanning, thus crystal column surface electric charge can be alleviated
A large amount of effects assembled, are prevented effectively from the generation of arc discharge, and can smoothly detect connecting hole open defect；The present invention passes through should
With the method for on-line monitoring, it is that the solution of defect provides data target, and provides data reference for process window optimization, from
And be that online manufacture of semiconductor provides powerful guarantee with Yield lmproved.
Brief description
Fig. 1 is the electric capacity schematic diagram that metal barrier layer process is formed after connecting hole etching；
Fig. 2 a-2b is defect map and defect produced by destruction to wafer for the arc discharge during electron beam scanning
Picture；
Fig. 3 is to lead to high potential difference schematic diagram between the e-beam scanners of arc discharge and wafer；
Fig. 4 is that a kind of of one embodiment of the invention avoids producing the defects detection side of arc discharge during electron beam scanning
Method flow chart；
Fig. 5 a- Fig. 5 b is that crystal column surface voltage is in undersaturated condition and saturation state schematic diagram；
Fig. 6 a- Fig. 6 b is to avoid the not enough defects detection distribution map of connecting hole etching and defect picture after arc discharge.
Specific embodiment
Invention applies following know-why, that is, by being lifted crystal column surface potential using prescan mode,
To reduce the electrical potential difference between crystal column surface and scanner battery lead plate during Defect Scanning, thus it is a large amount of to alleviate crystal column surface electric charge
The effect assembled, is prevented effectively from the generation of arc discharge, and can smoothly detect connecting hole open defect.
Below in conjunction with the accompanying drawings, the specific embodiment of the present invention is described in further detail.
It should be noted that in following specific embodiments, when describing embodiments of the present invention in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special to the structure in accompanying drawing not according to general scale, and carried out local
Amplify, deformation and simplification are processed, therefore, should avoid being understood in this, as limitation of the invention.
In specific embodiment of the invention below, refer to Fig. 4, Fig. 4 is that one kind of one embodiment of the invention avoids
The defect inspection method flow chart of arc discharge is produced during electron beam scanning.As shown in figure 4, one kind of the present invention avoids electricity
Produce the defect inspection method of arc discharge in beamlet scanning process, comprise the following steps：
Execution step S01：Wafer after connecting hole etching is provided, described wafer is sent to sweeping of e-beam scanners
Retouch in cavity, and be aligned.
Refer to Fig. 1.After connecting hole etching, metal barrier, layer are defined on described crystal column surface from top to bottom
Between medium (IMD) and front layer metal, and form capacity effect.
Execution step S02：It is determined by the Defect Scanning condition making crystal column surface keep during stabilizing potential.
Making crystal column surface keep Defect Scanning condition during stabilizing potential is to make crystal column surface overall image keep uniformly steady
Determine corresponding scanning energy during state.Only crystal column surface overall potential keeps stable, and the image on its surface just can be uniform and stable,
It is that its criterion is so that the overall image of crystal column surface is uniform and stable.
Refer to Fig. 5 a- Fig. 5 b, Fig. 5 a- Fig. 5 b is that crystal column surface voltage is in undersaturated condition and saturation state signal
Figure.As shown in Figure 5 a, for the wafer of a certain specific products or special process layer, when it is applied with the scanning energy of 100ev,
The voltage of crystal column surface is in the undersaturated condition of -10v to -25v, and that is, it is in potential unsure state, then cannot be formed
Uniform and stable overall image.As shown in Figure 5 b, when wafer is applied with the scanning energy of 8ev, the voltage of crystal column surface is in-
The saturation state of 8v, that is, it is in the stable state of potential, can form uniform and stable overall image.
Therefore, when being tested, for the wafer of the specific products being prepared and special process layer, need to survey respectively
Try scanning energy when its surface potential is stablized.Such as the wafer of 55 nanometers of customizing products V1M2ASI, need individually to survey
Try the condition that its surface can keep stabilizing potential, and can not adopt and other product identical scanning energies.
Execution step S03：Prescan is carried out to crystal column surface, and applies to form stabilizing potential, to lift crystal column surface
Potential, reduces the electrical potential difference between crystal column surface and e-beam scanners battery lead plate.
During prescan, the potential that required scanning energy standard is to maintain crystal column surface is stable, that is, ensure crystal column surface shadow
Picture uniform and stable.On this basis, in the state of making wafer keep stabilizing potential, by adjusting Defect Scanning condition, can
To determine optimized Defect Scanning condition.
Then, after stabilizing potential is applied to wafer, with the above-mentioned optimized Defect Scanning condition determined, to wafer
Surface carries out Defect Scanning, checks that crystal column surface image produces the time point of deviation, and records this time point, in order to test crystalline substance
Circle keeps time during stabilizing potential.
Execution step S04：Select scanning area, keep carrying out defects detection under stabilizing potential state in crystal column surface.
Through prescan, determine optimized Defect Scanning condition and count holding stabilizing potential under this condition
When Defect Scanning time after, you can crystal column surface is started with formal Defect Scanning.
When carrying out Defect Scanning, according to aforesaid optimized Defect Scanning condition, select corresponding properly sweeping
Retouch region it is ensured that its surface potential keep stable state under, this scanning area can have abundance time complete defects detection.
During execution step S03 and step S04, when crystal column surface occurs the unstable situation of potential, can lead to
Cross the repeating so as to reach stable state again of prescan step, and execute defect inspection process again.
By Defect Scanning, you can obtain the complete Defect Scanning image (image) of crystal column surface, thus can continue executing with：
Step S05：The connecting hole etching defect finding is observed.
Refer to Fig. 6 a- Fig. 6 b, Fig. 6 a- Fig. 6 b is to avoid the not enough defects detection distribution map of connecting hole etching after arc discharge
With defect picture.As shown in Figure 6 a, its display, for a certain wafer of 55 nanometers of customizing products V1M2ASI, applies above-mentioned side
The not enough Defect Scanning image of connecting hole etching that the crystal column surface that method scanning obtains exists；Fig. 6 b shows crystal column surface one local
The not enough defect picture of connecting hole etching at position.
In sum, the present invention, by being lifted crystal column surface potential using prescan mode, is swept with reducing defect
Electrical potential difference between crystal column surface and scanner battery lead plate when retouching, thus a large amount of effect assembled of crystal column surface electric charge can be alleviated,
It is prevented effectively from the generation of arc discharge, and can smoothly detect connecting hole open defect.The present invention passes through to apply the side of on-line monitoring
Method, is that the solution of defect provides data target, and provides data reference for process window optimization, thus online for semiconductor
Manufacture and provide powerful guarantee with Yield lmproved.
Above-described only the preferred embodiments of the present invention, the patent that described embodiment is simultaneously not used to limit the present invention is protected
The equivalent structure change that shield scope, the specification of therefore every utilization present invention and accompanying drawing content are made, should be included in the same manner
In protection scope of the present invention.
Claims (9)
1. a kind of defect inspection method avoiding producing arc discharge during electron beam scanning is it is characterised in that include following
Step：
Step S01：Wafer after connecting hole etching is provided, described wafer is sent to the scanning cavity of e-beam scanners
In, and be aligned；
Step S02：It is determined by the Defect Scanning condition making crystal column surface keep during stabilizing potential；
Step S03：Prescan is carried out to crystal column surface, and applies to form stabilizing potential, to lift the potential of crystal column surface, reduce
Electrical potential difference between crystal column surface and e-beam scanners battery lead plate；
Step S04：Select scanning area, keep carrying out defects detection under stabilizing potential state in crystal column surface.
2. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, in step S01, described crystal column surface have from top to bottom formed the metal barrier of capacity effect, inter-level dielectric and
Front layer metal.
3. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, in step S02, described make crystal column surface keep stabilizing potential when Defect Scanning condition be make crystal column surface entirety shadow
As keeping corresponding scanning energy during uniform and stable state.
4. according to claim 3 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, for the wafer of specific products and special process layer, need to test scanning energy when its surface potential is stablized respectively
Amount.
5. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, in step S03, during prescan required energy scale be to maintain crystal column surface potential stable, that is, ensure wafer table
Face picture uniform and stable.
6. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, in step S03, when carrying out prescan, in the state of making wafer keep stabilizing potential, by adjusting Defect Scanning bar
Part, to determine optimized Defect Scanning condition.
7. according to claim 7 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, when carrying out prescan, after stabilizing potential is applied to wafer, with described optimized Defect Scanning condition, it is carried out
Defect Scanning, checks that crystal column surface image produces the time point of deviation, and records, with test wafer keep stabilizing potential when
Between.
8. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, in step S03 and step S04, when crystal column surface occur potential unstable when, by prescan step repeat hold
Row is so as to reach stable state again.
9. according to claim 1 avoid producing the defect inspection method of arc discharge during electron beam scanning, it is special
Levy and be, also include step S05：The connecting hole etching defect finding is observed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610703019.1A CN106405372B (en) | 2016-08-22 | 2016-08-22 | Defect detection method for avoiding arc discharge generated in electron beam scanning process |
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| CN201610703019.1A CN106405372B (en) | 2016-08-22 | 2016-08-22 | Defect detection method for avoiding arc discharge generated in electron beam scanning process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111257727A (en) * | 2020-01-17 | 2020-06-09 | 上海华力集成电路制造有限公司 | Device and method for detecting arc discharge in WAT test |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359471A (en) * | 1998-08-17 | 2002-07-17 | 泰格尔公司 | Method and apparatus for minimizing semiconductor wafer arcing semiconductor wafer processing |
| US20090294664A1 (en) * | 2008-05-30 | 2009-12-03 | Hermes Microvision, Inc. | Electron beam apparatus |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN102683173A (en) * | 2012-03-31 | 2012-09-19 | 上海宏力半导体制造有限公司 | Method for reducing wafer arc discharge, and manufacturing method of integrated circuit |
| CN103500720A (en) * | 2013-09-30 | 2014-01-08 | 上海华力微电子有限公司 | Testing structure and testing method for matching degree of electron beam flaw scanner |
| CN104051433A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System And Method For Preventing Etch Arcing During Semiconductor Processing |
| CN104143519A (en) * | 2014-08-01 | 2014-11-12 | 上海华力微电子有限公司 | Product through hole etching defect detection method |
| CN104157590A (en) * | 2014-08-21 | 2014-11-19 | 上海华力微电子有限公司 | Electron beam defect scanning apparatus and method |
| CN105826240A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer arcing defect avoiding method |
-
2016
- 2016-08-22 CN CN201610703019.1A patent/CN106405372B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1359471A (en) * | 1998-08-17 | 2002-07-17 | 泰格尔公司 | Method and apparatus for minimizing semiconductor wafer arcing semiconductor wafer processing |
| US20090294664A1 (en) * | 2008-05-30 | 2009-12-03 | Hermes Microvision, Inc. | Electron beam apparatus |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN102683173A (en) * | 2012-03-31 | 2012-09-19 | 上海宏力半导体制造有限公司 | Method for reducing wafer arc discharge, and manufacturing method of integrated circuit |
| CN104051433A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System And Method For Preventing Etch Arcing During Semiconductor Processing |
| CN103500720A (en) * | 2013-09-30 | 2014-01-08 | 上海华力微电子有限公司 | Testing structure and testing method for matching degree of electron beam flaw scanner |
| CN104143519A (en) * | 2014-08-01 | 2014-11-12 | 上海华力微电子有限公司 | Product through hole etching defect detection method |
| CN104157590A (en) * | 2014-08-21 | 2014-11-19 | 上海华力微电子有限公司 | Electron beam defect scanning apparatus and method |
| CN105826240A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer arcing defect avoiding method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111257727A (en) * | 2020-01-17 | 2020-06-09 | 上海华力集成电路制造有限公司 | Device and method for detecting arc discharge in WAT test |
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