CN106405372B - Defect detection method for avoiding arc discharge generated in electron beam scanning process - Google Patents

Defect detection method for avoiding arc discharge generated in electron beam scanning process Download PDF

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CN106405372B
CN106405372B CN201610703019.1A CN201610703019A CN106405372B CN 106405372 B CN106405372 B CN 106405372B CN 201610703019 A CN201610703019 A CN 201610703019A CN 106405372 B CN106405372 B CN 106405372B
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wafer
scanning
potential
stable
defect
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CN106405372A (en
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范荣伟
陈宏璘
龙吟
顾晓芳
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

The invention discloses a defect detection method for avoiding arc discharge generated in the scanning process of an electron beam, which comprises the following steps: providing a wafer etched through the connecting hole, transferring the wafer into a scanning cavity of an electron beam scanner, and aligning; determining a defect scanning condition when the surface of the wafer is kept at a stable potential through testing; pre-scanning the surface of the wafer, and applying a stable potential to improve the potential of the surface of the wafer and reduce the potential difference between the surface of the wafer and an electrode plate of an electron beam scanner; and selecting a scanning area, and detecting defects under the condition that the surface of the wafer is kept in a stable potential state. The invention improves the surface potential of the wafer by pre-scanning, reduces the potential difference between the surface of the wafer and the electrode plate, can relieve the effect of large-scale accumulation of the surface charge of the wafer, effectively avoids the occurrence of arc discharge, and can smoothly detect the open circuit defect of the connecting hole, thereby providing powerful guarantee for the online manufacture of semiconductors and the improvement of yield.

Description

Defect detection method for avoiding arc discharge generated in electron beam scanning process
Technical Field
The invention relates to the technical field of integrated circuit defect detection, in particular to a defect detection method capable of avoiding an arc discharge effect generated in an electron beam scanning process when defect detection of insufficient etching of a connecting hole is carried out.
Background
As integrated circuit processes have been developed, semiconductor processes have become more complex, and more new processes, such as metal barrier processes, have been introduced. The introduction of new processes also brings new problems, such as insufficient etching of the connection hole related to the metal barrier layer process. In order to detect such defects, an electron beam scanner must be used for scanning.
Referring to fig. 1, fig. 1 is a schematic diagram of a capacitor formed after a metal barrier layer process is performed to etch a connection hole. As shown in fig. 1, when the wafer 10 is subjected to the metal barrier process, the capacitance effect formed by the metal barrier 11, the IMD (interlayer dielectric) 12 and the front metal 13 will cause the wafer to accumulate a large amount of charges on the surface during the defect scanning process to generate the arc discharge effect.
Arcing will cause wafer damage. As shown in fig. 2a-2b, a defect distribution map and a defect picture generated by the damage of the arc discharge to the wafer during the electron beam scanning process are respectively shown.
Referring to FIG. 3, FIG. 3 is a schematic diagram of a high potential difference between an electron beam scanner and a wafer resulting in an arc discharge. As shown in fig. 3, the reason why the arc discharge occurs is that the potential difference (0-U) between the electrode plate 15 of the electron beam scanner 14 and the surface of the wafer 10 is excessively large. From the capacitance equation:
Q＝UC (1)
it can be concluded that the larger the voltage U, the more charge Q the wafer surface can accumulate at a larger capacitance C. And once it exceeds a certain level, arcing effects will occur to the arc at the wafer surface.
If the problem is not solved, the corresponding defect problem can not be detected, and the wafer can be damaged. However, the conventional method cannot overcome this problem, and innovation is required.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a defect detection method for avoiding arc discharge generated in the electron beam scanning process, can avoid the arc discharge effect generated by electron beam scanning after the etching process of the connecting hole, can effectively detect the open circuit defect of the connecting hole, and establishes a data index for improving the yield.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a defect detection method for avoiding arc discharge generated in the scanning process of an electron beam comprises the following steps:
step S01: providing a wafer etched through the connecting hole, transferring the wafer into a scanning cavity of an electron beam scanner, and aligning;
step S02: determining a defect scanning condition when the surface of the wafer is kept at a stable potential through testing;
step S03: pre-scanning the surface of the wafer, and applying a stable potential to improve the potential of the surface of the wafer and reduce the potential difference between the surface of the wafer and an electrode plate of an electron beam scanner;
step S04: and selecting a scanning area, and detecting defects under the condition that the surface of the wafer is kept in a stable potential state.
Preferably, in step S01, the wafer surface has a metal barrier layer, an interlayer dielectric and a front metal layer from top to bottom, which form a capacitance effect.
Preferably, in step S02, the defect scanning condition for maintaining the wafer surface at the stable potential is the corresponding scanning energy for maintaining the whole image of the wafer surface at a uniform and stable state.
Preferably, the scanning energy when the surface potential is stable needs to be tested separately for a specific product and a wafer of a specific process layer.
Preferably, in step S03, the energy level required for pre-scanning is to keep the potential of the wafer surface stable, i.e. to ensure uniform and stable image of the wafer surface.
Preferably, in step S03, the optimum defect scanning condition is determined by adjusting the defect scanning condition while keeping the wafer at a stable potential in the pre-scanning.
Preferably, in the pre-scanning, after the wafer is applied with the stable potential, the wafer is scanned for defects under the optimized defect scanning condition, and a time point of deviation of the image on the surface of the wafer is checked and recorded to test a time when the wafer is maintained with the stable potential.
Preferably, in steps S03 and S04, when the wafer surface is subjected to potential instability, it is brought to a stable state again by the repetition of the pre-scanning step.
Preferably, the method further comprises the step S05: and observing the found etching defects of the connecting hole.
According to the technical scheme, the potential on the surface of the wafer is improved in a pre-scanning mode so as to reduce the potential difference between the surface of the wafer and the electrode plate of the scanner during defect scanning, so that the effect of large accumulation of charges on the surface of the wafer can be relieved, the occurrence of arc discharge can be effectively avoided, and the open circuit defect of the connecting hole can be smoothly detected; by applying the online monitoring method, the invention provides data indexes for solving defects and data reference for optimizing the process window, thereby providing powerful guarantee for the online manufacture and yield improvement of semiconductors.
Drawings
FIG. 1 is a schematic diagram of a capacitor formed after a metal barrier layer process is performed on a connection hole;
FIGS. 2a-2b are a defect map and defect pictures of the damage to a wafer caused by arc discharge during electron beam scanning;
FIG. 3 is a schematic diagram of a high potential difference between an electron beam scanner and a wafer resulting in arcing;
FIG. 4 is a flowchart of a defect detection method for avoiding arcing during scanning of an electron beam according to an embodiment of the present invention;
FIGS. 5 a-5 b are schematic diagrams of wafer surface voltages in an unsaturated state and a saturated state;
FIGS. 6 a-6 b are defect detection distribution diagrams and defect pictures for preventing under-etching of a via hole after arc discharge.
Detailed Description
The invention applies the following technical principle that the potential difference between the wafer surface and the electrode plate of the scanner is reduced when the defect is scanned by adopting the pre-scanning mode to improve the potential of the wafer surface, thereby relieving the effect of large accumulation of the charges on the wafer surface, effectively avoiding the occurrence of arc discharge and smoothly detecting the open circuit defect of the connecting hole.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 4, fig. 4 is a flowchart illustrating a defect detection method for avoiding arc discharge generated during an electron beam scanning process according to an embodiment of the present invention. As shown in fig. 4, a defect detection method for avoiding arc discharge during electron beam scanning according to the present invention includes the following steps:
step S01 is executed: and providing the wafer etched by the connecting hole, and conveying the wafer into a scanning cavity of an electron beam scanner for alignment.
Please refer to fig. 1. After the etching of the connecting hole, a metal barrier layer, an interlayer dielectric (IMD) and a front metal layer are formed on the surface of the wafer from top to bottom, and a capacitance effect is formed.
Step S02 is executed: the defect scanning conditions were determined by testing while maintaining the wafer surface at a stable potential.
The condition for scanning the defect while keeping the wafer surface at a stable potential is the corresponding scanning energy while keeping the whole image of the wafer surface at a uniform and stable state. The image of the surface of the wafer is uniform and stable only if the whole potential of the surface of the wafer is kept stable, namely the judgment standard is to ensure that the whole image of the surface of the wafer is uniform and stable.
Referring to fig. 5 a-5 b, fig. 5 a-5 b are schematic diagrams illustrating the wafer surface voltage in an unsaturated state and a saturated state. As shown in fig. 5a, when 100ev of scanning energy is applied to a wafer of a specific product or a specific process layer, the voltage of the wafer surface is in an unsaturated state of-10 v to-25 v, i.e. it is in a state of unstable potential, and a uniform and stable overall image cannot be formed. When 8ev of scanning energy is applied to the wafer, the voltage at the wafer surface is in a-8 v saturation state, i.e., it is in a potential stable state, and a uniform and stable overall image can be formed, as shown in fig. 5 b.
Therefore, when testing, the scanning energy for testing the surface potential of the wafer with stable surface potential is required for the prepared specific product and the specific process layer. Such as a wafer for a 55 nm customized product V1M2ASI, requires testing the conditions for maintaining a stable potential on its surface alone, and not using the same scanning energy as other products.
Step S03 is executed: the wafer surface is prescanning, and a stable potential is applied to improve the potential of the wafer surface and reduce the potential difference between the wafer surface and the electrode plate of the electron beam scanner.
During pre-scanning, the required scanning energy standard is to keep the potential of the wafer surface stable, i.e. to ensure the uniformity and stability of the wafer surface image. On this basis, by adjusting the defect scanning conditions in a state where the wafer is kept at a stable potential, the optimum defect scanning conditions can be determined.
And then, after the stable potential is applied to the wafer, carrying out defect scanning on the surface of the wafer according to the determined optimized defect scanning condition, checking the time point of deviation of the image on the surface of the wafer, and recording the time point for testing the time when the wafer keeps the stable potential.
Step S04 is executed: and selecting a scanning area, and detecting defects under the condition that the surface of the wafer is kept in a stable potential state.
After pre-scanning, determining the optimized defect scanning condition and counting the defect scanning time when the stable potential is kept under the condition, the formal defect scanning on the surface of the wafer can be started.
When the defect scanning is carried out, according to the optimized defect scanning condition, a corresponding proper scanning area is selected, and the scanning area can have enough time to finish the defect detection under the condition that the surface potential is kept in a stable state.
In the process of performing steps S03 and S04, when a situation in which the potential of the wafer surface is unstable occurs, it may be brought to a stable state again by the repeated execution of the pre-scanning step, and the defect detecting process may be performed again.
Through the defect scanning, a complete defect scanning image (image) of the wafer surface can be obtained, so that the following steps can be continuously executed:
step S05: and observing the found etching defects of the connecting hole.
Referring to fig. 6 a-6 b, fig. 6 a-6 b are defect detection distribution diagrams and defect pictures for preventing insufficient etching of the connection hole after arc discharge. As shown in fig. 6a, it shows a scanning image of insufficient etching defects of a connection hole on the wafer surface obtained by scanning the wafer surface according to the above method for a certain wafer of a 55 nm customized product V1M2 ASI; FIG. 6b is a diagram showing an under-etched defect of a via at a local location on a wafer surface.
In summary, the invention employs the pre-scanning method to raise the potential on the wafer surface to reduce the potential difference between the wafer surface and the scanner electrode plate during defect scanning, so as to alleviate the effect of large amount of accumulated charges on the wafer surface, effectively avoid the occurrence of arc discharge, and smoothly detect the open circuit defect of the connecting hole. By applying the online monitoring method, the invention provides data indexes for solving defects and data reference for optimizing the process window, thereby providing powerful guarantee for the online manufacture and yield improvement of semiconductors.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (7)

1. A defect detection method for avoiding arc discharge generated in the scanning process of an electron beam is characterized by comprising the following steps:
step S01: providing a wafer etched through the connecting hole, transferring the wafer into a scanning cavity of an electron beam scanner, and aligning;
step S02: determining a defect scanning condition when the surface of the wafer is kept at a stable potential through testing; the defect scanning condition when the wafer surface is kept at the stable potential is corresponding scanning energy when the whole image of the wafer surface is kept in a uniform and stable state;
step S03: pre-scanning the surface of the wafer, and applying a stable potential to improve the potential of the surface of the wafer and reduce the potential difference between the surface of the wafer and an electrode plate of an electron beam scanner; the energy standard required during pre-scanning is to keep the potential of the wafer surface stable, i.e. to ensure the uniformity and stability of the wafer surface image;
step S04: and selecting a scanning area, and detecting defects under the condition that the surface of the wafer is kept in a stable potential state.
2. The method as claimed in claim 1, wherein in step S01, the wafer has a metal barrier layer, an interlayer dielectric and a front metal layer from top to bottom for forming capacitance effect.
3. The method as claimed in claim 1, wherein the scanning energy is measured when the surface potential of the wafer is stable for a specific product and a specific process layer.
4. The method as claimed in claim 1, wherein the step S03 is performed by adjusting the defect scanning condition while maintaining the wafer at a stable potential to determine the optimized defect scanning condition.
5. The method as claimed in claim 4, wherein the pre-scan is performed by applying a stable potential to the wafer, scanning the wafer with the optimized defect scanning condition, checking the time point of the deviation of the image on the wafer surface, and recording to test the time of the wafer maintaining the stable potential.
6. The method as claimed in claim 1, wherein the step S03 and the step S04 are repeated to reach the stable state again when the wafer surface is unstable in potential.
7. The method for detecting defects to avoid arcing during electron beam scanning as claimed in claim 1, further comprising step S05: and observing the found etching defects of the connecting hole.
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CN104143519A (en) * 2014-08-01 2014-11-12 上海华力微电子有限公司 Product through hole etching defect detection method

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US7759653B2 (en) * 2008-05-30 2010-07-20 Hermes Microvision, Inc. Electron beam apparatus
CN102376600B (en) * 2010-08-24 2013-05-29 中芯国际集成电路制造(上海)有限公司 Evaluation method for failure of contact hole
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