CN106385254A - Frequency band scanning circuit for LC type phase locked loop - Google Patents
Frequency band scanning circuit for LC type phase locked loop Download PDFInfo
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- CN106385254A CN106385254A CN201610893528.5A CN201610893528A CN106385254A CN 106385254 A CN106385254 A CN 106385254A CN 201610893528 A CN201610893528 A CN 201610893528A CN 106385254 A CN106385254 A CN 106385254A
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- 238000010586 diagram Methods 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention relates to a frequency band scanning circuit for an LC type phase locked loop. The frequency band scanning circuit comprises a comparator, an AND gate circuit, an N-bit counter, and a D trigger. The input end of the comparator is connected to lower limit voltage VL and a determination voltage Vdect. The input end of the AND gate circuit is connected to a counting circuit Count_clk and the output end of the comparator. The D input end of the D trigger is connected to the output end O of the N-bit counter. The input end C of the N-bit counter is connected to a counting period Count_period. The C input end of the D trigger is connected to the output end of the AND gate circuit. The Q output end of the D trigger is connected to a VCOsel selection signal and is used for controlling a voltage controlled oscillator array SW<0:2<N>-1>. According to the frequency band scanning circuit, the determining voltage is judged by using the feedback circuit of the phase-locked loop, the configuration circuit and process are simplified greatly, the automatic frequency band scanning and selection of the voltage controlled oscillator array can be realized, and the frequency band scanning circuit can be widely applied to the design of the LC type phase-locked loop.
Description
Technical field
The invention belongs to microelectronics technology, it is related to a kind of LC type phaselocked loop, especially one kind is used for LC type phaselocked loop
Frequency scan circuit.
Background technology
Phaselocked loop is applied to the fields such as Digital Frequency Synthesize, wireless receiving and dispatching as a common part, and its performance is good and bad straight
Connect the work quality affecting whole Circuits System.Under the conditions of high band operation, LC type phaselocked loop is due to its superior mutually making an uproar property
The features such as energy, frequency stability, is used widely in wireless communication field.Because the LC oscillator frequency range of single size is narrower,
Need in actual applications for different size LC to be combined as array application, to meet broadband requirement.Conventional method is according to input ginseng
Examine frequency, frequency calculates output frequency, choose LC array in conjunction with operating temperature, calculating process and configuration are cumbersome.
Content of the invention
The technical problem to be solved in the present invention is to overcome existing defect, provides a kind of frequency band for LC type phaselocked loop to sweep
Scanning circuit, this frequency scan circuit utilize phaselocked loop backfeed loop judge judge voltage, greatly simplifie configuration circuit and
Process, can achieve the automatic frequency scan for voltage controlled oscillator array and selection, can be widely applied to LC type Design of PLL.
In order to solve above-mentioned technical problem, the invention provides following technical scheme：
A kind of frequency scan circuit for LC type phaselocked loop of the present invention, this frequency scan circuit includes comparator and door
Circuit, N-bit counter and d type flip flop, the input of comparator connects lower voltage limit VLWith judgement voltage Vdect, with gate circuit
Input connection count clock Count_clk and the output end of comparator, the D input of d type flip flop connects the defeated of N-bit counter
Go out and hold O, the input C connection count cycle Count_period of N-bit counter, the C input of d type flip flop connects and gate circuit
Output end, the Q output of d type flip flop connects VCOselSelection signal, for controlling voltage controlled oscillator array switch SW<0:2N-
1>.
Further, frequency scan circuit input judges voltage VdectExported by charge pump, its magnitude of voltage is equal to voltage-controlled electricity
Pressure Vctrl；Frequency scan circuit output VCOselSelection signal selects array to voltage controlled oscillator.
Further, the counting cycle Count_period and counting clock Count_clk of frequency scan circuit exists and divides
Frequency relation, Count_period=Count_clk/2N.
Further, the N value of the N-bit counter of frequency scan circuit is determined by the voltage controlled oscillator quantity of required control
Fixed, 2NMore than voltage controlled oscillator quantity.
Further, frequency scan circuit output 2NPosition control code.
Beneficial effects of the present invention：
The frequency scan circuit of the present invention make use of the backfeed loop of phaselocked loop, judges to judge voltage VdectWhether in optimum
In control area, obtain voltage controlled oscillator antenna array control selection signal VCOsel；As judgement voltage VdectExceed optimum control range
Lower voltage limit VLWhen, output valve VCO of the current d type flip flop of lockablesel.Circuit of the present invention can achieve for voltage controlled oscillator VCO
The automatic frequency scan of array and selection, compared with the circuit that circuit selects frequency band with conventional manual, simplify frequency band calculating process
And circuit configuration, can be widely applied in LC type phase-locked loop circuit.
Brief description
Fig. 1 is the LC type principle of phase lock loop figure of the present invention；
Fig. 2 is the frequency scan circuit diagram of the present invention；
Fig. 3 is the frequency scan circuit diagram of the N=5 of one embodiment of the invention；
Fig. 4 is the LC array circuit figure of one embodiment of the invention.
Specific embodiment
Below in conjunction with accompanying drawing and instantiation, the specific embodiment of the present invention is illustrated.
Fig. 1 is LC type phase-locked loop circuit schematic diagram applied in being embodied as the present invention, and this circuit is typical LC
Type phaselocked loop, voltage controlled oscillator 2 is using 32 sections of array structures as shown in figure 4, voltage controlled oscillator 2 exports divides through N1 frequency divider 3, N2
Frequency device 4 is supplied to frequency discrimination phase-sensitive detector PFD 5 and input reference clock Refclk frequency discrimination phase-detecting after dividing twice.Frequency scan circuit
1 is in the middle of charge pump 6 and voltage controlled oscillator 2, by comparing to determine voltage VdectObtain 32 selection signals VCOsetFor controlling
Voltage controlled oscillator 2 array switch SW processed<0:31>.
In this example, the lower limit of the voltage-controlled voltage range of the optimum of voltage controlled oscillator 2 is VL, higher limit is VH, in this voltage
In the range of in array all of LC voltage controlled oscillator 2 there is optimized linear convergent rate, this design can ensure whole VCO
Device 2 has continuous frequency band output.
Fig. 2 is frequency scan circuit diagram, and this frequency scan circuit 1 includes comparator CMP111 and gate circuit AND 12, N
The input of digit counter N_Counter 13 and d type flip flop DFF 14, comparator CMP111 connects lower voltage limit VLAnd judgement
Voltage Vdect, output end with the input connection count clock Count_clk and comparator CMP111 of gate circuit AND 12, D
The D input of trigger DFF 14 connects output end O of N-bit counter N_Counter 13, N-bit counter N_Counter 13
Input C connection count cycle Count_period, the C input of d type flip flop DFF 14 connects with gate circuit AND's 12
Output end, the Q output of d type flip flop DFF 14 connects VCOselSelection signal, for controlling voltage controlled oscillator 2 array switch SW<
0:2N-1>.
Fig. 3 is a kind of exemplary embodiments of Fig. 2, and this circuit includes comparator 11 and gate circuit 12, N-bit counter 13 and D
Trigger 14, because LC array is 32 sections, so the N value of N-bit counter 13 is 5 in this example.Wherein, count cycle Count_
There is frequency dividing relation, Count_period=31.25KHz, 32ms, Count_clk=in period and counting clock Count_clk
1MHz, 1000ns, N-bit counter 13 is added up with the clock interval of 32ms, and (this time interval design load should be much larger than phaselocked loop lock
Fix time).
Fig. 4 is LC array circuit figure, terminates because frequency scan starts paramount frequency band BAND-31 from low-frequency band BAND-0,
Voltage-controlled voltage V before the selection of this circuit non-lockingctrlWith judgement voltage VdectIt is toward high, V from lowdectLess than optimum voltage-controlled voltage
Lower limit VLWhen, the 1MHz clock transfer of Count_clk can be provided clock to the C input of d type flip flop 14 with gate circuit 12
Extension signal, now d type flip flop 14 will be with 32ms for the VCO of cycle output Continuous accumulationselSelection signal, from 00000 to 11111；
Work as VCOselWhen the LC segment frequence that selection signal is selected meets ongoing frequency setting, by feeding back the voltage-controlled voltage V obtainingctrl
With judgement voltage VdectWill be greater than optimum voltage-controlled voltage lower limit value VL, now will export permanent 0 with gate circuit 12, now d type flip flop 14
Current VCO can be lockedselSelection signal, and it is allocated to array switch signal SW<0:31>.So far, this LC type phaselocked loop completes
Automatically frequency scan and selection.
Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as protecting model to the present invention
The restriction enclosed, for those skilled in the art, without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, and these improve and modification also falls in the range of the claims in the present invention protection.
Claims (5)
1. a kind of frequency scan circuit for LC type phaselocked loop it is characterised in that：Described frequency scan circuit (1) includes comparing
Device (11) and gate circuit (12), N-bit counter (13) and d type flip flop (14), the input of comparator (11) connects lower voltage limit
VLWith judgement voltage Vdect, with the input connection count clock Count_clk of gate circuit (12) and the output of comparator (11)
End, the D input of d type flip flop (14) connects output end O of N-bit counter (13), and the input C of N-bit counter (13) connects
Counting cycle Count_period, the C input of d type flip flop (14) connects the output end with gate circuit (12), d type flip flop (14)
Q output connect VCOselSelection signal, for controlling voltage controlled oscillator (2) array switch SW<0:2N-1>.
2. the frequency scan circuit for LC type phaselocked loop according to claim 1 it is characterised in that：Described frequency scan
Circuit (1) input judges voltage VdectExported by charge pump (6), its magnitude of voltage is equal to voltage-controlled voltage Vctrl；Frequency scan circuit
(1) export VCOselSelection signal selects array to voltage controlled oscillator (2).
3. the frequency scan circuit for LC type phaselocked loop according to claim 1 it is characterised in that：Described frequency scan
There is frequency dividing relation, Count_period=in the counting cycle Count_period and counting clock Count_clk of circuit (1)
Count_clk/2N.
4. the frequency scan circuit for LC type phaselocked loop according to claim 1 it is characterised in that：Described frequency scan
The N value of the N-bit counter (13) of circuit (1) is determined by voltage controlled oscillator (2) quantity of required control, 2NMore than VCO
Device (2) quantity.
5. the frequency scan circuit for LC type phaselocked loop according to claim 1 it is characterised in that：Described frequency scan
Circuit (1) output 2NPosition control code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610893528.5A CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610893528.5A CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106385254A true CN106385254A (en) | 2017-02-08 |
| CN106385254B CN106385254B (en) | 2019-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610893528.5A Active CN106385254B (en) | 2016-10-13 | 2016-10-13 | A kind of frequency scan circuit for LC type phaselocked loop |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158208A (en) * | 2011-04-02 | 2011-08-17 | 东南大学 | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit |
| US8358159B1 (en) * | 2011-03-10 | 2013-01-22 | Applied Micro Circuits Corporation | Adaptive phase-locked loop (PLL) multi-band calibration |
| CN103346787A (en) * | 2013-06-14 | 2013-10-09 | 浙江大学 | Phase-locked loop frequency synthesizer structure with automatic frequency correction |
-
2016
- 2016-10-13 CN CN201610893528.5A patent/CN106385254B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8358159B1 (en) * | 2011-03-10 | 2013-01-22 | Applied Micro Circuits Corporation | Adaptive phase-locked loop (PLL) multi-band calibration |
| CN102158208A (en) * | 2011-04-02 | 2011-08-17 | 东南大学 | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit |
| CN103346787A (en) * | 2013-06-14 | 2013-10-09 | 浙江大学 | Phase-locked loop frequency synthesizer structure with automatic frequency correction |
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| Publication number | Publication date |
|---|---|
| CN106385254B (en) | 2019-04-19 |
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