CN106374944A - CMOS (Complementary Metal Oxide Semiconductor) fully-integrated Ka-band full-radio-frequency structure phased array anti-interference receiving front end - Google Patents
CMOS (Complementary Metal Oxide Semiconductor) fully-integrated Ka-band full-radio-frequency structure phased array anti-interference receiving front end Download PDFInfo
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- CN106374944A CN106374944A CN201610754921.6A CN201610754921A CN106374944A CN 106374944 A CN106374944 A CN 106374944A CN 201610754921 A CN201610754921 A CN 201610754921A CN 106374944 A CN106374944 A CN 106374944A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
- H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
- H04B1/126—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means having multiple inputs, e.g. auxiliary antenna for receiving interfering signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
- H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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Abstract
The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) fully-integrated Ka-band full-radio-frequency structure phased array anti-interference receiving front end. The receiving front end comprises four paths of receiving front-end links and a signal synthesizer, wherein the four paths of receiving front-end links have the same structures and independent phase shift; each receiving front-end link comprises a low noise amplifier (LAN), a passive shifter (PS) and a gain compensation amplifier (AMP); and through the four paths of receiving front-end links capable of independently adjusting a signal phase, an oriented signal can be obtained at an output port of the signal synthesizer, and side-lobe signal is attenuated, so that relatively high anti-interference performance is provided. A gain of a whole receiving front end in a frequency band of 26 to 29GHz is 20dB; noise is lower than 6dB; input and output reflection coefficients are lower than 10dB; and the power consumption is 120mW at the voltage of 1.8V.
Description
Technical field
The invention belongs to the technical field of millimetre integrated circuit design, especially a kind of complementary metal oxide semiconductors (CMOS)
Have and have the full radio-frequency structure phased array receiving front-end of capacity of resisting disturbance cmos fully integrated ka wave band, can be used for high-speed radiocommunication system
In system.
Background technology
In recent years, with broadband services, the rapid growth of especially broadband multimedia services demand, using l wave band (1 ~
2ghz) or the wireless communication system of the low band such as wave band c (4 ~ 8ghz) has tended to saturation, and can not fit compared with low band
Answer two-forty, the communication system in big broadband, it is wireless that this just forces Chinese scholars to turn to research millimeter wave band (30 ~ 300ghz)
Communication.
Millimeter wave band has extremely wide bandwidth, and this is in nervous undoubtedly very attractive today of frequency resource.Identical
Under antenna size, the wave beam of millimeter wave is more much narrower than the wave beam of microwave, therefore has higher resolution.Compare with microwave, in the least
The size of metric wave components and parts is much smaller, and therefore millimeter-wave systems are easier miniaturization.And compared with laser, the propagation of millimeter wave
The impact of climate much smaller it is believed that having round-the-clock characteristic.Therefore, millimetre-wave attenuator becomes radio communication in recent years
Study hotspot.
Ka wave band millimeter wave (26.5 ~ 40ghz) radio communication because the advantage of its own become Future broadband satellite communication and
The development trend of the 5th generation (5g) mobile communication, its advantage has: bandwidth abundant (theoretical bandwidth has 3.5ghz), message capacity be big,
Realize that wave beam is narrow, equipment volume is little and strong antijamming capability etc..Therefore, ka band satellite communication system can be led to for high speed satellite
Letter, gigabit level broadband digital transmission, high-definition television (hdtv), SNG (sng), vsat business, directly
There is provided a kind of brand-new means to the new business such as family's (dth) business and personal satellite communication.Samsung and Korea S's sk telecommunication are before this
Complete the test of the 5th generation (5g) mobile communication system based on 28ghz millimeter wave, but this is from 5g mobile communication technology just
Formula commercialization still suffers from distance.So, research ka wave band has great importance.However, the maximum shortcoming of ka wave band is link
Rainfall loss is more serious, and maximum, up to 30db, impacts to the amplitude-phase of transmission signal, in turn results in communications system transmission
Quality and the deterioration of systematic function.Just because of this kind of attenuation characteristic of ka wave band, cause available signal and be easily disturbed
The interference of signal, and cause communication system failure.This is and right just to requiring receiver in communication system to have capacity of resisting disturbance
The synthesis of tiny signal it is also proposed requirement.
And ka wave band millimeter wave receiving front-end is as the important module of receiver in ka wave band millimeter wave wireless communication system,
The quality of its performance is very big to the performance impact of whole communication system.In recent years in the iii-v such as gaas, inp race quasiconductor work
The existing successful case of ka-band receiving front-end phased array that skill and bicmos technique are realized, but it is relatively costly, power consumption is larger.
By contrast, have the advantages that under cmos technique that integrated level is high, cost and low in energy consumption, it is possible to achieve front ends of millimeter waves circuit and base
Integrated with circuit, the soc system integration has significant advantage.But cmos technique substrate loss is big, this gives high-quality-factor
The design of passive device brings challenges；And under cmos technique active device cut-off frequency relatively low, real based on cmos technique
Existing high performance ka wave band millimeter wave receiving front-end phased array is a big difficult point all the time.
Content of the invention
It is an object of the invention to provide a kind of cmos fully integrated ka wave band full radio-frequency structure phased array anti-interference reception front end.
The object of the present invention is achieved like this:
A kind of cmos fully integrated ka wave band full radio-frequency structure phased array anti-interference reception front end, feature is: described anti-interference reception
Front end includes:
The identical receiving front-end link with independent phase shift of four line structures, its each link includes:
Low-noise amplifier lan, using two-stage cascode structure, input connects input signal, and outfan connected with passive moves
The input of phase device ps；
Passive phase shifter ps, using four bit architecture, by control bit signal phase can be carried out 22.5 degree, 45 degree, 67.5 degree,
90 degree, 112.5 degree, 135 degree, 157.5 degree, 180 degree, 202.5 degree, 225 degree, 247.5 degree, 270 degree, 292.5 degree, 315 degree or
337.5 degree of phase shift, the input of output termination gain compensation amplifier amp；
Gain compensation amplifier amp, using one-level cascode structure；Output connects an input of signal synthesizer；
One signal synthesizer, using quarter-wave coplanar waveguide transmission line structure, by three structure identical two-way
Synthesizer forms No. four synthesizers.
Described low-noise amplifier lna particularly as follows:
First inductance lg1 two ends connect rfin end and the grid of a nmos pipe m1 respectively；The ls two ends of the second inductance connect respectively
The source electrode of one nmos pipe m1 and ground connection gnd；The drain electrode of the first nmos pipe m1 connects the source electrode of the 2nd nmos pipe m2；2nd nmos pipe m2
Grid meet power supply vdd；The two ends of the 3rd inductance ld1 meet drain electrode and the power supply vdd of the 2nd nmos pipe m2 respectively；First mim electricity
The two ends holding c1 connect the drain electrode of the 2nd nmos pipe m2 and the grid of the 3rd nmos pipe m3 respectively；The source ground of the 3rd nmos pipe m3
Gnd, drain electrode connects the source electrode of the 4th nmos pipe m4；The two ends of the 4th inductance ld2 connect drain electrode and the power supply of the 4th nmos pipe m4 respectively
vdd；The two ends of the 2nd mim electric capacity c2 connect the drain electrode of the 4th nmos pipe m4 and the leakage of the 6th nmos pipe m6 in passive phase shifter respectively
Pole；The two ends of first resistor r1 meet grid and the offset side vg1 of a nmos pipe m1 respectively；The two ends of second resistance r2 connect respectively
The grid of the 3rd nmos pipe m3 and offset side vg2.
Described passive phase shifter ps is by the first phase-shifting unit 180-bit unit of independent control, the second phase-shifting unit 90-
Bit, the 3rd phase-shifting unit 45-bit and the 4th phase-shifting unit 22.5-bit composition, particularly as follows:
In first phase-shifting unit 180-bit, the two ends of the 5th inductance l1 connect source electrode and the drain electrode of the 6th nmos pipe m6 respectively；6th
The grid of nmos pipe m6 meets control bit vc1；The two ends of the 3rd electric capacity c3 meet drain electrode and the 5th nmos of the 6th nmos pipe m6 respectively
The drain electrode of pipe m5；The two ends of the 4th electric capacity c4 connect the source electrode of the 6th nmos pipe m6 and the drain electrode of the 5th nmos pipe m5 respectively；6th
The two ends of inductance l2 connect source electrode and the drain electrode of the 5th nmos pipe m5 respectively；The grid of the 5th nmos pipe m5 connects control bit vc2, source electrode
Ground connection gnd；The two ends of the 7th inductance l3 connect source electrode and the drain electrode of the 8th nmos pipe m8 respectively；The drain electrode of the 8th nmos pipe m8 connects
The source electrode of six nmos pipe m6, grid meet control bit vc1；The two ends of the 5th electric capacity c5 connect the drain electrode and of the 8th nmos pipe m8 respectively
The drain electrode of seven nmos pipe m7；The two ends of the 6th electric capacity c6 connect the source electrode of the 8th nmos pipe m8 and the leakage of the 7th nmos pipe m7 respectively
Pole；The two ends of the 8th inductance l4 connect source electrode and the drain electrode of the 7th nmos pipe m7 respectively；The grid of the 7th nmos pipe m7 connects control bit
Vc2, source ground gnd；
In second phase-shifting unit 90-bit, the two ends of the 9th inductance l5 connect the tenth nmos pipe m10 source electrode and drain electrode respectively；Tenth
The grid of nmos pipe m10 meets control bit vc3, drain electrode connects the source electrode of the 8th nmos pipe m8 in the first phase-shifting unit 180-bit；7th
The two ends of electric capacity c7 connect the drain electrode of the tenth nmos pipe m10 and the drain electrode of the 9th nmos pipe m9 respectively；The two ends of the 8th electric capacity c8 are divided
Do not connect the source electrode of the tenth nmos pipe m10 and the drain electrode of the 9th nmos pipe m9；The two ends of the tenth inductance l6 connect the 9th nmos pipe respectively
The source electrode of m9 and drain electrode；The grid of the 9th nmos pipe m9 meets control bit vc4, source ground gnd；
In 3rd phase-shifting unit 45-bit, the two ends of the 11st inductance l7 connect the 12nd nmos pipe m12 source electrode and drain electrode respectively；The
The grid of 12 nmos pipe m12 meets control bit vc5, drain electrode connects the source electrode of the tenth nmos pipe m10 in the second phase-shifting unit 90-bit；
The two ends of the 9th electric capacity c9 connect the drain electrode of the 12nd nmos pipe m12 and the drain electrode of the 11st nmos pipe m11 respectively；Tenth electric capacity
The two ends of c10 connect the source electrode of the 12nd nmos pipe m12 and the drain electrode of the 11st nmos pipe m11 respectively；The two of 12nd inductance l8
End connects source electrode and the drain electrode of the 11st nmos pipe m11 respectively；The grid of the 11st nmos pipe m11 connects control bit vc6, source ground
gnd；
In 4th phase-shifting unit 22.5-bit, the two ends of the 13rd inductance l9 connect the 14th nmos pipe m14 source electrode and drain electrode respectively；
The grid of the 14th nmos pipe m14 meets control bit vc7, drain electrode meets the 12nd nmos pipe m12 in the 3rd phase-shifting unit 45-bit
Source electrode；The two ends of the 11st electric capacity c11 connect the drain electrode of the 14th nmos pipe m14 and the drain electrode of the 13rd nmos pipe m13 respectively；The
The two ends of 12 electric capacity c12 connect the source electrode of the 14th nmos pipe m14 and the drain electrode of the 13rd nmos pipe m13 respectively；14th electricity
The two ends of sense l10 connect source electrode and the drain electrode of the 13rd nmos pipe m13 respectively；The grid of the 13rd nmos pipe m13 connects control bit
Vc8, source electrode meet gnd.
Described gain compensation amplifier amp particularly as follows:
The two ends of the 13rd electric capacity c13 connect the source electrode of the 14th nmos pipe m14 and in the 4th phase-shifting unit 22.5-bit respectively
One end of 15 inductance lg2, the grid of another termination the 15th nmos pipe m15 of the 15th inductance lg2；15th nmos pipe
The source ground gnd of m15, drain electrode connect the source electrode of the 16th nmos pipe m16；The grid of the 16th nmos pipe m16 meets power supply vdd；
The two ends of the 16th inductance ld3 connect power supply vdd and the drain electrode of the 16th nmos pipe m16 respectively；The two ends of the 14th electric capacity c14 are divided
Do not meet drain electrode and the outfan rfout of the 16th nmos pipe m16；The two ends of 3rd resistor r3 meet the 15th nmos pipe m15 respectively
Grid and offset side vg3.
It is an advantage of the current invention that:
(1), noise coefficient is low
Post-simulation shows, the noise coefficient of the fully integrated ka wave band full radio-frequency structure phased array receiving front-end of the present invention is whole
Both less than 6db in 26-29ghz frequency range, at center bin 27.5ghz frequency, noise coefficient is 4.9db.
(2), strong antijamming capability
The receiver front end structure of the present invention employs the system structure of four tunnel synthesis, because the signal that four tunnels receive has fixation
Phase contrast, freely adjust the phase place of receipt signal by the single receiver in each road, can in signal synthesizer output port
To receive the signal of a certain specific direction, compacting side-lobe signal so that the receiver system of the present invention have preferably anti-interference
Ability.
(3), low in energy consumption
Employ passive phase shifter due in the receiver front end circuit of the present invention, this circuit structure does not consume extra work(
Rate is so that the power consumption of whole circuit structure is relatively low.
(4), save chip area, low cost
All circuit structures due to the present invention employ single-ended design, are compared to difference channel, and whole chip area reduces
Nearly half, and then reduce production cost.
Brief description
Fig. 1 is present configuration block diagram；
Fig. 2 is low-noise amplifier lna circuit diagram of the present invention；
Fig. 3 is passive phase shifter ps circuit diagram of the present invention；
Fig. 4 is gain compensation amplifier amp circuit diagram of the present invention；
Fig. 5 is embodiment of the present invention structured flowchart；
Fig. 6 is embodiment of the present invention receipt signal schematic diagram；
Fig. 7 is the normalized signal intensity map obtained by 45 degree of direction signals of reception.
Specific embodiment
Describe the present invention below in conjunction with drawings and Examples.
Embodiment
Refering to Fig. 5, the present embodiment is by receiving front-end link e1, e2, e3, e4 of four tunnel independences and four road signal synthesizer e5
Composition, wherein, the circuit structure of four road receiving front-end links is identical.The input of its four roads receiving front-end link is respectively
Rfin1, rfin2, rfin3, rfin4, the output of each road is respectively rfout1, rfout2, rfout3, rfout4, by signal
Synthesizer final synthesized output signal rfout_tol.Each receiving front-end chain route low-noise amplifier lan, and 4 bit passives move
Phase device ps and gain compensation amplifier apm composition, circuit structure adopts single-end circuit to design.
Refering to Fig. 2, the low-noise amplifier lan of the present embodiment, using the two-stage single-ended cascode structure of lc load, lead to
Cross and mosfet emulation is obtained by its best static working-point is: the direct current biasing of the amplifier first order is set to a 0.15ma/ μm of left side
The right side, with noise-reduction coefficient；The direct current biasing of the second level is 0.3ma/ μm about, to increase the gain of amplifier.First order electricity
In road, the first inductance lg1 and the second inductance ls constitutes the input matching network of amplifier.4th inductance ld2 and the second electric capacity c2 makees
Impedance matching network for circuit output end.
Refering to Fig. 3, the 4 bit passive phase shifter ps of the present embodiment, using lc switching mode structure, wherein 4 bits are respectively
For 22.5 degree, 45 degree, 90 degree and 180 degree, by the combination in any of this 4 bit phase, input signal can be carried out from 0 degree
To between 360 degree with the phase shift of 22.5 degree of 16 states for an interval, the out of phase signal of each link can be entered
Row " shaping " is so that it has been phase place identical state that the signal of each link reaches during synthesizer.Wherein, control bit vc1 and
The current potential of vc2 is contrary.The current potential of control bit vc3 and vc4 is contrary.The current potential of control bit vc5 and vc6 is contrary.Control bit vc7 and
The current potential of vc8 is contrary.In the phase shifter of 4 bits, the phase-shift circuit of wherein 180 degree is by two 90 degree of phase-shift circuit series connection
Form.
Refering to Fig. 4, the gain compensation amplifier apm of the present embodiment, using single-ended cascode structure, its effect is to be directed to
Prime passive phase shifter ps compensates to signal gain to the insertion loss that link brings, and its method for designing is similar to low noise
Amplifier lan, by the comparison summary to mosfet simulation result, has drawn the best static working-point of mosfet, maximum ft
Residing electric current density is about 0.3ma/ μm, and to determine the optimal width value of the 15th nmos pipe and the 16th nmos pipe with this.
16th inductance and the 14th electric capacity are as the output matching network of circuit.
When one frequency of reception is the plane wave signal of 30ghz ka wave band it is assumed that the normal on signal corrugated becomes 45 with antenna
Degree angle (θ in), the distance between neighboring receivers antenna is d, as shown in Figure 6 it is known that signal reach neighboring receivers antenna it
Between range difference (d*sin (θ in)) determine the phase contrast of two-way receiver receipt signal.Spacing when neighboring receivers antenna
From d for 5mm when, using first via receiver phase for 0 degree as reference, then second road signal phase place falls behind 127 degree, the 3rd tunnel phase
Position falls behind 255 degree, and the 4th tunnel phase place falls behind 382 degree.The first via phase shifter control bit vc11, vc13, vc15, vc17 are connect high electricity
Position, vc12, vc14, vc16, vc18 connect electronegative potential to keep signal to be input to rfout1 output phase invariant from rfin1；By
Two tunnel phase shifter control bit vc22, vc25, vc26, vc27 connect high potential, and vc21, vc23, vc24, vc28 connect electronegative potential, produce
One close to 233 degree phase shift so that signal phase from rfin2 be input to rfout2 output after be consistent with the first via；Will
3rd tunnel phase shifter control bit vc31, vc33, vc34, vc38 connects high potential, and vc32, vc35, vc36, vc37 connect electronegative potential, produces
Raw one close to 105 degree of phase shift so that signal phase is input to after rfout3 exports from rfin3 is consistent with the first via；
4th tunnel phase shifter control bit vc42, vc44, vc46, vc48 is connect high potential, vc41, vc43, vc45, vc47 connect electronegative potential,
Produce one close to 338 degree phase shift so that signal phase from rfin4 be input to rfout4 output after with the first via holding one
Cause.Eventually through synthesizer synthesis, obtain the curve of a spacing wave phase place and normalized gain in rfout_tol port,
As shown in fig. 7, the corresponding signal gain highest in 45 degree of angles, and the side-lobe signal of other phase places obtains effective attenuation.
The all device sizes of the present embodiment refer to table 1.
Claims (4)
1. a kind of cmos fully integrated ka wave band full radio-frequency structure phased array anti-interference reception front end is it is characterised in that described anti-dry
Disturb receiving front-end to include:
The identical receiving front-end link with independent phase shift of four line structures, its each link includes:
Low-noise amplifier lan, using two-stage cascode structure, input connects input signal, and outfan connected with passive moves
The input of phase device ps；
Passive phase shifter ps, using four bit architecture, by control bit signal phase can be carried out 22.5 degree, 45 degree, 67.5 degree,
90 degree, 112.5 degree, 135 degree, 157.5 degree, 180 degree, 202.5 degree, 225 degree, 247.5 degree, 270 degree, 292.5 degree, 315 degree or
337.5 degree of phase shift, the import and export end of output termination gain compensation amplifier amp；
Gain compensation amplifier amp, using one-level cascode structure；Output connects an input of signal synthesizer；
One signal synthesizer, using quarter-wave coplanar waveguide transmission line structure, by three structure identical two-way
Synthesizer forms No. four synthesizers.
2. receiving front-end according to claim 1 it is characterised in that described low-noise amplifier lna particularly as follows:
First inductance lg1 two ends connect rfin end and the grid of a nmos pipe m1 respectively；The ls two ends of the second inductance connect respectively
The source electrode of one nmos pipe m1 and ground connection gnd；The drain electrode of the first nmos pipe m1 connects the source electrode of the 2nd nmos pipe m2；2nd nmos pipe m2
Grid meet power supply vdd；The two ends of the 3rd inductance ld1 meet drain electrode and the power supply vdd of the 2nd nmos pipe m2 respectively；First mim electricity
The two ends holding c1 connect the drain electrode of the 2nd nmos pipe m2 and the grid of the 3rd nmos pipe m3 respectively；The source ground of the 3rd nmos pipe m3
Gnd, drain electrode connects the source electrode of the 4th nmos pipe m4；The two ends of the 4th inductance ld2 connect drain electrode and the power supply of the 4th nmos pipe m4 respectively
vdd；The two ends of the 2nd mim electric capacity c2 connect the drain electrode of the 4th nmos pipe m4 and the leakage of the 6th nmos pipe m6 in passive phase shifter respectively
Pole；The two ends of first resistor r1 connect grid and the biasing vg1 end of a nmos pipe m1 respectively；The two ends of second resistance r2 connect respectively
The grid of the 3rd nmos pipe m3 and biasing vg2 end.
3. receiving front-end according to claim 1 is it is characterised in that described passive phase shifter ps is by the first of independent control
Phase-shifting unit 180-bit unit, the second phase-shifting unit 90-bit, the 3rd phase-shifting unit 45-bit and the 4th phase-shifting unit 22.5-
Bit forms, particularly as follows:
In first phase-shifting unit 180-bit, the two ends of the 5th inductance l1 connect source electrode and the drain electrode of the 6th nmos pipe m6 respectively；6th
The grid of nmos pipe m6 meets control bit vc1；The two ends of the 3rd electric capacity c3 meet drain electrode and the 5th nmos of the 6th nmos pipe m6 respectively
The drain electrode of pipe m5；The two ends of the 4th electric capacity c4 connect the source electrode of the 6th nmos pipe m6 and the drain electrode of the 5th nmos pipe m5 respectively；6th
The two ends of inductance l2 connect source electrode and the drain electrode of the 5th nmos pipe m5 respectively；The grid of the 5th nmos pipe m5 connects control bit vc2, source electrode
Ground connection gnd；The two ends of the 7th inductance l3 connect source electrode and the drain electrode of the 8th nmos pipe m8 respectively；The drain electrode of the 8th nmos pipe m8 connects
The source electrode of six nmos pipe m6, grid meet control bit vc1；The two ends of the 5th electric capacity c5 connect the drain electrode and of the 8th nmos pipe m8 respectively
The drain electrode of seven nmos pipe m7；The two ends of the 6th electric capacity c6 connect the source electrode of the 8th nmos pipe m8 and the leakage of the 7th nmos pipe m7 respectively
Pole；The two ends of the 8th inductance l4 connect source electrode and the drain electrode of the 7th nmos pipe m7 respectively；The grid of the 7th nmos pipe m7 connects control bit
Vc2, source ground gnd；
In second phase-shifting unit 90-bit, the two ends of the 9th inductance l5 connect the tenth nmos pipe m10 source electrode and drain electrode respectively；Tenth
The grid of nmos pipe m10 meets control bit vc3, drain electrode connects the source electrode of the 8th nmos pipe m8 in the first phase-shifting unit 180-bit；7th
The two ends of electric capacity c7 connect the drain electrode of the tenth nmos pipe m10 and the drain electrode of the 9th nmos pipe m9 respectively；The two ends of the 8th electric capacity c8 are divided
Do not connect the source electrode of the tenth nmos pipe m10 and the drain electrode of the 9th nmos pipe m9；The two ends of the tenth inductance l6 connect the 9th nmos pipe respectively
The source electrode of m9 and drain electrode；The grid of the 9th nmos pipe m9 meets control bit vc4, source ground gnd；
In 3rd phase-shifting unit 45-bit, the two ends of the 11st inductance l7 connect the 12nd nmos pipe m12 source electrode and drain electrode respectively；The
The grid of 12 nmos pipe m12 meets control bit vc5, drain electrode connects the source electrode of the tenth nmos pipe m10 in the second phase-shifting unit 90-bit；
The two ends of the 9th electric capacity c9 connect the drain electrode of the 12nd nmos pipe m12 and the drain electrode of the 11st nmos pipe m11 respectively；Tenth electric capacity
The two ends of c10 connect the source electrode of the 12nd nmos pipe m12 and the drain electrode of the 11st nmos pipe m11 respectively；The two of 12nd inductance l8
End connects source electrode and the drain electrode of the 11st nmos pipe m11 respectively；The grid of the 11st nmos pipe m11 connects control bit vc6, source ground
gnd；
In 4th phase-shifting unit 22.5-bit, the two ends of the 13rd inductance l9 connect the 14th nmos pipe m14 source electrode and drain electrode respectively；
The grid of the 14th nmos pipe m14 meets control bit vc7, drain electrode meets the 12nd nmos pipe m12 in the 3rd phase-shifting unit 45-bit
Source electrode；The two ends of the 11st electric capacity c11 connect the drain electrode of the 14th nmos pipe m14 and the drain electrode of the 13rd nmos pipe m13 respectively；The
The two ends of 12 electric capacity c12 connect the source electrode of the 14th nmos pipe m14 and the drain electrode of the 13rd nmos pipe m13 respectively；14th electricity
The two ends of sense l10 connect source electrode and the drain electrode of the 13rd nmos pipe m13 respectively；The grid of the 13rd nmos pipe m13 connects control bit
Vc8, source electrode meet gnd.
4. receiving front-end according to claim 1 it is characterised in that described gain compensation amplifier amp particularly as follows:
The two ends of the 13rd electric capacity c13 connect the source electrode of the 14th nmos pipe m14 and in the 4th phase-shifting unit 22.5-bit respectively
One end of 15 inductance lg2, the grid of another termination the 15th nmos pipe m15 of the 15th inductance lg2；15th nmos pipe
The source ground gnd of m15, drain electrode connect the source electrode of the 16th nmos pipe m16；The grid of the 16th nmos pipe m16 meets power supply vdd；
The two ends of the 16th inductance ld3 connect power supply vdd end and the drain electrode of the 16th nmos pipe m16 respectively；The two ends of the 14th electric capacity c14
Meet drain electrode and the outfan rfout of the 16th nmos pipe m16 respectively；The two ends of 3rd resistor r3 connect the 15th nmos pipe respectively
The grid of m15 and offset side vg3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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