CN106373605A - Novel anti single-node SRAM unit with reinforced SEU - Google Patents
Novel anti single-node SRAM unit with reinforced SEU Download PDFInfo
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- CN106373605A CN106373605A CN201610841737.5A CN201610841737A CN106373605A CN 106373605 A CN106373605 A CN 106373605A CN 201610841737 A CN201610841737 A CN 201610841737A CN 106373605 A CN106373605 A CN 106373605A
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- pipe
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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- Static Random-Access Memory (AREA)
Abstract
The invention discloses a novel anti single-node SRAM unit with reinforced SEU. The novel anti single-node SRAM unit with reinforced SEU is characterized by comprising a novel storage unit, a SRAM read-write circuit (1), a SRAM read-write circuit (2). The novel storage unit comprises a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit, wherein an output end of the first subcircuit is connected to an input end of the second/fourth subcircuit, the output end of the second subcircuit is connected to the input end of the first/third subcircuit, the output end of the third subcircuit is connected to the input end of the second/fourth, and the output end of the fourth subcircuit is connected to the input end of the first/third subcircuit. The novel storage unit also comprises a node A, a node B, a node C and a node D. In the circuit of the novel anti single-node SRAM unit with reinforced SEU, the strength of anti SEU reinforcing is increased through crystal valve redundancy. When overturns from 0 to 1 and 1 to 0 occur in any storage node, the novel anti single-node SRAM unit with reinforced SEU have correct logic outputs.
Description
Technical field
The present invention relates to the new sram unit that a kind of anti-single node seu is reinforced, belong to the upset of sram unit anti-single particle
(seu) reinforcement technique field.
Background technology
In universe, there are multiple radiation environments, the impact to chip for the different radiation environments is also different.Setting
During meter aviation special chip, space radiation environment is chip open-assembly time most environment, is also will in chip manufacturing proces
The subject matter considering.The main component of space radiation environment is solar rayss, milky way ray and earth magnetism capture area.
There are many high energy charged particles in space radiation environment.When these high energy particles incide chip, often
Electron hole pair can be formed in chip internal sensitizing range it is possible to there is see phenomenon (single particle effect), and then initiating system event
Barrier, loses and disabler including information.Energy size according to charged particle and the position hitting device, in memory element
Position is it may happen that overturn, also known as single-particle inversion (seu).Although seu is a kind of " soft error ", memory element is only caused to patrol
Volume state change, does not damage circuit itself, be but the dangerous effect that may meet with of spacecraft electronic devices and components of in-orbit period it
One.
With the development continuing forward of modern science and technology, radiation is got over for the impact of microelectronic circuit (particularly memorizer)
Come bigger, cause the probability of single particle effect also just bigger, and often cause new single particle effect.Moreover,
Present commercial product it is also proposed higher requirement to this, nowadays also stricter to this requirement in the occasion of high reliability.
Content of the invention
It is an object of the invention to, overcome the defect that prior art exists, solve standard storage structure and be easy to produce seu mistake
Problem, proposes the new sram unit that a kind of anti-single node seu is reinforced by mistake.
The present invention adopt the following technical scheme that a kind of new sram unit that anti-single node seu reinforces it is characterised in that
Including new memory element, sram read/write circuit (1), sram read/write circuit (2), described new memory element includes first
Road, the second branch road, the 3rd branch road, the 4th branch road, described tie point, described second branch road, described 3rd branch road, the described 4th
One end of branch road connects tie point power supply, the second branch road power supply, the 3rd branch road power supply, the 4th branch road power supply respectively, and described first
Branch road, described second branch road, described 3rd branch road, the other end of described 4th branch road are all grounded simultaneously, described tie point
Outfan is connected with the input of described the second/tetra- branch road, the outfan of described second branch road and described the first/tri- branch road
Input is connected, and the outfan of described 3rd branch road is connected with the input of described the second/tetra- branch road, described 4th branch road
Outfan be connected with the input of described the first/tri- branch road, described new memory element also includes node a, node b, section
Point c, node d, described sram read/write circuit (1) is connected with described node b, described node c respectively, described sram read/write circuit
(2) it is connected with described node a, node d respectively；
Described tie point includes pmos pipe p1, pmos pipe p2, nmos pipe n1, nmos pipe n2, the source of described pmos pipe p1
Pole is connected with described tie point power supply, and the source electrode of described pmos pipe p2 is connected with the drain electrode of described pmos pipe p1, described
The drain electrode of pmos pipe p2 is connected with the drain electrode of described nmos pipe n1, the leakage of the source electrode of described nmos pipe n1 and described nmos pipe n2
Pole is connected, the source ground of described nmos pipe n2；
Described second branch road includes pmos pipe p3, pmos pipe p4, nmos pipe n3, nmos pipe n4, the source of described pmos pipe p3
Pole is connected with described second branch road power supply, and the source electrode of described pmos pipe p4 is connected with the drain electrode of described pmos pipe p3, described
The drain electrode of pmos pipe p4 is connected with the drain electrode of described nmos pipe n3, the leakage of the source electrode of described nmos pipe n3 and described nmos pipe n4
Pole is connected, the source ground of described nmos pipe n4；
Described 3rd branch road includes pmos pipe p5, pmos pipe p6, nmos pipe n5, nmos pipe n6, the source of described pmos pipe p5
Pole is connected with described 3rd branch road power supply, and the source electrode of described pmos pipe p6 is connected with the drain electrode of described pmos pipe p5, described
The drain electrode of pmos pipe p6 is connected with the drain electrode of described nmos pipe n5, the leakage of the source electrode of described nmos pipe n5 and described nmos pipe n6
Pole is connected, the source ground of described nmos pipe n6；
Described 4th branch road includes pmos pipe p7, pmos pipe p8, nmos pipe n7, nmos pipe n8, the source of described pmos pipe p7
Pole is connected with described 4th branch road power supply, and the source electrode of described pmos pipe p8 is connected with the drain electrode of described pmos pipe p7, described
The drain electrode of pmos pipe p8 is connected with the drain electrode of described nmos pipe n7, the leakage of the source electrode of described nmos pipe n7 and described nmos pipe n8
Pole is connected, the source ground of described nmos pipe n8；
Connecting node a of described p2 pipe drain electrode and the drain electrode of n1 pipe connects the grid of described pmos pipe p4, described nmos respectively
The grid of pipe n3, the grid of described pmos pipe p7, the grid of described nmos pipe n8, the connection of described p4 pipe drain electrode and the drain electrode of n3 pipe
Node b connects the grid of described pmos pipe p6, the grid of described nmos pipe n5 respectively, the grid of described pmos pipe p1, described
The grid of nmos pipe n2, connecting node c of described p6 pipe drain electrode and the drain electrode of n5 pipe connects the grid of described pmos pipe p8, institute respectively
State the grid of nmos pipe n7, the grid of described pmos pipe p3, the grid of described nmos pipe n4, described p8 pipe drain electrode and the drain electrode of n7 pipe
Connecting node d connect described pmos pipe p2 grid, the grid of described nmos pipe n1, the grid of described pmos pipe p5, institute respectively
State the grid of nmos pipe n6.
Described sram read/write circuit (1) includes nmos pipe n9, nmos pipe n10, wordline wl, bit line bl, anti-phase bit line blb,
The grid of described nmos pipe n9, the grid of described nmos pipe n10 are connected with described wordline wl respectively, the source of described nmos pipe n9
Pole is connected with described anti-phase bit line blb, and the source electrode of described nmos pipe n10 is connected with described bit line bl, described nmos pipe n9
Drain electrode be connected with described node b, the drain electrode of described nmos pipe n10 is connected with described node c.
Described sram read/write circuit (2) includes nmos pipe n11, nmos pipe n12, wordline wl, bit line bl, anti-phase bit line blb,
The grid of described nmos pipe n11, the grid of described nmos pipe n12 are connected with described wordline wl respectively, described nmos pipe n1's
Source electrode is connected with described anti-phase bit line blb, and the source electrode of described nmos pipe n12 is connected with described bit line bl, described nmos pipe
The drain electrode of n1 is connected with described node d, and the drain electrode of described nmos pipe n12 is connected with described node a.
The beneficial effect that the present invention is reached: increase the intensity that anti-seu reinforces in the circuit of the present invention by single node,
When any of which memory node occurs 0 to 1 and 1 to 0 upset, this structure all can have correct logic output.
Brief description
Fig. 1 is the circuit connection diagram of the new memory element of the present invention.
Fig. 2 is the circuit connection diagram of the sram read/write circuit of the present invention.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
Fig. 1 is the circuit connection diagram of the new memory element of the present invention.The present invention proposes a kind of anti-single node seu and adds
Solid new sram unit it is characterised in that include new memory element, sram read/write circuit (1), sram read/write circuit (2),
Described new memory element includes tie point, the second branch road, the 3rd branch road, the 4th branch road, described tie point, described second
Branch road, described 3rd branch road, one end of described 4th branch road connect tie point power supply, the second branch road power supply, the 3rd branch road respectively
Power supply, the 4th branch road power supply, described tie point, described second branch road, described 3rd branch road, the other end of described 4th branch road
All it is grounded, the outfan of described tie point is connected with the input of described the second/tetra- branch road simultaneously, described second branch road
Outfan is connected with the input of described the first/tri- branch road, the outfan of described 3rd branch road and described the second/tetra- branch road
Input is connected, and the outfan of described 4th branch road is connected with the input of described the first/tri- branch road, described new storage
Unit also includes node a, node b, node c, node d, described sram read/write circuit (1) respectively with described node b, described node
C is connected, and described sram read/write circuit (2) is connected with described node a, node d respectively；
Described tie point includes pmos pipe p1, pmos pipe p2, nmos pipe n1, nmos pipe n2, the source of described pmos pipe p1
Pole is connected with described tie point power supply, and the source electrode of described pmos pipe p2 is connected with the drain electrode of described pmos pipe p1, described
The drain electrode of pmos pipe p2 is connected with the drain electrode of described nmos pipe n1, the leakage of the source electrode of described nmos pipe n1 and described nmos pipe n2
Pole is connected, the source ground of described nmos pipe n2；
Described second branch road includes pmos pipe p3, pmos pipe p4, nmos pipe n3, nmos pipe n4, the source of described pmos pipe p3
Pole is connected with described second branch road power supply, and the source electrode of described pmos pipe p4 is connected with the drain electrode of described pmos pipe p3, described
The drain electrode of pmos pipe p4 is connected with the drain electrode of described nmos pipe n3, the leakage of the source electrode of described nmos pipe n3 and described nmos pipe n4
Pole is connected, the source ground of described nmos pipe n4；
Described 3rd branch road includes pmos pipe p5, pmos pipe p6, nmos pipe n5, nmos pipe n6, the source of described pmos pipe p5
Pole is connected with described 3rd branch road power supply, and the source electrode of described pmos pipe p6 is connected with the drain electrode of described pmos pipe p5, described
The drain electrode of pmos pipe p6 is connected with the drain electrode of described nmos pipe n5, the leakage of the source electrode of described nmos pipe n5 and described nmos pipe n6
Pole is connected, the source ground of described nmos pipe n6；
Described 4th branch road includes pmos pipe p7, pmos pipe p8, nmos pipe n7, nmos pipe n8, the source of described pmos pipe p7
Pole is connected with described 4th branch road power supply, and the source electrode of described pmos pipe p8 is connected with the drain electrode of described pmos pipe p7, described
The drain electrode of pmos pipe p8 is connected with the drain electrode of described nmos pipe n7, the leakage of the source electrode of described nmos pipe n7 and described nmos pipe n8
Pole is connected, the source ground of described nmos pipe n8；
Connecting node a of described p2 pipe drain electrode and the drain electrode of n1 pipe connects the grid of described pmos pipe p4, described nmos respectively
The grid of pipe n3, the grid of described pmos pipe p7, the grid of described nmos pipe n8, the connection of described p4 pipe drain electrode and the drain electrode of n3 pipe
Node b connects the grid of described pmos pipe p6, the grid of described nmos pipe n5 respectively, the grid of described pmos pipe p1, described
The grid of nmos pipe n2, connecting node c of described p6 pipe drain electrode and the drain electrode of n5 pipe connects the grid of described pmos pipe p8, institute respectively
State the grid of nmos pipe n7, the grid of described pmos pipe p3, the grid of described nmos pipe n4, described p8 pipe drain electrode and the drain electrode of n7 pipe
Connecting node d connect described pmos pipe p2 grid, the grid of described nmos pipe n1, the grid of described pmos pipe p5, institute respectively
State the grid of nmos pipe n6；
Fig. 2 is the circuit connection diagram of the sram read/write circuit of the present invention.Described sram read/write circuit (1) includes nmos
Pipe n9, nmos pipe n10, wordline wl, bit line bl, anti-phase bit line blb, the grid of described nmos pipe n9, the grid of described nmos pipe n10
Pole is connected with described wordline wl respectively, and the source electrode of described nmos pipe n9 is connected with described anti-phase bit line blb, described nmos pipe
The source electrode of n10 is connected with described bit line bl, and the drain electrode of described nmos pipe n9 is connected with described node b, described nmos pipe n10
Drain electrode be connected with described node c.Described sram read/write circuit (2) includes nmos pipe n11, nmos pipe n12, wordline wl, position
Line bl, anti-phase bit line blb, the grid of described nmos pipe n11, the grid of described nmos pipe n12 are connected with described wordline wl respectively
Connect, the source electrode of described nmos pipe n1 is connected with described anti-phase bit line blb, the source electrode of described nmos pipe n12 and described bit line bl
It is connected, the drain electrode of described nmos pipe n1 is connected with described node d, the drain electrode of described nmos pipe n12 is connected with described node a
Connect.
The operation principle of the present invention: because this sram unit be symmetrical structure, below only assume that node a, node b, node c,
When the state of node d is 1010, various situations are described respectively:
First, node a catches a packet, produce the set pulse of 1- > 0: for the second branch road, p3 ends, and n4 turns on, due to a
Overturn as 0 from 1, lead to p4 to turn on, n3 ends, but node b is in high-impedance state floating and can't overturn, similarly to the 4th
Road, p8 ends, and n7 turns on, and because a overturns as 0 from 1, leads to p7 to turn on, n8 ends, and also floating can't overturn, therefore node d
Entirely new memory element will not overturn.
Second, node b catches a packet, produce the set pulse of 0- > 1: for the 3rd branch road, p5 turns on, and n6 ends, due to b
Overturn as 1 from 0, lead to p6 to end, n5 turns on, but node c is in high-impedance state floating and can't overturn, similarly to first
Road, p2 turns on, and n1 ends, and because b overturns as 1 from 0, leads to p1 to end, n2 turns on, and also floating can't overturn, therefore node a
Entirely new memory element will not overturn.
Third, node c catches a packet, produce the set pulse of 1- > 0: for the 4th branch road, p7 ends, and n8 turns on, due to c
Overturn as 0 from 1, lead to p8 to turn on, n7 ends, but node d is in high-impedance state floating and can't overturn, similarly to second
Road, p4 ends, and n3 turns on, and because c overturns as 0 from 1, leads to p3 to turn on, n4 ends, and also floating can't overturn, therefore node b
Entirely new memory element will not overturn.
Fourth, node d catches a packet, produce the set pulse of 0- > 1: for tie point, p1 turns on, and n2 ends, due to d
Overturn as 1 from 0, lead to p2 to end, n1 turns on, but node a is in high-impedance state floating and can't overturn, similarly to the 3rd
Road, p6 turns on, and n5 ends, and because d overturns as 1 from 0, leads to p5 to end, n6 turns on, and also floating can't overturn, therefore node c
Entirely new memory element will not overturn.
In entirely new memory element, whichsoever node is subject to the strike of high energy particle to be overturn, all without
Cause other node to overturn it is ensured that the reliability of new memory element, that is, ensure that the stability of new memory element not
As for upset it is achieved that the anti-seu of new memory element reinforces.
When operation is read and write to new sram unit, sram read/write circuit (1) and sram read/write circuit (2)
Form closed-loop path, that is, nmos pipe n9, n11 and nmos pipe n10, n12 is both turned on；When reading, anti-phase bit line blb and bit line bl
All it is precharged to high level, wl effectively starts to read data, and bit line bl can read 0 by pulldown network electric discharge, anti-phase bit line blb
Precharge level is maintained to can read 1 by upper pull-up network or high resistant floating state, similarly, bit line bl is floated by upper pull-up network or high resistant
Empty state maintains precharge level to can read 1, and anti-phase bit line blb can read 0 by pulldown network electric discharge；When carrying out write operation,
To the node that will write 1, bl=1, blb=0；To the node that will write 0, bl=0, blb=1.
The above is only the preferred embodiment of the present invention it is noted that ordinary skill people for the art
For member, on the premise of without departing from the technology of the present invention principle, some improvement can also be made and deform, these improve and deform
Also should be regarded as protection scope of the present invention.
Claims (3)
1. the new sram unit that a kind of anti-single node seu is reinforced is it is characterised in that include new memory element, sram read-write
Circuit (1), sram read/write circuit (2), described new memory element include tie point, the second branch road, the 3rd branch road, the 4th
Road, described tie point, described second branch road, described 3rd branch road, one end of described 4th branch road connect tie point electricity respectively
Source, the second branch road power supply, the 3rd branch road power supply, the 4th branch road power supply, described tie point, described second branch road, the described 3rd
Branch road, the other end of described 4th branch road are all grounded simultaneously, and the outfan of described tie point is defeated with described the second/tetra- branch road
Enter end to be connected, the outfan of described second branch road is connected with the input of described the first/tri- branch road, described 3rd branch road
Outfan is connected with the input of described the second/tetra- branch road, the outfan of described 4th branch road and described the first/tri- branch road
Input is connected, and described new memory element also includes node a, node b, node c, node d, described sram read/write circuit
(1) be connected with described node b, described node c respectively, described sram read/write circuit (2) respectively with described node a, node d phase
Connect；
Described tie point includes pmos pipe p1, pmos pipe p2, nmos pipe n1, nmos pipe n2, the source electrode of described pmos pipe p1 with
Described tie point power supply is connected, and the source electrode of described pmos pipe p2 is connected with the drain electrode of described pmos pipe p1, described pmos
The drain electrode of pipe p2 is connected with the drain electrode of described nmos pipe n1, the drain electrode phase of the source electrode of described nmos pipe n1 and described nmos pipe n2
Connect, the source ground of described nmos pipe n2；
Described second branch road includes pmos pipe p3, pmos pipe p4, nmos pipe n3, nmos pipe n4, the source electrode of described pmos pipe p3 with
Described second branch road power supply is connected, and the source electrode of described pmos pipe p4 is connected with the drain electrode of described pmos pipe p3, described pmos
The drain electrode of pipe p4 is connected with the drain electrode of described nmos pipe n3, the drain electrode phase of the source electrode of described nmos pipe n3 and described nmos pipe n4
Connect, the source ground of described nmos pipe n4；
Described 3rd branch road includes pmos pipe p5, pmos pipe p6, nmos pipe n5, nmos pipe n6, the source electrode of described pmos pipe p5 with
Described 3rd branch road power supply is connected, and the source electrode of described pmos pipe p6 is connected with the drain electrode of described pmos pipe p5, described pmos
The drain electrode of pipe p6 is connected with the drain electrode of described nmos pipe n5, the drain electrode phase of the source electrode of described nmos pipe n5 and described nmos pipe n6
Connect, the source ground of described nmos pipe n6；
Described 4th branch road includes pmos pipe p7, pmos pipe p8, nmos pipe n7, nmos pipe n8, the source electrode of described pmos pipe p7 with
Described 4th branch road power supply is connected, and the source electrode of described pmos pipe p8 is connected with the drain electrode of described pmos pipe p7, described pmos
The drain electrode of pipe p8 is connected with the drain electrode of described nmos pipe n7, the drain electrode phase of the source electrode of described nmos pipe n7 and described nmos pipe n8
Connect, the source ground of described nmos pipe n8；
Connecting node a of described p2 pipe drain electrode and the drain electrode of n1 pipe connects the grid of described pmos pipe p4, described nmos pipe n3 respectively
Grid, the grid of described pmos pipe p7, the grid of described nmos pipe n8, the connecting node of the drain electrode of described p4 pipe and the drain electrode of n3 pipe
B connects the grid of described pmos pipe p6, the grid of described nmos pipe n5, the grid of described pmos pipe p1, described nmos pipe respectively
The grid of n2, connecting node c of described p6 pipe drain electrode and the drain electrode of n5 pipe connects the grid of described pmos pipe p8, described nmos respectively
The grid of pipe n7, the grid of described pmos pipe p3, the grid of described nmos pipe n4, the connection of described p8 pipe drain electrode and the drain electrode of n7 pipe
Node d connects described pmos pipe p2 grid, the grid of described nmos pipe n1, the grid of described pmos pipe p5, described nmos respectively
The grid of pipe n6.
2. a kind of anti-single node seu according to claim 1 is reinforced new sram unit is it is characterised in that described
Sram read/write circuit (1) includes nmos pipe n9, nmos pipe n10, wordline wl, bit line bl, anti-phase bit line blb, described nmos pipe n9
Grid, the grid of described nmos pipe n10 be connected with described wordline wl respectively, the source electrode of described nmos pipe n9 is anti-phase with described
Bit line blb is connected, and the source electrode of described nmos pipe n10 is connected with described bit line bl, the drain electrode of described nmos pipe n9 with described
Node b is connected, and the drain electrode of described nmos pipe n10 is connected with described node c.
3. the new sram unit reinforced according to arbitrary described a kind of anti-single node seu of claim 1 or 2 it is characterised in that
Described sram read/write circuit (2) includes nmos pipe n11, nmos pipe n12, wordline wl, bit line bl, anti-phase bit line blb, described nmos
The grid of pipe n11, the grid of described nmos pipe n12 are connected with described wordline wl respectively, the source electrode of described nmos pipe n1 and institute
State anti-phase bit line blb to be connected, the source electrode of described nmos pipe n12 is connected with described bit line bl, the drain electrode of described nmos pipe n1
It is connected with described node d, the drain electrode of described nmos pipe n12 is connected with described node a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610841737.5A CN106373605A (en) | 2016-09-22 | 2016-09-22 | Novel anti single-node SRAM unit with reinforced SEU |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610841737.5A CN106373605A (en) | 2016-09-22 | 2016-09-22 | Novel anti single-node SRAM unit with reinforced SEU |
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| Publication Number | Publication Date |
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| CN106373605A true CN106373605A (en) | 2017-02-01 |
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| CN201610841737.5A Pending CN106373605A (en) | 2016-09-22 | 2016-09-22 | Novel anti single-node SRAM unit with reinforced SEU |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103778954A (en) * | 2014-02-24 | 2014-05-07 | 哈尔滨工业大学 | Multi-node upset resistant memorizer |
| CN105049031A (en) * | 2015-07-29 | 2015-11-11 | 西北工业大学 | DICE structure latch unit resisting single-particle irradiation effect |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
-
2016
- 2016-09-22 CN CN201610841737.5A patent/CN106373605A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103778954A (en) * | 2014-02-24 | 2014-05-07 | 哈尔滨工业大学 | Multi-node upset resistant memorizer |
| CN105049031A (en) * | 2015-07-29 | 2015-11-11 | 西北工业大学 | DICE structure latch unit resisting single-particle irradiation effect |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
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