CN106365109A - MEMS device, production method thereof, and electronic device - Google Patents
MEMS device, production method thereof, and electronic device Download PDFInfo
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- CN106365109A CN106365109A CN201510442736.9A CN201510442736A CN106365109A CN 106365109 A CN106365109 A CN 106365109A CN 201510442736 A CN201510442736 A CN 201510442736A CN 106365109 A CN106365109 A CN 106365109A
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Abstract
The invention relates to an MEMS device, a production method thereof, and an electronic device. The method comprises the following steps: 1, providing a semiconductor substrate, and forming an ion implantation area in a position needing a cavity on the semiconductor substrate to define the pattern of the cavity; 2, forming an MEMS element and a CMOS element on the semiconductor substrate, wherein the MEMS element is positioned above the ion implantation area; 3, patterning the area of the MEMS element to form a plurality of openings in order to expose the ion implantation area; and 4, carrying out wet etching to remove the ion implantation area in order to form the cavity under the MEMS element. The method allows the etching selectivity ratio of the ion implantation area to the semiconductor substrate to be 400 or above, and well controls the formation of the cavity in order to make the whole process be stable, so the sensitivity of the MEMS device is improved.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of mems device and its system
Preparation Method, electronic installation.
Background technology
With the continuous development of semiconductor technology, in the city of sensor (motion sensor) class product
On field, smart mobile phone, integrated cmos and MEMS (mems) device are increasingly becoming the most main
Stream, state-of-the-art technology, and the renewal with technology, the development side of this kind of transmission sensors product
To being the less size of scale, high-quality electric property and lower loss.
Wherein, microelectromechanical systems (mems) is in volume, power consumption, weight and in price
There is fairly obvious advantage, have been developed over multiple different sensors, such as micro-phone so far
Part, pressure transducer, acceleration transducer, inertial sensor and other devices.
In described mems device fabrication process, for example, there is cavity in the preparation process of mike
Etch process, to form cavity in mems substrate, the preparation method of described cavity is to hold at present
After row cmos technique, the geometry defining described sensor is etched by rie, finally leads to
Cross xef2Base gas is etched, and removes section substrate material, forms described cavity.
Constantly reducing with semiconductor device, in the above-mentioned methods due in rie formed opening between
Gap very little, is difficult to control the etching of cavity in subsequent step, leads to cavity etch wayward, steady
Qualitative difference, has had a strong impact on the sensitivity of mems device and yield it is therefore desirable to described side at present
Method is improved further, to eliminate the problems referred to above.
Content of the invention
Introduce a series of concept of reduced forms in Summary, this will be in specific embodiment party
Formula partly middle further description.The Summary of the present invention is not meant to attempt to limit
Go out key feature and the essential features of technical scheme required for protection, more do not mean that and attempt really
The protection domain of fixed technical scheme required for protection.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of mems device,
Including:
Step s1: Semiconductor substrate, the position shape of cavity to be formed in described Semiconductor substrate are provided
Become to have ion implanted regions, to define the pattern of described cavity；
Step s2: form mems element and cmos element on the semiconductor substrate, wherein,
Described mems element is located at the top of described ion implanted regions；
Step s3: the region that the described mems element of patterning is located, to form some openings, expose
Described ion implanted regions；
Step s4: remove described ion implanted regions from wet etching, with described mems element
Formed below described cavity.
Alternatively, in described step s1, described ion implanted regions are phosphonium ion injection zone.
Alternatively, in described step s4, carry out described wet etching from isotropic etching liquid.
Alternatively, in described step s4, from hno3, one or more of hf and hac enter
The described wet etching of row.
Alternatively, in described step s4, the etching of described ion implanted regions and described Semiconductor substrate
Select ratio more than 400.
Alternatively, described step s1 includes:
Step s11: Semiconductor substrate is provided, is formed with mask layer on the semiconductor substrate；
Step s12: ion implanting is executed for mask with described mask layer, with described Semiconductor substrate
Form described ion implanted regions.
Alternatively, the energy in the injection of described step s1 intermediate ion is 450-1500kev, described to be formed
Ion implanted regions.
Alternatively, the method selecting reactive ion etching in described step s3 patterns described mems
The region that element is located, to define the geometry of described mems device.
Present invention also offers a kind of mems device being prepared based on above-mentioned method.
Present invention also offers a kind of electronic installation, including above-mentioned mems device.
The present invention is in order to solve problems of the prior art, there is provided a kind of system of mems device
Preparation Method, in the process to described quasiconductor before formation mems element, cmos element
Substrate carries out ion implanting, to form ion implanted regions, defines cavity pattern, then described from
Form mems element above sub- injection zone, finally pattern described mems element region,
Expose described ion implanted regions and described ion implanted region removed by wet etching to form opening
Domain, to form cavity.
Etching choosing by ion implanted regions described in the method for the invention and described Semiconductor substrate
Select ratio more than 400, the formation of described cavity can be better controled over, make whole technical process more
Stable, improve the sensitivity of described mems device further.
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.In accompanying drawing
Show embodiments of the invention and its description, for explaining assembly of the invention and principle.In accompanying drawing
In,
Fig. 1 a-1e is that the preparation process of mems device described in the embodiment of the invention is illustrated
Figure；
Fig. 2 is the preparation technology flow process of mems device described in the embodiment of the invention
Figure.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can one
Or multiple these details and be carried out.In other examples, in order to avoid obscuring with the present invention,
Some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, it is open thoroughly and complete to provide these embodiments will make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He area
Size and relative size may be exaggerated.Same reference numerals represent identical element from start to finish.
It should be understood that be referred to as when element or layer " ... on ", " with ... adjacent ", " being connected to " or " coupling
Close " other elements or during layer, its can directly on other elements or layer, adjacent thereto, connect
Or be coupled to other elements or layer, or there may be element between two parties or layer.On the contrary, when element is claimed
For " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other unit
When part or layer, then there is not element between two parties or layer.Although it should be understood that can using term first, the
2nd, third class describes various elements, part, area, floor and/or part, these elements, part, area,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, part,
Area, floor or part and another element, part, area, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, part, area, floor or part be represented by the second element,
Part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ",
" ... on ", " above " etc., can describe for convenience here and be used thus describing in figure
A shown element or the relation of feature and other elements or feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term be intended to also include using and operating in device different orientation.Example
As if the device upset in accompanying drawing, then, being described as " below other elements " or " its it
Under " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, example
Property term " ... below " and " ... under " may include upper and lower two orientation.Device can additionally take
To (ratate 90 degrees or other orientation) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When here uses, " one " of singulative, " one " and " described/to be somebody's turn to do " are also intended to including plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " inclusion ",
When using in this specification, determine described feature, integer, step, operation, element and/or part
Presence, but be not excluded for one or more other features, integer, step, operation, element, part
And/or group presence or interpolation.When here uses, term "and/or" includes any of related Listed Items
And all combinations.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, so that explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these describe in detail, the present invention can also have other embodiment.
Embodiment 1
In order to solve problems of the prior art, the invention provides a kind of preparation of mems device
Method, below in conjunction with the accompanying drawings 1a-1e methods described is described further.
First, execution step 101, provide Semiconductor substrate 101, wanted shape in described Semiconductor substrate
The position becoming cavity is formed with ion implanted regions 102, to define the pattern of described cavity.
Specifically, as shown in Figure 1a, wherein said Semiconductor substrate 101 can be the following material being previously mentioned
At least one in material: stacking silicon (ssoi), insulation on silicon, silicon-on-insulator (soi), insulator
Stacking SiGe (s-sigeoi), germanium on insulator SiClx (sigeoi) and germanium on insulator on body
(geoi) etc..
Alternatively, described Semiconductor substrate 101 selects silicon.
Before forming described mems element and cmos element in described Semiconductor substrate 101
Define described cavity pattern, accurately to control the etching of described cavity in subsequent steps, wherein,
Described cavity pattern can be defined by the method for ion implanting, by described Semiconductor substrate
Form ion implanted regions, to form the pattern being different from described Semiconductor substrate.
Specifically, the method for described ion implanting may include that in described Semiconductor substrate in this application
Upper formation mask layer, is formed with opening in wherein said mask layer, the size of described opening is equal to described sky
The size in chamber, as shown in Figure 1a；Then ion implanting is executed for mask with described mask layer, with described
Form described ion implanted regions 102, as shown in Figure 1 b in Semiconductor substrate.
Alternatively, wherein, described mask layer can select any hard mask layer, metal mask layer, also may be used
With from photoresist layer, darc etc. it is not limited to a certain, described mask layer in this embodiment
From photoresist.
In the step of execution ion implanting, ion implanting can be controlled by adjusting ion implantation energy
Depth, the energy of for example described ion implanting is 450-1500kev, to form described ion implanted regions.
Alternatively, the energy of described ion implanting is 600-1200kev, and for example described ion implanting
Energy is 800-1000kev, or the energy of described ion implanting is 900kev.
Wherein, the species of described ion implanting is also not limited to a certain kind, for example, can be N-shaped ion
Or p-type ion.
Further, in this embodiment, described ion implanting selects phosphonium ion to inject.
Execution step 102, forms mems element and cmos element on the semiconductor substrate, its
In, described mems element is located at the top of described ion implanted regions.
Specifically, as illustrated in figure 1 c, form mems unit in this step on the semiconductor substrate
Part and cmos element, wherein, described cmos element is located at the side of described mems element, such as
In Fig. 1 c, it is cmos element positioned at the rightmost side.Alternatively, described mems element is positioned at described
The top of ion implanted regions 102.
Alternatively, it is also formed with interlayer dielectric layer 103 on the semiconductor substrate, wherein, described
Mems element and cmos element are formed in described interlayer dielectric layer 103.
Wherein, described interlayer dielectric layer 103 can use such as sio2, fluorocarbon (cf), carbon dope
Silicon oxide (sioc) or carbonitride of silicium (sicn) etc..Or, it is possible to use at fluorocarbon (cf)
On define film of sicn thin film etc..
Then pattern described interlayer dielectric layer 103, to form various patterns, and then form mems unit
Part and cmos element.
For example, the mems element being formed on the semiconductor substrate in this application is sensor, than
As microphone sensor, include being formed above described ion implanted regions in the described mike being formed
Vibrating diaphragm 1031, and be located at described vibrating diaphragm both sides interconnection structure, wherein, described interconnection structure includes
Some metal levels and some through holes replace connect setting.
Wherein, described cmos element can include grid, source and drain, any type of memory element etc.,
It is not limited to a certain kind, as illustrated in figure 1 c, described cmos element is also formed with metal interconnection
Structure.
Execution step 103, the region that the described mems element of patterning is located, to form opening, expose
Described ion implanted regions 102.
Specifically, as shown in Figure 1 d, etch the region that described mems element is located in this step,
To define the geometry of described mems element.
Specifically, dry etching can be selected in this step, for example, pass through to select appropriate etching gas
To form described opening.
Alternatively, dry etching, reactive ion etching (rie), ion beam can be selected in this step
Etching, plasma etching.
Further, carry out preferably by one or more rie step in the specific embodiment of the invention
Dry etching, for example, can select n in the present invention2In conduct etching atmosphere, can also add simultaneously
Enter other a small amount of gas such as cf4、co2、o2, described etching pressure can be 50-200mtorr,
It is preferably 100-150mtorr, power is 200-600w, described etching period is in the present invention
5-80s, select larger gas flow in the present invention, in n of the present invention simultaneously2Flow be
30-300sccm.
Alternatively, described patterning method can be from various methods commonly used in the art, such as described
Form mask layer above device, such as photoresist layer, and to described photoresist layer exposure imaging, then with
Described mask layer is interlayer dielectric layer 103 described in mask etch, to form some described openings.
Alternatively, the described layer removing described vibrating diaphragm 1031 top can also be etched in this step further
Between dielectric layer.
Wherein, the described interlayer dielectric layer of described vibrating diaphragm 1031 top can be carried out with described opening simultaneously,
It is also used as a single step to carry out, method when individually removing can select conventional method,
Will not be described here.
Execution step 104, removes described ion implanted regions 102 from wet etching, to form described sky
Chamber.
Specifically, as shown in fig. le, described ion implanted regions 102 are removed in this step, with institute
State the cavity formed below of mems element (such as mike), to form the sensing of mike further
Electric capacity.
Specifically, carry out described wet etching from isotropic etching liquid in this step, for example, can select
It is etched with various acidic etchant.
Further, hno can be selected in this step3, one or more of hf and hac carry out
Described wet etching.It should be noted that described etchant is not limited to a certain kind in this embodiment,
Can be selected according to actual needs.
In this step, the etching selectivity of described ion implanted regions and described Semiconductor substrate is more than
400.
For example described Semiconductor substrate selects silicon in this embodiment, and described ion implanting is p, works as selection
hno3, one or more of hf and hac be when carrying out described wet etching, described ion implanted regions
It is much larger than 400 with the etching selectivity of described Semiconductor substrate, there is very big etching selectivity, permissible
Preferably control the profile of described cavity, described Semiconductor substrate will not be caused to damage, improve further
The sensitivity of described mems device.
So far, complete the introduction of the correlation step of mems device preparation of the embodiment of the present invention.Upper
After stating step, other correlation step can also be included, here is omitted.And, except above-mentioned step
Outside rapid, the preparation method of the present embodiment can also be among each step above-mentioned or between different steps
Including other steps, these steps all can be realized by various techniques of the prior art, herein not
Repeat again.
The present invention is in order to solve problems of the prior art, there is provided a kind of system of mems device
Preparation Method, in the process to described quasiconductor before formation mems element, cmos element
Substrate carries out ion implanting, to form ion implanted regions, defines cavity pattern, then described from
Form mems element above sub- injection zone, finally pattern described mems element region,
Expose described ion implanted regions and described ion implanted region removed by wet etching to form opening
Domain, to form cavity.
Etching choosing by ion implanted regions described in the method for the invention and described Semiconductor substrate
Select ratio more than 400, the formation of described cavity can be better controled over, make whole technical process more
Stable, improve the sensitivity of described mems device further.
Fig. 2 is the preparation technology flow chart of mems device described in the embodiment of the invention,
Specifically include following steps:
Step s1: Semiconductor substrate, the position shape of cavity to be formed in described Semiconductor substrate are provided
Become to have ion implanted regions, to define the pattern of described cavity；
Step s2: form mems element and cmos element on the semiconductor substrate, wherein,
Described mems element is located at the top of described ion implanted regions；
Step s3: the region that the described mems element of patterning is located, to form some openings, expose
Described ion implanted regions；
Step s4: remove described ion implanted regions from wet etching, with described mems element
Formed below described cavity.
Embodiment 2
Present invention also offers a kind of mems device, described mems device is by embodiment 1
Methods described prepares, the cavity shape below mems element described in described mems device
It is more prone to control, be more nearly expected pattern, make whole technical process more stable, carry further
The sensitivity of high described mems device, improves product yield.
Embodiment 3
Present invention also offers a kind of electronic installation, including the mems device described in embodiment 2.Wherein,
Semiconductor device is the mems device described in embodiment 2, or the preparation method according to embodiment 1
The mems device obtaining.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, vcd, dvd, navigator, photographing unit, video camera, recording pen, mp3,
Any electronic product such as mp4, psp or equipment, alternatively any centre including described mems device
Product.The electronic installation of the embodiment of the present invention, due to employing above-mentioned mems device, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and be not intended to limit the invention to described scope of embodiments
Interior.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, root
More kinds of variants and modifications can also be made according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and its waits
Effect scope is defined.
Claims (10)
1. a kind of preparation method of mems device, comprising:
Step s1: Semiconductor substrate, the position shape of cavity to be formed in described Semiconductor substrate are provided
Become to have ion implanted regions, to define the pattern of described cavity；
Step s2: form mems element and cmos element on the semiconductor substrate, wherein,
Described mems element is located at the top of described ion implanted regions；
Step s3: the region that the described mems element of patterning is located, to form some openings, expose
Described ion implanted regions；
Step s4: remove described ion implanted regions from wet etching, with described mems element
Formed below described cavity.
2. method according to claim 1 is it is characterised in that in described step s1, described
Ion implanted regions are phosphonium ion injection zone.
3. method according to claim 1 is it is characterised in that in described step s4, select
Isotropic etching liquid carries out described wet etching.
4. method according to claim 1 is it is characterised in that in described step s4, select
hno3, one or more of hf and hac carry out described wet etching.
5. method according to claim 1 is it is characterised in that in described step s4, described
The etching selectivity of ion implanted regions and described Semiconductor substrate is more than 400.
6. method according to claim 1 is it is characterised in that described step s1 includes:
Step s11: Semiconductor substrate is provided, is formed with mask layer on the semiconductor substrate；
Step s12: ion implanting is executed for mask with described mask layer, with described Semiconductor substrate
Form described ion implanted regions.
7. the method according to claim 1 or 6 it is characterised in that in described step s1 from
The energy of son injection is 450-1500kev, to form described ion implanted regions.
8. method according to claim 1 is it is characterised in that select anti-in described step s3
The method answering ion etching patterns the region that described mems element is located, to define described mems
The geometry of device.
9. a kind of mems device being prepared based on the method described in one of claim 1 to 8.
10. a kind of electronic installation, including the mems device described in claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510442736.9A CN106365109A (en) | 2015-07-24 | 2015-07-24 | MEMS device, production method thereof, and electronic device |
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| CN201510442736.9A CN106365109A (en) | 2015-07-24 | 2015-07-24 | MEMS device, production method thereof, and electronic device |
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Cited By (1)
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| WO2024016095A1 (en) * | 2022-07-18 | 2024-01-25 | 京东方科技集团股份有限公司 | Filter unit and preparation method therefor, and electronic apparatus |
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