CN106340319B - 用于保护和验证地址数据的方法和电路 - Google Patents

用于保护和验证地址数据的方法和电路 Download PDF

Info

Publication number
CN106340319B
CN106340319B CN201610108842.8A CN201610108842A CN106340319B CN 106340319 B CN106340319 B CN 106340319B CN 201610108842 A CN201610108842 A CN 201610108842A CN 106340319 B CN106340319 B CN 106340319B
Authority
CN
China
Prior art keywords
address
data
write
circuit
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610108842.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN106340319A (zh
Inventor
E·贝尔纳斯科尼
R·奥科诺尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Publication of CN106340319A publication Critical patent/CN106340319A/zh
Application granted granted Critical
Publication of CN106340319B publication Critical patent/CN106340319B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Storage Device Security (AREA)
CN201610108842.8A 2015-07-10 2016-02-26 用于保护和验证地址数据的方法和电路 Active CN106340319B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1556621 2015-07-10
FR1556621A FR3038752B1 (fr) 2015-07-10 2015-07-10 Procede et circuit pour proteger et verifier des donnees d'adresse

Publications (2)

Publication Number Publication Date
CN106340319A CN106340319A (zh) 2017-01-18
CN106340319B true CN106340319B (zh) 2020-05-12

Family

ID=54848669

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201610108842.8A Active CN106340319B (zh) 2015-07-10 2016-02-26 用于保护和验证地址数据的方法和电路
CN201620148491.9U Withdrawn - After Issue CN205692570U (zh) 2015-07-10 2016-02-26 用于保护和验证存储器地址数据的电路和地址保护/验证电路

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201620148491.9U Withdrawn - After Issue CN205692570U (zh) 2015-07-10 2016-02-26 用于保护和验证存储器地址数据的电路和地址保护/验证电路

Country Status (3)

Country Link
US (1) US10248580B2 (cg-RX-API-DMAC10.html)
CN (2) CN106340319B (cg-RX-API-DMAC10.html)
FR (1) FR3038752B1 (cg-RX-API-DMAC10.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3038752B1 (fr) 2015-07-10 2018-07-27 Stmicroelectronics (Rousset) Sas Procede et circuit pour proteger et verifier des donnees d'adresse
US10489241B2 (en) * 2015-12-30 2019-11-26 Arteris, Inc. Control and address redundancy in storage buffer
CN108733311B (zh) * 2017-04-17 2021-09-10 伊姆西Ip控股有限责任公司 用于管理存储系统的方法和设备
FR3077893B1 (fr) * 2018-02-14 2020-09-11 St Microelectronics Rousset Systeme de controle d'acces a une memoire
US10824560B2 (en) * 2019-02-18 2020-11-03 Nxp B.V. Using a memory safety violation indicator to detect accesses to an out-of-bounds or unallocated memory area
US11789647B2 (en) * 2019-12-20 2023-10-17 Micron Technology, Inc. Address verification for a memory device
CN113312294B (zh) * 2020-02-27 2024-06-18 瑞昱半导体股份有限公司 电子装置以及通讯方法
CN112948167B (zh) 2021-03-31 2022-10-18 地平线征程(杭州)人工智能科技有限公司 数据通路的保护电路、方法、装置及计算机可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787481A (en) * 1994-03-24 1998-07-28 Texas Instruments Incorporated System for managing write and/or read access priorities between central processor and memory operationally connected
CN1825296A (zh) * 2005-03-25 2006-08-30 威盛电子股份有限公司 介接不同宽度总线的接口电路、系统及方法
EP1873649A1 (en) * 2006-06-28 2008-01-02 Hitachi, Ltd. Storage system and data protection method therefor
CN205692570U (zh) * 2015-07-10 2016-11-16 意法半导体(鲁塞)公司 用于保护和验证存储器地址数据的电路和地址保护/验证电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10320913A (ja) * 1997-05-23 1998-12-04 Sony Corp データ記録装置および方法、データ再生装置および方法、データ記録再生装置および方法、並びに伝送媒体
US7433980B1 (en) * 2005-04-21 2008-10-07 Xilinx, Inc. Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports
US8402349B2 (en) * 2010-12-06 2013-03-19 Apple Inc. Two dimensional data randomization for a memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787481A (en) * 1994-03-24 1998-07-28 Texas Instruments Incorporated System for managing write and/or read access priorities between central processor and memory operationally connected
CN1825296A (zh) * 2005-03-25 2006-08-30 威盛电子股份有限公司 介接不同宽度总线的接口电路、系统及方法
EP1873649A1 (en) * 2006-06-28 2008-01-02 Hitachi, Ltd. Storage system and data protection method therefor
CN205692570U (zh) * 2015-07-10 2016-11-16 意法半导体(鲁塞)公司 用于保护和验证存储器地址数据的电路和地址保护/验证电路

Also Published As

Publication number Publication date
FR3038752B1 (fr) 2018-07-27
FR3038752A1 (cg-RX-API-DMAC10.html) 2017-01-13
US10248580B2 (en) 2019-04-02
CN205692570U (zh) 2016-11-16
CN106340319A (zh) 2017-01-18
US20170010980A1 (en) 2017-01-12

Similar Documents

Publication Publication Date Title
US10248580B2 (en) Method and circuit for protecting and verifying address data
CN109993008B (zh) 用于隐式完整性的方法和布置
US7149945B2 (en) Systems and methods for providing error correction code testing functionality
US7506217B2 (en) Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability
US7139965B2 (en) Bus device that concurrently synchronizes source synchronous data while performing error detection and correction
US9665423B2 (en) End-to-end error detection and correction
US5331645A (en) Expandable digital error detection and correction device
US6105155A (en) Method and apparatus for performing on-chip function checks and locating detected anomalies within a nested time interval using CRCs or the like
CN111880961A (zh) 用于透明寄存器数据错误检测和纠正的系统和方法
US20220327020A1 (en) Error rate reduction in a non-volatile memory (nvm), including magneto-resistive random access memories (mrams)
JP2006293982A (ja) アクセス時間が減少したフラッシュメモリ装置
US12038808B2 (en) Memory integrity check
WO1990002374A1 (en) Failure detection for partial write operations for memories
US7321996B1 (en) Digital data error insertion methods and apparatus
US9983926B2 (en) Apparatus, system and method for protecting data
CN210984286U (zh) 错误校正码存储器和电子电路
US11132483B2 (en) Method and arrangement for forming an electronic circuit
US5774482A (en) Apparatus and method for processing errors associated with data transfers in a computer
US11314513B2 (en) Circuit for verifying the content of registers
US11797306B2 (en) Circuit for verifying the content of registers
US20050289409A1 (en) Parallel data bus
US10250279B2 (en) Circuits and methods for writing and reading data
US12066888B2 (en) Efficient security metadata encoding in error correcting code (ECC) memory without dedicated ECC bits
CN102521170B (zh) 测量仪器校准数据病毒免疫和自恢复系统
JPH06103469B2 (ja) メモリ制御回路

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant