CN106301656A - A kind of method and device improving timestamp certainty of measurement - Google Patents
A kind of method and device improving timestamp certainty of measurement Download PDFInfo
- Publication number
- CN106301656A CN106301656A CN201610787322.4A CN201610787322A CN106301656A CN 106301656 A CN106301656 A CN 106301656A CN 201610787322 A CN201610787322 A CN 201610787322A CN 106301656 A CN106301656 A CN 106301656A
- Authority
- CN
- China
- Prior art keywords
- sampling clock
- tested
- cycle
- signal
- enumerator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000005259 measurement Methods 0.000 title claims abstract description 31
- 238000005070 sampling Methods 0.000 claims abstract description 130
- 230000000737 periodic effect Effects 0.000 claims abstract description 96
- 230000000630 rising effect Effects 0.000 claims description 40
- 230000002123 temporal effect Effects 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 3
- 206010044565 Tremor Diseases 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Measurement Of Unknown Time Intervals (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
Abstract
The invention provides a kind of method and device improving timestamp certainty of measurement, described method includes: acquisition and tested periodic signal have the sampling clock of predeterminated frequency deviation；The frequency of tested periodic signal is f1, the frequency of sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；Utilizing sampling clock to sample tested periodic signal, it is thus achieved that a periodic samples signal, the cycle of this periodic samples signal is the cycle T of tested periodic signal1N times；When tested event being detected in certain moment, obtain count value n of the coarse counter corresponding with this moment, and count value m of thin enumerator, and obtain timestamp [n+m* (1/N)] the * T of tested event according to n and m2.The method and device improving timestamp certainty of measurement that the present invention provides, it is achieved get up more convenient, relatively low to device performance requirements, and can reach to be better than the time precision of conventional clock counting method as required.
Description
Technical field
The present invention relates to field of computer technology, be specifically related to a kind of method and device improving timestamp certainty of measurement.
Background technology
In the application such as measurement, control, more and more use distributed system.Various kinds of equipment (such as computer, sensing
Device, numerical control device etc.) it is interconnected to form network, and according to the time synchronized between certain protocol realization all devices, so that
Individual device performs task jointly with the harmony of height.Different application is different to the requirement of timing tracking accuracy, the most general
Logical audio network requires nothing more than the synchronization of ms level, and industrial bus the most typically requires the synchronization of sub-us level.When IEEE-1588 is accurate
Between synchronous protocol (PTP) be i.e. in order at precise synchronization purpose formulate, (include any similar association in this agreement
View) in, having directly affect most to timing tracking accuracy is i.e. " timestamp "." timestamp " of one event refers to that this event occurs
Moment with reference to the time interval in zero moment, determine " timestamp " precision is time measurement technology therein.
Accurately " timestamp " provide the floor portions being usually located at agreement, such as in time synchronization network based on Ethernet
In network, " timestamp " is given in data link layer, and some PHY chip have a function of measurement " timestamp ", or can be can
Programmed digital logic device (such as FPGA) realizes measure of time.
Realizing measure of time in FPGA, simplest method is clock counter, and the resolution of the method is i.e. counting
One cycle of clock, such as, be i.e. 10ns for 100MHz clock；Another kind of method is temporal interpolation, and its resolution depends on
In FPGA, the unit time delay of time delay chain, can generally achieve less than 100ps.For different application demands, both approaches
All being widely used, clock counter method realizes simple, it is adaptable to general synchronization system；Temporal interpolation method is more complicated,
Can reach the highest resolution, the most special split-second precision numeral conversion (TDC) chip is i.e. real based on this principle
Existing.
The resolution of clock counter method depends on the frequency of counting clock, as a rule for the resolution of 10ns rank
Rate is easy to reach, but to realize higher resolution then can be to device (such as FPGA) performance and circuit design etc. in terms of
All proposing higher requirement, therefore this is a kind of technology being only applicable to network less demanding to synchronization accuracy.And in the time
The shortcoming of insert method is to realize complexity, has the rigid line resource that can use as time delay chain, and require these time delays in needing FPGA
The time delay of unit is uniform and stable.This all proposes more harsh requirement to aspects such as device technology, stability and concordance, therefore this
It it is a kind of method of relatively high cost.
Summary of the invention
For defect of the prior art, the present invention provides a kind of method and device improving timestamp certainty of measurement, real
Now get up more convenient, relatively low to device performance requirements, and can reach to be better than the time of conventional clock counting method as required
Precision.
First aspect, the invention provides a kind of method improving timestamp certainty of measurement, including:
Acquisition and tested periodic signal have the sampling clock of predeterminated frequency deviation；The frequency of wherein said tested periodic signal
Rate is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；
Utilize described sampling clock that described tested periodic signal is sampled, it is thus achieved that a periodic samples signal, should
The cycle of periodic samples signal is the cycle T of described tested periodic signal1N times；
Use coarse counter that from 0, the rising edge of described sampling clock is started continuous counter, add up in tested event and comprise
The number in cycle of sampling clock；
Use thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter, but at described periodic samples
Each trailing edge of signal is reset, and this thin enumerator is circulated with a cycle of described periodic samples signal for length
Counting, adds up the part in cycle less than a sampling clock in tested event, and the resolution of thin enumerator is sampling clock
Cycle T21/N times, i.e. (1/N) * T2；
When tested event being detected in certain moment, obtain count value n of the coarse counter corresponding with this moment, Yi Jiyu
Count value m of the thin enumerator that this moment is corresponding, and according to described n and described m, obtain the timestamp [n+m* (1/ of tested event
N)]*T2, wherein, the periodicity of the sampling clock that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point, T2
Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
Further, described acquisition and tested periodic signal have the sampling clock of predeterminated frequency deviation, including:
Utilize the phaselocked loop resource in phase-locked loop circuit or programmable digital logic device FPGA to produce to believe with the tested cycle
Number there is the sampling clock of predeterminated frequency deviation.
Further, N value is 2,4,8,16,32,64 or 128.
Second aspect, present invention also offers a kind of device improving timestamp certainty of measurement, including:
Acquiring unit, has the sampling clock of predeterminated frequency deviation for acquisition and tested periodic signal；Wherein said quilt
The frequency surveying periodic signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；
Sampling unit, is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a cycle
Property sampled signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
First counting unit, for using coarse counter that from 0, the rising edge of described sampling clock is started continuous counter, system
Count the number in the cycle of the sampling clock comprised in tested event；
Second counting unit, for using thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter, but
Each trailing edge at described periodic samples signal is reset, and this thin enumerator is with a week of described periodic samples signal
Phase is that length is circulated counting, adds up the part in cycle less than a sampling clock in tested event；Thin enumerator
Resolution is the cycle T of sampling clock21/N times, i.e. (1/N) * T2；
Timestamp acquiring unit, for when certain moment detects tested event, obtains the thick counting corresponding with this moment
Count value n of device, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain tested thing
Timestamp [n+m/N] the * T of part2, wherein, the sampling clock that n+m/N is crossed over by tested event place moment Distance Time zero point
Periodicity, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
Further, described acquiring unit specifically for:
Utilize the phaselocked loop resource in phase-locked loop circuit or programmable digital logic device FPGA to produce to believe with the tested cycle
Number there is the sampling clock of predeterminated frequency deviation.
Further, N value is 2,4,8,16,32,64 or 128.
The third aspect, present invention also offers a kind of device improving timestamp certainty of measurement, including: phase-locked loop circuit,
Sampler, coarse counter, thin enumerator and processor；
Wherein, described phase-locked loop circuit has the sampling clock of predeterminated frequency deviation for acquisition and tested periodic signal；
The frequency of wherein said tested periodic signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is
Positive integer；
Described sampler is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a cycle
Property sampled signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
Described coarse counter, for the rising edge of described sampling clock is started continuous counter from 0, adds up in tested event
The number in the cycle of the sampling clock comprised；
Described thin enumerator, for starting continuous counter to the rising edge of described sampling clock from 0, but in described periodicity
Each trailing edge of sampled signal is reset, and is circulated counting with a cycle of described periodic samples signal for length,
For adding up the part in the cycle less than a sampling clock in tested event；The resolution of thin enumerator is sampling clock
Cycle T21/N times, i.e. (1/N) * T2；
Described processor, for when certain moment detects tested event, obtains the coarse counter corresponding with this moment
Count value n, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain tested event
Timestamp [n+m* (1/N)] * T2, wherein, the sampling that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
The periodicity of clock, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
Further, N value is 2,4,8,16,32,64 or 128.
As shown from the above technical solution, the method improving timestamp certainty of measurement that the present invention provides uses one with tested
There is the sampling clock of tiny frequency deviation and sample described tested periodic signal in periodic signal, obtains periodic samples letter
Number, in the moment then occurred according to described sampling clock, described periodic samples signal and tested event, utilize coarse counter
Deficiency in the number in the cycle of the sampling clock comprised in the tested event of statistics, and the tested event of thin counters count
The part in the cycle of one sampling clock, the common timestamp obtaining tested event.The raising timestamp that the present invention provides is measured
The method of precision, it is achieved get up more convenient, relatively low to device performance requirements, and can reach as required to be better than conventional clock
The time precision of counting method.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to according to
These accompanying drawings obtain other accompanying drawing.
Fig. 1 is the method flow diagram improving timestamp certainty of measurement that the embodiment of the present invention one provides；
Fig. 2 is the principle explanatory diagram that split-second precision is measured；
Fig. 3 is that split-second precision measures exemplary plot；
Fig. 4 is the structural representation of the device improving timestamp certainty of measurement that the embodiment of the present invention two provides；
Fig. 5 is the structural representation of the device improving timestamp certainty of measurement that the embodiment of the present invention three provides.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is carried out clear, complete description, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
The embodiment of the present invention one provides a kind of method improving timestamp certainty of measurement, sees Fig. 1, the method include as
Lower step:
Step 101: acquisition and tested periodic signal have the sampling clock of predeterminated frequency deviation；The wherein said tested cycle
The frequency of signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer.
In this step, it is possible to use the phaselocked loop money in phase-locked loop circuit PLL or programmable digital logic device FPGA
Source generation and tested periodic signal have the sampling clock of predeterminated frequency deviation.Wherein, the value of N is according to tested periodic signal
Frequency and the required precision of timestamp is determined.In theory, in the case of tested periodic signal frequency determines, N value
The biggest, sampling clock is the least with the frequency departure of tested periodic signal, and the timestamp of the event to be measured finally determined is the most accurate.
Such as, N value can be 2,4,8,16,32,64 or 128.
Being tested periodic signal for example, with reference to Fig. 3, clk_B, clk_A is having with tested periodic signal clk_B of acquisition
The sampling clock of predeterminated frequency deviation, frequency f of clk_A2Frequency f for 5Hz, clk_B1For 4Hz, f2=(1+1/4) * f1, i.e.
N=4.In this case, be equivalent to the cycle T of tested periodic signal clk_B by subsequent sampling process1It is subdivided into 4 parts,
Such that it is able to reach the resolution of 0.05s.And for example, continue to keep f2=5Hz, f1=4Hz, as N=64, is equivalent to tested
The cycle T of periodic signal clk_B1It is subdivided into 64 parts, such that it is able to reach the resolution of 3.9ms.
And for example, f is worked as1For 25MHz, f2=(1+1/64) * f1Time, be equivalent to the cycle T of tested periodic signal clk_B1Carefully
It is divided into 64 parts, such that it is able to reach the resolution of 6.25ns.
And for example, f is worked as1For 25MHz, f2=(1+1/128) * f1Time, be equivalent to the cycle T of tested periodic signal clk_B1
It is subdivided into 128 parts, such that it is able to reach the resolution of 3.125ns.
Step 102: utilize described sampling clock that described tested periodic signal is sampled, it is thus achieved that a periodic samples
Signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times.
In this step, see Fig. 3, with clk_A, clk_B is sampled, obtain a periodic samples signal samp, it
Cycle is N=4 times of the cycle of tested periodic signal clk_B.
Step 103: use coarse counter that from 0, the rising edge of described sampling clock is started continuous counter, add up tested thing
The number in the cycle of the sampling clock comprised in part.
In this step, using clk_B at the rising edge in e moment as tested event, measure this with the resolution of 0.05s
The timestamp of event.In Fig. 3, coarse counter rough is according to clk_A rising edge continuous counter, and it points out to comprise in the tested time
The number in clk_A cycle.
Step 104: use thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter, but in described week
Each trailing edge of phase property sampled signal is reset, and this thin enumerator is with cycle of described periodic samples signal as length
Being circulated counting, add up the part in cycle less than a sampling clock in tested event, the resolution of thin enumerator is
The cycle T of sampling clock21/N times, i.e. (1/N) * T2。
In this step, see Fig. 3, thin enumerator fine also according to clk_A rising edge count, but samp each under
Drop along time be reset, i.e. it is circulated counting with a cycle of samp for length, utilizes thin enumerator fine to calculate
The part less than a clk_A cycle in the tested time, then the resolution of thin enumerator is T1-T2=[(N+1)/N] * T2-T2
=(1/N) * T2, the cycle T that resolution is sampling clock of i.e. thin enumerator21/N times, i.e. (1/N) * T2。
Step 105: when tested event being detected in certain moment, obtains the count value of the coarse counter corresponding with this moment
N, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain the timestamp of tested event
[n+m*(1/N)]*T2, wherein, the sampling clock that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
Periodicity, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
In this step, see Fig. 3, clk_A tested event to be detected when the rising edge in c moment (clk_B is in the e moment
Rising edge), now coarse counter rough=5, represent 5 clk_A cycles；Thin enumerator fine=3, represents tested event
B edge 3/4 clk_A cycle afterwards at clk_A.Comprehensive thickness counting, obtains tested incident distance time zero 5.75
Clk_A cycle, i.e. 1.15s, this is the timestamp of tested event.
Seen from the above description, the embodiment of the present invention provide improve timestamp certainty of measurement method, uses one and
There is the sampling clock of tiny frequency deviation and sample described tested periodic signal in tested periodic signal, obtains periodically adopting
Sample signal, in the moment then occurred according to described sampling clock, described periodic samples signal and tested event, utilizes thick meter
The number in the cycle of the sampling clock comprised in the tested event of number device statistics, and in the tested event of thin counters count
Less than the part in the cycle of a sampling clock, the common timestamp obtaining tested event.The raising that the embodiment of the present invention provides
The method of timestamp certainty of measurement, it is achieved get up more convenient, relatively low to device performance requirements, and can reach excellent as required
Time precision in conventional clock counting method.
The resolution that can realize due to the method improving timestamp certainty of measurement of embodiment of the present invention offer depends on
The fine degree of the frequency departure of sampling clock and tested periodic signal, namely depend on the size of N value, when N value is the biggest,
The timestamp of the event to be measured obtained is more fine.I.e. improving the value of N can make resolution have a more raising, but the taking of N
Value is limited to phaselocked loop and clock quality.
The method improving timestamp certainty of measurement that the embodiment of the present invention provides, based on similar slide gauge the most former
Reason, the i.e. phase contrast of two clocks with tiny frequency deviation can regularly, periodically change.Such as in Fig. 2, one
The clock clk_B of the clock clk_A of 5Hz and a 4Hz is phase alignment when a moment, and after 1 second, clk_A has passed by 5
In the cycle, clk_B has passed by 4 cycles, then the leading clk_B of clk_A mono-π phase place complete cycle that is 2 and again reach phase alignment
(d moment).During a moment to d moment, often the time difference through cycle both corresponding rising edge be followed successively by 0s,
0.05s, 0.1s, 0.15s, 2s (0s), i.e. a cycle to clk_A have done 1/4 segmentation, such that it is able to reach dividing of 0.05s
Resolution.
In theory, the resolution that the method improving timestamp certainty of measurement that the embodiment of the present invention provides can realize depends on
Fine degree in sampling clock Yu the frequency departure of tested periodic signal.In the design, it is possible to use phase-locked loop circuit (or
Phaselocked loop resource in programmable digital logic device FPGA) produce with tested periodic signal, there is adopting of certain tiny frequency deviation
Sample clock.But on the one hand, owing to actual phase-locked loop circuit cannot at random produce the clock of certain precise frequency, i.e. cannot make
Sampling clock arbitrarily close to tested periodic signal, is said in frequency from this point on, and the raising timestamp that the present embodiment provides is surveyed
The precision that the method for accuracy of measurement can reach is limited by the frequency generative capacity of phase-locked loop circuit.On the other hand, due to time
On Zhong Yuan, holding wire, factor, sampling clock or the measured clock such as interference are constantly present edge trembling (jitter), generally at sub-ns
Magnitude.When sampling clock is the most small with the frequency departure of measured signal, so that the temporal resolution reached can be with clock
During the analogy of edge trembling error, just cannot be continued to improve time precision by the method again.Therefore, the method can reach time
Between precision (resolution) by clock signal matter quantitative limitation.In actual design, this limits this method often and can reach
The principal element of temporal resolution.In general, the temporal resolution limit that the method that the present embodiment provides can be reached by it
System is at more than 1ns.
Fig. 3 illustrates how to utilize ultimate principle, using clk_B at the rising edge in e moment as tested event, with 0.05s
Resolution measure the timestamp of this event.In Fig. 3, the frequency of clk_A be the frequency of 5Hz, clk_B be 4Hz, with clk_A
First rising edge at be time zero.With clk_A, clk_B is sampled, obtain a periodic samples signal samp, it
Cycle is 5 times of the cycle of clk_A, is 4 times of cycle of clk_B.Coarse counter rough counts continuously according to clk_A rising edge
Number, it points out the number in the clk_A cycle comprised in the tested time；Thin enumerator fine also counts according to clk_A rising edge, but
Being reset when each trailing edge of samp, i.e. it is circulated counting with a cycle of samp for length, utilizes thin counting
Device fine can calculate the part less than a clk_A cycle in the tested time.In Fig. 3, clk_A is at the rising edge in c moment
Time tested event (clk_B is at the rising edge in e moment), now coarse counter rough=5 detected, represent 5 clk_A cycles；
Thin enumerator fine=3, represents that the tested event b at clk_A is along 3/4 clk_A cycle afterwards.Comprehensive thickness counting, obtains
Tested incident distance time zero 5.75 clk_A cycles, i.e. 1.15s, this is the timestamp of tested event.
In the example of fig. 3, tested event is the periodic signal clk_B rising edge in the e moment.All have this example feature
Data transmission applications, the situation of the most every " carrying out synchronous transmitting data according to data clock " all can use this method.Such as with
The too MII sublayer interface in network data link layer, MII Sublayer Protocol receives data according to rx_clk and sends out according to tx_clk
Send data, it is simply that can use the method to measure the typical case of precise time stamp.
The key point of the embodiment of the present invention is to use a sampling that there is tiny frequency deviation with tested periodic signal
Clock, then utilizes principle shown in Fig. 2 to realize the segmentation to a clock cycle, thus reaches finer temporal resolution.
The method improving timestamp certainty of measurement that the embodiment of the present invention provides has the advantage that
1) high-resolution；Relative to traditional clock count method, the time can be divided by the method that the embodiment of the present invention provides
Resolution improves decades of times.
2) low cost；The method that the embodiment of the present invention provides can realize, to device performance in common FPGA device
There is no higher requirement.Relative to temporal interpolation method, the embodiment of the present invention can use more cheap device to arrive enough
Certainty of measurement.
3) application is wider；Method described in the embodiment of the present invention is widely used, and all have " according to data clock synchronous transfer
Data " application of feature, the method described in the embodiment of the present invention can be used to measure precise time stamp.
The embodiment of the present invention two provides a kind of device improving timestamp certainty of measurement, sees Fig. 4, including: obtain single
Unit 41, sampling unit the 42, first counting unit the 43, second counting unit 44 and timestamp acquiring unit 45；
Acquiring unit 41, has the sampling clock of predeterminated frequency deviation for acquisition and tested periodic signal；Wherein said
The frequency of tested periodic signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；Example
As, N value can be 2,4,8,16,32,64 or 128.
Sampling unit 42, is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a week
Phase property sampled signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
First counting unit 43, for using coarse counter that from 0, the rising edge of described sampling clock is started continuous counter,
Add up the number in the cycle of the sampling clock comprised in tested event；
Second counting unit 44, for using thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter,
But each trailing edge at described periodic samples signal is reset, this thin enumerator is with one of described periodic samples signal
Cycle is that length is circulated counting, adds up the part in cycle less than a sampling clock in tested event；Thin enumerator
The cycle T that resolution is sampling clock21/N times, i.e. (1/N) * T2；
Timestamp acquiring unit 45, for when certain moment detects tested event, obtains the thick meter corresponding with this moment
Count value n of number device, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain tested
Timestamp [n+m* (1/N)] the * T of event2, wherein, n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
The periodicity of sampling clock, T2Cycle for sampling clock；Wherein, time zero is first rising of described sampling clock
At Yan.
Further, described acquiring unit 41 specifically for:
Utilize the phaselocked loop resource in phase-locked loop circuit or programmable digital logic device FPGA to produce to believe with the tested cycle
Number there is the sampling clock of predeterminated frequency deviation.
The device improving timestamp certainty of measurement that the embodiment of the present invention provides may be used for performing described in above-described embodiment
Improve timestamp certainty of measurement method, it is similar with technique effect that it realizes principle, the most no longer describes in detail.
The third aspect, present invention also offers a kind of device improving timestamp certainty of measurement, sees Fig. 5, including: phase-locked
Loop circuit 51, sampler 52, coarse counter 53, thin enumerator 54 and processor 55；
Wherein, when described phase-locked loop circuit 51 is for obtaining the sampling with tested periodic signal with predeterminated frequency deviation
Clock；The frequency of wherein said tested periodic signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N
For positive integer；Such as, N value can be 2,4,8,16,32,64 or 128.
Described sampler 52 is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a week
Phase property sampled signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
Described coarse counter 53, for the rising edge of described sampling clock is started continuous counter from 0, adds up tested event
In the number in cycle of sampling clock that comprises；
Described thin enumerator 54 is used for the rising edge to described sampling clock and starts continuous counter from 0, but in the described cycle
Each trailing edge of property sampled signal is reset, and is circulated with cycle of described periodic samples signal for length and counts
Number, for adding up the part in the cycle less than a sampling clock in tested event；When the resolution of thin enumerator is for sampling
The cycle T of clock21/N times, i.e. (1/N) * T2；
Described processor, for when certain moment detects tested event, obtains the coarse counter corresponding with this moment
Count value n, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain tested event
Timestamp [n+m* (1/N)] * T2, wherein, the sampling that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
The periodicity of clock, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
The device improving timestamp certainty of measurement that the embodiment of the present invention provides may be used for performing described in above-described embodiment
Improve timestamp certainty of measurement method, it is similar with technique effect that it realizes principle, the most no longer describes in detail.
In describing the invention, it should be noted that term " on ", the orientation of the instruction such as D score or position relationship be base
In orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description rather than instruction or hint
The device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to this
The restriction of invention.Unless otherwise clearly defined and limited, term " is installed ", " being connected ", " connection " should be interpreted broadly, example
As, can be fixing connection, it is also possible to be to removably connect, or be integrally connected；Can be to be mechanically connected, it is also possible to be to be electrically connected
Connect；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, can be the connection of two element internals.For this
For the those of ordinary skill in field, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
Also, it should be noted in this article, the relational terms of such as first and second or the like is used merely to one
Entity or operation separate with another entity or operating space, and not necessarily require or imply between these entities or operation
There is relation or the order of any this reality.And, term " includes ", " comprising " or its any other variant are intended to contain
Comprising of lid nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include that those are wanted
Element, but also include other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that
Including process, method, article or the equipment of described key element there is also other identical element.
Above example is merely to illustrate technical scheme, is not intended to limit；Although with reference to previous embodiment
The present invention is described in detail, it will be understood by those within the art that: it still can be to aforementioned each enforcement
Technical scheme described in example is modified, or wherein portion of techniques feature is carried out equivalent；And these are revised or replace
Change, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. the method improving timestamp certainty of measurement, it is characterised in that including:
Acquisition and tested periodic signal have the sampling clock of predeterminated frequency deviation；The frequency of wherein said tested periodic signal is
f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；
Utilize described sampling clock that described tested periodic signal is sampled, it is thus achieved that a periodic samples signal, this cycle
The cycle T that cycle is described tested periodic signal of property sampled signal1N times；
Use coarse counter that from 0, the rising edge of described sampling clock is started continuous counter, add up adopting of comprising in tested event
The number in the cycle of sample clock；
Use thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter, but at described periodic samples signal
Each trailing edge be reset, this thin enumerator is circulated with cycle of described periodic samples signal for length and counts
Number, adds up the part in cycle less than a sampling clock in tested event, and the resolution of thin enumerator is sampling clock
Cycle T21/N times, i.e. (1/N) * T2；
When tested event being detected in certain moment, obtain count value n of the coarse counter corresponding with this moment, and during with this
Carve count value m of corresponding thin enumerator, and according to described n and described m, obtain timestamp [n+m* (the 1/N)] * of tested event
T2, wherein, the periodicity of the sampling clock that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point, T2For adopting
The cycle of sample clock；Wherein, time zero is at first rising edge of described sampling clock.
Method the most according to claim 1, it is characterised in that it is inclined that described acquisition and tested periodic signal have predeterminated frequency
The sampling clock of difference, including:
Utilize the phaselocked loop resource in phase-locked loop circuit or programmable digital logic device FPGA to produce to have with tested periodic signal
There is the sampling clock of predeterminated frequency deviation.
Method the most according to claim 1, it is characterised in that N value is 2,4,8,16,32,64 or 128.
4. the device improving timestamp certainty of measurement, it is characterised in that including:
Acquiring unit, has the sampling clock of predeterminated frequency deviation for acquisition and tested periodic signal；Wherein said tested week
The frequency of phase signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is positive integer；
Sampling unit, is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a periodicity is adopted
Sample signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
First counting unit, for using coarse counter that from 0, the rising edge of described sampling clock is started continuous counter, adds up quilt
The number in the cycle of the sampling clock comprised in survey event；
Second counting unit, for using thin enumerator that from 0, the rising edge of described sampling clock is started continuous counter, but in institute
The each trailing edge stating periodic samples signal is reset, and this thin enumerator with a cycle of described periodic samples signal is
Length is circulated counting, adds up the part in cycle less than a sampling clock in tested event；The resolution of thin enumerator
Rate is the cycle T of sampling clock21/N times, i.e. (1/N) * T2；
Timestamp acquiring unit, for when certain moment detects tested event, obtains the coarse counter corresponding with this moment
Count value n, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain tested event
Timestamp [n+m* (1/N)] * T2, sampling that wherein n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
The periodicity of clock, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
Device the most according to claim 4, it is characterised in that described acquiring unit specifically for:
Utilize the phaselocked loop resource in phase-locked loop circuit or programmable digital logic device FPGA to produce to have with tested periodic signal
There is the sampling clock of predeterminated frequency deviation.
Device the most according to claim 4, it is characterised in that N value is 2,4,8,16,32,64 or 128.
7. the device improving timestamp certainty of measurement, it is characterised in that including: phase-locked loop circuit, sampler, slightly count
Device, thin enumerator and processor；
Wherein, described phase-locked loop circuit has the sampling clock of predeterminated frequency deviation for acquisition and tested periodic signal；Wherein
The frequency of described tested periodic signal is f1, the frequency of described sampling clock is f2, f2=(1+1/N) * f1, N >=2, N is the most whole
Number；
Described sampler is used for utilizing described sampling clock to sample described tested periodic signal, it is thus achieved that a periodicity is adopted
Sample signal, the cycle of this periodic samples signal is the cycle T of described tested periodic signal1N times；
Described coarse counter, for the rising edge of described sampling clock is started continuous counter from 0, adds up in tested event and comprises
The number in cycle of sampling clock；
Described thin enumerator, for starting continuous counter to the rising edge of described sampling clock from 0, but at described periodic samples
Each trailing edge of signal is reset, and is circulated counting with a cycle of described periodic samples signal for length, is used for
Add up the part in cycle less than a sampling clock in tested event；The cycle that resolution is sampling clock of thin enumerator
T21/N times, i.e. (1/N) * T2；
Described processor, for when certain moment detects tested event, obtains the counting of the coarse counter corresponding with this moment
Value n, and count value m of the thin enumerator corresponding with this moment, and according to described n and described m, obtain the time of tested event
Stamp [n+m* (1/N)] * T2, wherein, the sampling clock that n+m* (1/N) is crossed over by tested event place moment Distance Time zero point
Periodicity, T2Cycle for sampling clock；Wherein, time zero is at first rising edge of described sampling clock.
Device the most according to claim 7, it is characterised in that N value is 2,4,8,16,32,64 or 128.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610787322.4A CN106301656B (en) | 2016-08-30 | 2016-08-30 | A kind of method and device for improving timestamp measurement accuracy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610787322.4A CN106301656B (en) | 2016-08-30 | 2016-08-30 | A kind of method and device for improving timestamp measurement accuracy |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106301656A true CN106301656A (en) | 2017-01-04 |
| CN106301656B CN106301656B (en) | 2018-04-13 |
Family
ID=57673165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610787322.4A Active CN106301656B (en) | 2016-08-30 | 2016-08-30 | A kind of method and device for improving timestamp measurement accuracy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106301656B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108564634A (en) * | 2018-04-03 | 2018-09-21 | 沈阳东软医疗系统有限公司 | A kind of method and device improving time sampling precision |
| CN108924461A (en) * | 2018-06-20 | 2018-11-30 | 斑马网络技术有限公司 | Method of video image processing and device |
| CN108932007A (en) * | 2017-05-25 | 2018-12-04 | 纬颖科技服务股份有限公司 | Method for acquiring time stamp and computer device |
| WO2019144754A1 (en) * | 2018-01-25 | 2019-08-01 | 固高科技(深圳)有限公司 | Signal receiving method |
| CN112994738A (en) * | 2021-05-06 | 2021-06-18 | 成都瀚德科技有限公司 | Small signal detection method based on multi-station cooperation |
| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
| WO2023220939A1 (en) * | 2022-05-17 | 2023-11-23 | 北京小米移动软件有限公司 | Time delay measurement method and apparatus, and device, system, storage medium and chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1729440A1 (en) * | 2005-06-01 | 2006-12-06 | AGILENT TECHNOLOGIES, INC. (A Delaware Corporation) | Determining synchronization error |
| CN102474410A (en) * | 2009-07-24 | 2012-05-23 | 阿尔卡特朗讯公司 | High-precision synchronisation method and system |
| CN102932084A (en) * | 2012-10-17 | 2013-02-13 | 航天科工深圳（集团）有限公司 | Sampling clock synchronizing method and system |
| CN104199276A (en) * | 2014-09-23 | 2014-12-10 | 李亚锋 | FPGA-based (field programmable gate array based) signal time difference measurement method and FPGA-based time-to-digital converter |
-
2016
- 2016-08-30 CN CN201610787322.4A patent/CN106301656B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1729440A1 (en) * | 2005-06-01 | 2006-12-06 | AGILENT TECHNOLOGIES, INC. (A Delaware Corporation) | Determining synchronization error |
| CN102474410A (en) * | 2009-07-24 | 2012-05-23 | 阿尔卡特朗讯公司 | High-precision synchronisation method and system |
| CN102932084A (en) * | 2012-10-17 | 2013-02-13 | 航天科工深圳（集团）有限公司 | Sampling clock synchronizing method and system |
| CN104199276A (en) * | 2014-09-23 | 2014-12-10 | 李亚锋 | FPGA-based (field programmable gate array based) signal time difference measurement method and FPGA-based time-to-digital converter |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108932007A (en) * | 2017-05-25 | 2018-12-04 | 纬颖科技服务股份有限公司 | Method for acquiring time stamp and computer device |
| CN108932007B (en) * | 2017-05-25 | 2021-05-11 | 纬颖科技服务股份有限公司 | Method for acquiring time stamp and computer device |
| WO2019144754A1 (en) * | 2018-01-25 | 2019-08-01 | 固高科技(深圳)有限公司 | Signal receiving method |
| CN108564634A (en) * | 2018-04-03 | 2018-09-21 | 沈阳东软医疗系统有限公司 | A kind of method and device improving time sampling precision |
| CN108564634B (en) * | 2018-04-03 | 2021-10-15 | 东软医疗系统股份有限公司 | Method and device for improving time sampling precision |
| CN108924461A (en) * | 2018-06-20 | 2018-11-30 | 斑马网络技术有限公司 | Method of video image processing and device |
| CN108924461B (en) * | 2018-06-20 | 2021-08-13 | 斑马网络技术有限公司 | Video image processing method and device |
| CN112994738A (en) * | 2021-05-06 | 2021-06-18 | 成都瀚德科技有限公司 | Small signal detection method based on multi-station cooperation |
| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
| CN114019857B (en) * | 2021-10-28 | 2024-03-22 | 华中师范大学 | High-precision phase adjustment and measurement system and method based on phase interpolation |
| WO2023220939A1 (en) * | 2022-05-17 | 2023-11-23 | 北京小米移动软件有限公司 | Time delay measurement method and apparatus, and device, system, storage medium and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106301656B (en) | 2018-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106301656B (en) | A kind of method and device for improving timestamp measurement accuracy | |
| CN104485947B (en) | A kind of digital phase discriminator that crystal oscillator is tamed for GPS | |
| CN110442012A (en) | A kind of precision time interval measurement method and system based on FPGA | |
| CN105549379A (en) | Synchronous measurement apparatus based on high precision time reference triggering and method thereof | |
| TW202042521A (en) | Phase predictor and associated method of use | |
| CN101388741A (en) | Highly precised time synchronization device, system and method for computer network | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN2736821Y (en) | Programmable logic device based short time interval meter | |
| CN110445493A (en) | A kind of data collection synchronous device and method based on FPGA TDC | |
| CN105245203B (en) | High-precision low-speed clock duty ratio detecting system and method | |
| CN103248356A (en) | Counter based on phase-lock loop pulse interpolation technology and realization method | |
| CN103941622A (en) | Method for adopting high-accuracy pulse per second frequency multiplication to produce sampling pulse based on FPGA | |
| CN106302014A (en) | The signal measurement method of wide-range high-precision | |
| CN109709393A (en) | Device based on stability of frequency of time domain signal measurement | |
| CN106597097A (en) | High-precision frequency measurement method | |
| CN108736885A (en) | The clock phase-splitting method of phase-locked loop clock edging trigger | |
| CN102664701A (en) | System and method for dynamically adjusting multichannel and wide-range clock transmission delay | |
| US8294501B1 (en) | Multiphase clock generation and calibration | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| US20090198467A1 (en) | Measuring Clock Jitter | |
| CN207123716U (en) | A kind of pulse signal time difference measuring device | |
| CN113391333B (en) | Beidou high-precision time synchronization chip based on different-frequency group quantization phase processing | |
| CN108768388A (en) | The clock phase-splitting method that phaselocked loop clock edge of connecting triggers | |
| CN108732912A (en) | The clock phase-splitting method of measured signal edging trigger | |
| CN203950131U (en) | A kind of high precision time interval measurement device based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Yang Zhenhua Inventor after: Cao Xinjun Inventor after: Mu Baixin Inventor after: Xu Tongye Inventor before: Yang Zhenhua Inventor before: Cao Xinjun Inventor before: Chen Hongshun Inventor before: Xu Tongye |