CN106301356B - A kind of orthogonal signalling phase error correction device and method - Google Patents
A kind of orthogonal signalling phase error correction device and method Download PDFInfo
- Publication number
- CN106301356B CN106301356B CN201510259855.0A CN201510259855A CN106301356B CN 106301356 B CN106301356 B CN 106301356B CN 201510259855 A CN201510259855 A CN 201510259855A CN 106301356 B CN106301356 B CN 106301356B
- Authority
- CN
- China
- Prior art keywords
- signal
- phase error
- orthogonal signalling
- multichannel
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Particle Accelerators (AREA)
Abstract
The present invention provides a kind of orthogonal signalling phase error correction device and method.The orthogonal signalling phase error correction device includes: multipath delay module, corresponds progress delay disposal, signal after output multi-channel delay to multichannel input signal for controlling signal according to multipath delay；Quadrature phase generation module is connected with multipath delay module, for carrying out orthogonal processing, output multi-channel orthogonal signalling to signal after received multipath delay；Phase error detection module is connected with quadrature phase generation module, carries out phase error judgement for receiving multichannel orthogonal signalling, and to the two-way orthogonal signalling of arbitrary neighborhood, output multi-channel phase error judges signal；State machine module is connected with phase error detection module and multipath delay module, judges signal for receiving phase error described in multichannel, feedback generates multipath delay control signal further to correct multichannel input signal.Technical solution of the present invention can correct the phase error of leggy orthogonal signalling generator introducing.
Description
Technical field
The present invention relates to a kind of electronic technology, more particularly to a kind of orthogonal signalling phase error correction device and method.
Background technique
It is zero that orthogonal signalling group, which refers in the signal of the road N that any two paths of signals integrates in one cycle,.Extremely due to the road N signal
N number of driving and N number of physical connection and N number of load, the difference of each branch device mismatch and line parasitism and driving capability are corresponded to less
It is different, can the road N orthogonal signalling be brought with the mismatch in phase or amplitude.For the mismatch of the amplitude and phase of orthogonal signalling, pass
System method first is that the component size of orthogonal signalling generative circuit is done greatly, to reduce component bring mismatch, want simultaneously
It asks physics cabling symmetrical as far as possible and matching, keeps ghost effect identical as far as possible.But this power consumption and area for will will increase in circuit；Especially
It is for high frequency orthogonal signalling, and such as WIFI local oscillation signal, this method cannot substantially make phase error reach design object.It passes
System method second is that going sampling per signal all the way using a N frequency-doubled signal, to reduce or eliminate the phase between multi-phase signals
Position error.But the disadvantage is that need a high-frequency signal, while the mismatch between each sample circuit (such as D- trigger) be cannot
It eliminates.
In consideration of it, how to design the phase error correction circuit of better orthogonal signalling just becomes those skilled in the art
Member's urgent problem to be solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of orthogonal signalling phase error schools
Equipment and method, for solving the mismatch problems of the amplitude and phase of orthogonal signalling in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of orthogonal signalling phase error correction device,
The orthogonal signalling phase error correction device includes: multipath delay module, for controlling signal to multichannel according to multipath delay
Input signal, which corresponds, carries out delay disposal, signal after output multi-channel delay；Quadrature phase generation module prolongs with the multichannel
Slow module is connected, for carrying out orthogonal processing, output multi-channel orthogonal signalling to signal after the received multipath delay；Phase is missed
Poor detection module is connected with the quadrature phase generation module, for receiving the multichannel orthogonal signalling, and to arbitrary neighborhood
Two-way orthogonal signalling carry out phase error judgement, and output multi-channel phase error judges signal；State machine module is missed with the phase
Poor detection module and the multipath delay module are connected, and judge signal for receiving phase error described in multichannel, feedback generates
Multipath delay control signal is output to multipath delay module further to correct multichannel input signal.
Optionally, the quadrature phase generation module is also connected with load blocks, and the quadrature phase generation module is by institute
It states multichannel orthogonal signalling and is output to the load blocks.
Optionally, the quadrature phase generation module includes multiple phase demodulation units being made of phase inverter and logic gate, often
A phase demodulation unit receives signal after adjacent two-way delay, exports orthogonal signalling all the way.
Optionally, the phase error detection module controls signal according to selection for receiving the multichannel orthogonal signalling
Adjacent two-way orthogonal signalling are selected, and phase error judgement, output phase error judgement are carried out to the two-way orthogonal signalling
Signal；State machine module, the selection for sequentially generating the phase error detection module controls signal, and receives corresponding
Phase error judge signal, judge that signal is generated according to the phase error and control the corresponding institute all the way of signal with the selection
Delayed control signal is stated, so that sequence generates delayed control signal described in multichannel.
Optionally, the multipath delay module includes multiple delay cells, and the multiple delay cell is to corresponding
Delay disposal is carried out per input signal all the way, the delay cell can individually be controlled by the state machine module.
Optionally, multipath delay module delayed control signal according to multichannel controls the multiple delay cell,
Cyclically reduce the phase error of the adjacent phase signal of any two to zero or minimum value.
Optionally, the phase error detection module includes multiple groups filter, a signal selector and a comparison
Device；The filter is for being filtered the orthogonal signalling；The signal selector is used for according to selection control letter
Number adjacent two-way orthogonal signalling of selection；The comparator is exported for handling the adjacent two-way orthogonal signalling
Phase error judges signal.
Optionally, the phase error detection module includes the filtering for being filtered to the orthogonal signalling
Device, the filter include single order RC low-pass filter.
Optionally, the orthogonal signalling phase error correction device receives 4 tunnel input signals, exports 4 tunnel orthogonal signalling.
The present invention also provides a kind of orthogonal signalling phase error correction approach, the orthogonal signalling phase error correction approach
It include: to control signal according to multipath delay and carry out delay disposal to multichannel input signal to obtain signal after multipath delay；According to institute
Signal carries out orthogonal processing generation multichannel orthogonal signalling after stating multipath delay；To all phase phases in the multichannel orthogonal signalling
Adjacent two-way orthogonal signalling carry out phase error judgement, generate multichannel phase error and judge signal；Judged according to multichannel phase error
Signal feedback generates delayed control signal described in multichannel further to correct the multichannel input signal.
Optionally, the specific implementation that signal generates multichannel orthogonal signalling after the multipath delay includes: according to multipath delay
Signal generates multichannel orthogonal signalling after the adjacent two-way delay of multiple groups afterwards in signal；Wherein, by identifying any group of phase
The phase difference of signal, generates orthogonal signalling all the way after adjacent two-way delay.
Optionally, judge that signal generates the specific implementation packet of delayed control signal described in multichannel according to multichannel phase error
It includes: generating multiple groups selection control signal to be sequentially generated multipath delay control signal；Wherein, it is generated per delayed control signal all the way
Specific implementation include: described in selected one group selection control signal generate one group of phase error judge signal, according to generated
Phase error judges that signal and selected selection control signal generate delayed control signal all the way.
Optionally, the specific implementation packet of the multichannel input signal is further corrected according to the delayed control signal
It includes: the phase error of the adjacent phase signal of any two is cyclically reduced to zero or minimum according to the delayed control signal
Value.
Optionally, the orthogonal signalling phase error correction approach further include: the multichannel orthogonal signalling are filtered
Processing.
As described above, a kind of orthogonal signalling phase error correction device and method of the invention, has the advantages that
Under the negative-feedback characteristic effect of loop, the phase error of the adjacent phase signal of any two will adjust most zero by circulation
Or minimum value.After loop stability, the phase error of the road the N orthogonal signalling of final output reaches minimum.
Detailed description of the invention
Fig. 1 is shown as the module diagram of an embodiment of orthogonal signalling phase error correction device of the invention.
Fig. 2 is shown as the module diagram of an embodiment of orthogonal signalling phase error correction device of the invention.
Fig. 3 is shown as the electrical block diagram of an embodiment of orthogonal signalling phase error correction device of the invention.
Fig. 4 is shown as the work of the state machine module of an embodiment of orthogonal signalling phase error correction device of the invention
Flow diagram.
Fig. 5 is shown as the flow diagram of an embodiment of orthogonal signalling phase error correction approach of the invention.
Component label instructions
1 orthogonal signalling phase error correction system
11 multipath delay modules
12 quadrature phase generation modules
13 phase error detection modules
14 state machine modules
S1~S4 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It should be noted that the basic conception that only the invention is illustrated in a schematic way is illustrated provided in the present embodiment,
Then only shown in schema with it is of the invention in related component rather than component count, shape and size when according to actual implementation draw
System, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel can also
It can be increasingly complex.
The present invention provides a kind of orthogonal signalling phase error correction device.In one embodiment, as shown in Figure 1, it is described
Orthogonal signalling phase error correction device 1 includes multipath delay module 11, quadrature phase generation module 12, phase error detection mould
Block 13 and state machine module 14.Wherein:
Multipath delay module 11, which is used to control signal according to multipath delay, postpones multichannel input signal one-to-one correspondence
Processing, signal after output multi-channel delay.The multichannel be the road N, N >=3, i.e. multichannel is at least three tunnels.In one embodiment,
The multipath delay module includes multiple delay cells, the multiple delay cell to it is corresponding per input signal all the way into
Row delay disposal, the delay cell can individually be controlled by the state machine module.The multipath delay module is according to multichannel
The delayed control signal controls the multiple delay cell, and the phase for cyclically reducing the adjacent phase signal of any two is missed
Difference is to zero or minimum value.
Quadrature phase generation module 12 is connected with the multipath delay module 11, for receiving signal after the multipath delay
Carry out orthogonal processing, output multi-channel orthogonal signalling.In one embodiment, the quadrature phase generation module 12 include it is multiple by
The phase demodulation unit that phase inverter and logic gate are constituted, each phase demodulation unit receive signal after adjacent two-way delay, output one
Road orthogonal signalling.Phase demodulation refers to the difference for identifying input signal；Phase demodulation unit refers to identify the difference of input signal
Device cell.In one embodiment, the quadrature phase generation module 12 is also connected with load blocks, and the quadrature phase is raw
The multichannel orthogonal signalling are output to the load blocks at module 12, the load blocks may include frequency mixer or frequency multiplication
Device etc..Preferably, the multichannel orthogonal signalling are output to the load blocks after buffering driver drives.After the delay of the road N
The total N group of signal after the adjacent two-way delay of control signal, such as when N is 4, have signal after the delay of the road [0:3], wherein phase
Totally four groups of signal, respectively [0] and [1] after adjacent two-way delay, [1] and [2], [2] and [3], [3] and [0].
Phase error detection module 13 is connected with the quadrature phase generation module 12, for receiving the orthogonal letter of the multichannel
Number, and phase error judgement is carried out to the two-way orthogonal signalling of arbitrary neighborhood, output multi-channel phase error judges signal.Specifically
Ground, the total N group of adjacent two-way orthogonal signalling of the road N orthogonal signalling, such as when N is 4, there is the road [0:3] orthogonal signalling, wherein
Totally four groups adjacent of two-way orthogonal signalling (referring to the adjacent two-way orthogonal signalling of phase), respectively [0] and [1], [1] and [2],
[2] with [3], [3] and [0].
State machine module 14 is connected with the phase error detection module 13 and the multipath delay module 11, for connecing
Receive phase error described in multichannel and judge signal, delayed control signal described in feedback generation multichannel be output to multipath delay module with into
One step corrects the multichannel input signal.By the preset algorithm in state machine module 14, judged according to the phase error
Signal, feedback generates delayed control signal described in multichannel, further to control the digital delay list of each road of input signal
Member, to adjust the delay time per input signal all the way.By the feedback compensation of orthogonal signalling phase error correction device 1,
The multichannel orthogonal signalling (being referred to as quadrature phase) for the output for keeping its final do not have phase error.
In one embodiment, the phase error detection module 13 is for receiving the multichannel orthogonal signalling, according to choosing
The adjacent two-way orthogonal signalling of control signal behavior are selected, and phase error judgement, output phase are carried out to the two-way orthogonal signalling
Position error judgment signal；State machine module 14 is used to sequentially generate the selection control letter of the phase error detection module
Number, and receive and signal is judged by the phase error that phase error detection module 13 generates accordingly, sentenced according to the phase error
Break signal generates the delayed control signal described all the way corresponding with selection control signal, prolongs described in multichannel so that sequence generates
Control signal late.In one embodiment, the phase error detection module 13 includes for filtering to the orthogonal signalling
The filter of wave processing, the filter includes single order RC low-pass filter.
In one embodiment, the phase error detection module 13 include multiple groups filter, a signal selector with
An and comparator；The filter is for being filtered the orthogonal signalling；The signal selector is used for basis
The adjacent two-way orthogonal signalling of selection control signal behavior；The comparator is used to carry out the adjacent two-way orthogonal signalling
Processing, output phase error judge signal.
In one embodiment, as shown in Fig. 2, the orthogonal signalling phase error correction device 1 receives 4 tunnels input letter
Number, export 4 tunnel orthogonal signalling.The orthogonal signalling phase error correction device 1 is the phase error school of four phase quadrature signals
Positive loop, by delay cell array (multipath delay module 11), four phase quadrature signals generator (quadrature phase generation modules
12), driver, phase error detector (phase error detection module 13) and state machine (state machine module 14) composition.Its
Middle delay cell array is made of four identical digital control delay subelements, and the digital controlled signal of four subelements is (i.e.
Delayed control signal) by state machine timesharing independent control.Four phase quadrature signals generators are by four identical phase demodulation unit groups
At the functional schematic of each phase demodulation unit is formed by phase inverter and with logic gate, the phase for the adjacent Two-phases signal of phase demodulation
Potential difference.The multipath output signals of orthogonal signalling generator output enter buffering driver (Buffer), and buffering driver exports OUT
<3:0>(output signal) is used to driving load (such as frequency mixer or frequency multiplier) in practical application, at the same multipath output signals into
Applying aspect error detection circuit.Phase error detection circuit is made of filter, signal selector and comparator three parts.Wherein
The implementation of filter formed including but not limited to four single order RC low-pass filters, filter is by multipath output signals
Output signal mux_in<3:0>amplitude is directly proportional to the duty ratio of OUT<3:0>after filtering, also believes with OUT<3:0>adjacent phase
Phase difference between number is directly proportional.Filter output signal mux_in<3:0>entering signal selector.Selector work is selecting
Two adjacent input signals of circulation selection enter comparator under the action of control signal sel<1:0>.Such as when sel<1:0>is equal to
When<00>, mux_in<0>respectively enters the port vip and vin of comparator, comparator output logic signal with mux_in<1>
When comp (phase error judges signal) is high level " 1 ", indicates that the amplitude of mux_in<0>is higher than mux_in<1>, also illustrate that
Duty ratio ratio OUT<1>duty ratio of OUT<0>is big, in other words the phase difference ratio OUT<1>between OUT<0>and OUT<1>and OUT<
2 > between phase difference it is big.So the comp signal of comparator output enters state machine, pass through the output cc2 (delay of state machine
Control signal 2) control delay cell array in a delay cell, i.e., reduction In<1>branch delay time until
There is low level " 0 " in COMP, so that the duty ratio of OUT<0>is equal with OUT<1>duty ratio.Conversely, when sel<1:0>is equal to<00
>when, when comparator output logic signal comp is low level " 0 ", then increase the delay time one of In<1>branch by state machine
Make the duty ratio of OUT<0>equal with OUT<1>duty ratio until high level " 1 " occurs in COMP.When sel<1:0>is equal to<00>
When, state machine adjusts the delay cell of In<0>branch road in multichannel input signal In<3:0>, so that the duty ratio of OUT<0>
After equal with OUT<1>duty ratio；When sel<1:0>is arranged equal to<01>in state machine, phase error detector detects mux_in<1>
With mux_in<2>, the delay cell of the road of In<1>is then adjusted according to the result of comparator, so that the duty ratio of OUT<1>
It is equal with OUT<2>duty ratio.And so on, state machine will recycle the delay time for adjusting each branch, so that final is defeated
The duty ratio of signal OUT<3:0>is equal out, at this point, the phase difference between output signal OUT<3:0>is also equal, thus
Achieve the purpose that phase error correction.In another embodiment, the circuit knot of the orthogonal signalling phase error correction device 1
Structure is as shown in Figure 3.In the embodiment, input terminal receives 8 signal in<7:0>, processing of circuit of the in<7:0>Jing Guo delay cell
Del<7:0>is exported afterwards, after the processing of leggy phase discriminator and driving, final output end exports 8 signal out<7:0>.
Out<7:0>is output in load, while being handled by phase error detection circuit and state machine, is generated and is postponed described in multichannel
Control signal feedback control delay cell.It is finally reached the purpose of phase error correction.
In one embodiment, the specific workflow of the state machine module 14 is as shown in Figure 4.Phase in the embodiment
The filter of error detection circuit exports 4 signal mux_in<0-3>.Its workflow is as follows: cc0 is initialized when beginning,
Cc1, cc2, cc3.Cc0, cc1, cc2, cc3 are respectively used to corresponding to 4 signal mux_in<0>, mux_in<1>, mux_in<2
>, the delayed control signal for the delay cell to input signal that mux_in<3>processing generates.According to selection control signal Sel <
The adjacent two-way output signal of 1:0 > selection (by the orthogonal signalling of filtering processing) is input to comparator, and defeated to the two-way
Signal carries out phase error judgement out, and output phase error judges signal；Signal Comp is judged according to the phase error,
The value of comp_last controls signal Sel<1:0>corresponding one with the selection to generate and (be included on the basis of initial value and change)
Delayed control signal described in road.When the selection controls signal Sel<1:0>=<00>, adjacent two-way output signal is selected
(by the orthogonal signalling of filtering processing) mux_in<0>and mux_in<1>are input to comparator, corresponding to generate described all the way prolong
The value of control signal cc1 late.Work as Comp, when<11>comp_last=, cc1 subtracts 1；Work as Comp, when<11>comp_last=,
Cc1 subtracts 1；Work as Comp, when<00>comp_last=, cc1 adds 1；Work as Comp, comp_last=<10>or when<01>, cc1 is saved
It is constant.Similarly, cc1, cc2, cc3 are controlled.When the selection controls signal Sel<1:0>=<01>, select adjacent
Two-way output signal (by the orthogonal signalling of filtering processing) mux_in<1>and mux_in<2>be input to comparator, accordingly
Generate the value of the delayed control signal cc2 all the way.When the selection controls signal Sel<1:0>=<10>, select adjacent
Two-way output signal (by the orthogonal signalling of filtering processing) mux_in<2>and mux_in<3>is input to comparator, corresponding to produce
The value of the raw delayed control signal cc3 described all the way.When the selection controls signal Sel<1:0>=<11>, adjacent two are selected
Output signal (by the orthogonal signalling of filtering processing) mux_in<3>and mux_in<0>in road is input to comparator, corresponding to generate
The value of the delayed control signal cc0 all the way.In the present embodiment, the state machine module 14 further includes a control switch
Stop, as control switch stop=1, state machine terminates to above-mentioned workflow.
The present invention also provides a kind of orthogonal signalling phase error correction approach.As shown in figure 5, the orthogonal signalling phase is missed
Difference correcting method includes:
Step S1 controls signal according to multipath delay and believe after delay disposal obtains multipath delay to multichannel input signal
Number.
Step S2 carries out orthogonal processing to signal after the multipath delay and generates multichannel orthogonal signalling.In one embodiment
In, the specific implementation that signal generates multichannel orthogonal signalling after the multipath delay includes: according to more in signal after multipath delay
Signal generates multichannel orthogonal signalling after the adjacent two-way delay of group；Wherein, postponed by identifying described any group adjacent two-way
The phase difference of signal afterwards generates orthogonal signalling all the way.
Step S3 carries out phase error to the adjacent two-way orthogonal signalling of all phases in the multichannel orthogonal signalling and sentences
It is disconnected, it generates multichannel phase error and judges signal.
Step S4 judges that signal feedback generates delayed control signal described in multichannel with further school according to multichannel phase error
The just described multichannel input signal.By preset algorithm, judge that signal feedback generates control delay control according to multichannel phase error
Signal processed, to control the digital delay elements of each road of input signal, thus when adjusting per the delay of input signal all the way
Between, the multichannel orthogonal signalling (being referred to as quadrature phase) for the output for keeping its final do not have phase error.According to the delay
Control signal with the specific implementation for further correcting the multichannel input signal include: according to the delayed control signal cyclically
Reduce the phase error of the adjacent phase signal of any two to zero or minimum value.
In one embodiment, judge that signal generates the specific of delayed control signal described in multichannel according to multichannel phase error
Realization includes: to generate multiple groups selection control signal to be sequentially generated multipath delay control signal；Wherein, per delay control letter all the way
Number generate specific implementation include: described in selected one group selection control signal generate one group of phase error judge signal, according to institute
The phase error of generation judges that signal and selected selection control signal generate delayed control signal all the way.
In one embodiment, the orthogonal signalling phase error correction approach further include: to the multichannel orthogonal signalling
It is filtered.Specifically, to the multichannel orthogonal signalling before the multichannel orthogonal signalling are carried out with phase error judgement
It is filtered.
Technical solution of the present invention can be applied to general quadrature phase generative circuit, frequency synthesizer, frequency mixer, times
In the circuits such as frequency device, quasi-sine-wave generator.
In conclusion a kind of orthogonal signalling phase error correction device and method of the invention, has the advantages that
Under the negative-feedback characteristic effect of loop, the phase error of the adjacent phase signal of any two will adjust most zero by circulation
Or minimum value.After loop stability, the phase error of the road the N orthogonal signalling of final output reaches minimum.The present invention can make leggy
The phase error of the introducings such as input signal, each finger delays unit and quadrature phase generator can be corrected；The technology
Matching is required to substantially reduce in physics realization or laying out pattern cabling；The mismatch between each component can be tolerated simultaneously,
Convenient for circuit flexible design.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (14)
1. a kind of orthogonal signalling phase error correction device, which is characterized in that the orthogonal signalling phase error correction device packet
It includes:
Multipath delay module corresponds progress delay disposal to multichannel input signal for controlling signal according to multipath delay,
Signal after output multi-channel delay；
Quadrature phase generation module is connected with the multipath delay module, for signal after the received multipath delay into
Row orthogonal processing, output multi-channel orthogonal signalling；
Phase error detection module is connected with the quadrature phase generation module, for receiving the multichannel orthogonal signalling, and it is right
The two-way orthogonal signalling of arbitrary neighborhood carry out phase error judgement, and output multi-channel phase error judges signal；
State machine module is connected with the phase error detection module and the multipath delay module, for receiving multichannel institute
It states phase error and judges signal, feedback generates multipath delay control signal and exports to multichannel Postponement module further to correct multichannel
Input signal.
2. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the quadrature phase generates
Module is also connected with load blocks, and the multichannel orthogonal signalling are output to the load mould by the quadrature phase generation module
Block.
3. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the quadrature phase generates
Module includes multiple phase demodulation units being made of phase inverter and logic gate, and each phase demodulation unit receives adjacent two-way delay
Signal afterwards exports orthogonal signalling all the way.
4. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the phase error detection
Module is for receiving the multichannel orthogonal signalling, according to the adjacent two-way orthogonal signalling of selection control signal behavior, and to described
Two-way orthogonal signalling carry out phase error judgement, and output phase error judges signal；State machine module, for described in sequence generation
The selection of phase error detection module controls signal, and receives corresponding phase error and judge signal, according to the phase
Error judgment signal generates the delayed control signal described all the way corresponding with selection control signal, so that sequence generates multichannel
The delayed control signal.
5. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the multipath delay module
Including multiple delay cells, the multiple delay cell carries out delay disposal per input signal all the way to corresponding, described
Delay cell can individually be controlled by the state machine module.
6. orthogonal signalling phase error correction device according to claim 5, it is characterised in that: the multipath delay module
The delayed control signal according to multichannel controls the multiple delay cell, cyclically reduces the adjacent phase signal of any two
Phase error to zero or minimum value.
7. orthogonal signalling phase error correction device according to claim 4, it is characterised in that: the phase error detection
Module includes multiple groups filter, a signal selector and a comparator；The filter is used for the orthogonal signalling
It is filtered；The signal selector is used for the two-way orthogonal signalling adjacent according to selection control signal behavior；The ratio
Compared with device for handling the adjacent two-way orthogonal signalling, output phase error judges signal.
8. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the phase error detection
Module includes the filter for being filtered to the orthogonal signalling, and the filter includes single order RC low-pass filtering
Device.
9. orthogonal signalling phase error correction device according to claim 1, it is characterised in that: the orthogonal signalling phase
Error correction device receives 4 tunnel input signals, exports 4 tunnel orthogonal signalling.
10. a kind of orthogonal signalling phase error correction approach, it is characterised in that: the orthogonal signalling phase error correction approach packet
It includes:
Signal is controlled according to multipath delay delay disposal is carried out to multichannel input signal obtain signal after multipath delay；
Orthogonal processing is carried out to signal after the multipath delay and generates multichannel orthogonal signalling；
Phase error judgement is carried out to the adjacent two-way orthogonal signalling of all phases in the multichannel orthogonal signalling, generates multichannel phase
Position error judgment signal；
Judge that signal feedback generates delayed control signal described in multichannel further to correct the multichannel according to multichannel phase error
Input signal.
11. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: after the multipath delay
The specific implementation that signal generates multichannel orthogonal signalling includes: according to after the adjacent two-way delay of the multiple groups after multipath delay in signal
Signal generates multichannel orthogonal signalling；Wherein, it by the phase difference of signal after described any group of identification adjacent two-way delay, generates
Orthogonal signalling all the way.
12. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: missed according to multichannel phase
The specific implementation that difference judges that signal generates delayed control signal described in multichannel includes: to generate multiple groups selection control signal with sequentially raw
Signal is controlled at multipath delay；It wherein, include: selection described in selected one group per the specific implementation that delayed control signal all the way generates
Control signal generates one group of phase error and judges signal, judges signal and selected selection according to phase error generated
It controls signal and generates delayed control signal all the way.
13. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: controlled according to the delay
Signal processed includes: cyclically to be subtracted according to the delayed control signal with the specific implementation for further correcting the multichannel input signal
The phase error of the adjacent phase signal of small any two is to zero or minimum value.
14. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: the orthogonal signalling phase
Position error calibration method further include: the multichannel orthogonal signalling are filtered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510259855.0A CN106301356B (en) | 2015-05-20 | 2015-05-20 | A kind of orthogonal signalling phase error correction device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510259855.0A CN106301356B (en) | 2015-05-20 | 2015-05-20 | A kind of orthogonal signalling phase error correction device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106301356A CN106301356A (en) | 2017-01-04 |
| CN106301356B true CN106301356B (en) | 2019-04-16 |
Family
ID=57634204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510259855.0A Active CN106301356B (en) | 2015-05-20 | 2015-05-20 | A kind of orthogonal signalling phase error correction device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106301356B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899290A (en) * | 2017-02-16 | 2017-06-27 | 电子科技大学 | A kind of high accuracy multi-phase clock correcting circuit |
| US10841072B2 (en) * | 2018-12-05 | 2020-11-17 | Samsung Electronics Co., Ltd. | System and method for providing fast-settling quadrature detection and correction |
| CN113114227B (en) * | 2019-12-25 | 2023-07-18 | 澜至电子科技（成都）有限公司 | Multi-phase clock signal phase difference detection circuit and method and digital phase modulation system |
| CN117353748A (en) * | 2023-09-28 | 2024-01-05 | 深圳市鼎阳科技股份有限公司 | Delay correction method and related equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614878A (en) * | 2004-12-10 | 2005-05-11 | 清华大学 | Locking-phase loop style orthogonal signal phase calibrator |
| CN101729468A (en) * | 2008-10-27 | 2010-06-09 | 夏普株式会社 | IQ mismatch correction circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
-
2015
- 2015-05-20 CN CN201510259855.0A patent/CN106301356B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614878A (en) * | 2004-12-10 | 2005-05-11 | 清华大学 | Locking-phase loop style orthogonal signal phase calibrator |
| CN101729468A (en) * | 2008-10-27 | 2010-06-09 | 夏普株式会社 | IQ mismatch correction circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106301356A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106301356B (en) | A kind of orthogonal signalling phase error correction device and method | |
| CN103607183B (en) | A kind of multi-channel separation function signal generator and signal generating method | |
| EP3537610A2 (en) | Hybrid half/quarter-rate decision feedback equalizer and display including hybrid half/quarter-rate decision feedback equalizer | |
| WO2015034624A1 (en) | Method for testing data packet signal transceiver using interleaved device setup and testing | |
| CN108919105B (en) | Microwave mechanical switch repeatability test method | |
| TW202312673A (en) | Clock and data recovery for multi-phase, multi-level encoding | |
| CN105007063B (en) | A kind of space symmetr type high-voltage nanosecond pulse source based on Marx circuits | |
| CN106452400B (en) | Radio-frequency switch circuit | |
| CN103366214A (en) | Power supply control circuit and power supply control method | |
| KR101923012B1 (en) | High-Speed Programmable Clock Divider | |
| EP3907669A1 (en) | Selective frequency shifting of qubits | |
| CN212460415U (en) | Digital test circuit and digital integrated circuit test system of multi-clock domain | |
| US8970312B2 (en) | Differential ring oscillation circuit, device, and oscillation control method | |
| CN104125179B (en) | A kind of multi signal receiving and processing device and its working method based on FPGA | |
| CN105161062A (en) | Liquid crystal display panel | |
| CN109417361A (en) | The sending device of the current signal of photovoltaic group string | |
| CN103684362B (en) | Multiphase clock frequency eliminator | |
| CN204578499U (en) | Phase interpolator | |
| CN110830009B (en) | Control device and method for multi-path DC/DC converter | |
| CN103546164A (en) | Signal collecting device and working method thereof | |
| CN103267943B (en) | A kind of test device and method of integrated circuit | |
| CN106685412B (en) | Frequency divider, frequency divider system and scaling down processing method | |
| CN203278775U (en) | Programmable non-overlapping clock generation circuit | |
| CN104579318A (en) | Multichannel clock buffer | |
| US8607108B2 (en) | Scan testing with capture clock generator driven by clock distribution network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: A6, No. 900 Yishan Road, Xuhui District, Shanghai, 2003 Applicant after: Lanqi Technology Co., Ltd. Address before: Room A1601, 900 Yishan Road, Xuhui District, Shanghai, 2003 Applicant before: Acrospeed, Inc. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |