CN106301356A - A kind of orthogonal signalling phase error correction device and method - Google Patents
A kind of orthogonal signalling phase error correction device and method Download PDFInfo
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Abstract
The present invention provides a kind of orthogonal signalling phase error correction device and method.Described orthogonal signalling phase error correction device includes: multipath delay module, for multichannel input signal one_to_one corresponding being carried out delay disposal according to multipath delay control signal, output multi-channel postpone after signal；Quadrature phase generation module, is connected with multipath delay module, for signal after the multipath delay received is carried out orthogonal processing, output multi-channel orthogonal signalling；Phase error detection module, is connected with quadrature phase generation module, is used for receiving multichannel orthogonal signalling, and the two-way orthogonal signalling of arbitrary neighborhood are carried out phase error judgement, and output multi-channel phase error judges signal；State machine module, is connected with phase error detection module and multipath delay module, is used for receiving phase error described in multichannel and judges that signal, feedback generate multipath delay control signal with correction multichannel input signal further.Technical scheme can correct the phase error that leggy orthogonal signalling maker introduces.
Description
Technical field
The present invention relates to a kind of electronic technology, particularly relate to a kind of orthogonal signalling phase error correction device and method.
Background technology
Orthogonal signalling group refers to that in the signal of N road, any two paths of signals is divided into zero a cycle inner product.Owing to N road signal is the most right
Answer N number of driving and N number of physical connection and N number of load, each branch road device mismatch and line parasitic and the difference of driving force,
All N road orthogonal signalling can be brought the mismatch in phase place or amplitude.Amplitude and the mismatch of phase place, tradition side for orthogonal signalling
One of method is to do greatly by the component size of orthogonal signalling generative circuit, to reduce the mismatch that components and parts bring, requires physics simultaneously
Cabling is the most symmetrical and mates, and makes ghost effect the most identical.But this will increase the power consumption in circuit and area；Particularly with
High frequency orthogonal signalling, such as WIFI local oscillation signal, this method substantially can not make phase error reach design object.Tradition side
The two of method are to utilize a N frequency-doubled signal to remove each road signal of sampling, with the phase error being reduced or eliminated between multi-phase signals.
But shortcoming is to need a high-frequency signal, and the mismatch between each sample circuit (such as D-trigger) is indelible simultaneously.
In consideration of it, the phase error correction circuit how designing more preferable orthogonal signalling just becomes those skilled in the art urgently
The problem solved.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of orthogonal signalling phase error correction device
And method, for solving the amplitude of orthogonal signalling in prior art and the mismatch problems of phase place.
For achieving the above object and other relevant purposes, the present invention provides a kind of orthogonal signalling phase error correction device, described just
Hand over signal phase error correcting unit to include: multipath delay module, be used for according to multipath delay control signal multichannel input signal
One_to_one corresponding carries out delay disposal, signal after output multi-channel delay；Quadrature phase generation module, with described multipath delay module phase
Even, for signal after the described multipath delay received is carried out orthogonal processing, output multi-channel orthogonal signalling；Phase error detection mould
Block, is connected with described quadrature phase generation module, is used for receiving described multichannel orthogonal signalling, and orthogonal to the two-way of arbitrary neighborhood
Signal carries out phase error judgement, and output multi-channel phase error judges signal；State machine module, with described phase error detection mould
Block and described multipath delay module are connected, and are used for receiving phase error described in multichannel and judge that signal, feedback generate multipath delay control
Signal processed exports multipath delay module with correction multichannel input signal further.
Alternatively, described quadrature phase generation module is also connected with load blocks, and described quadrature phase generation module is by described multichannel
Orthogonal signalling export described load blocks.
Alternatively, described quadrature phase generation module includes multiple phase demodulation unit being made up of phase inverter and gate, each described
Phase demodulation unit receives signal after adjacent two-way postpones, and exports road orthogonal signalling.
Alternatively, described phase error detection module is used for receiving described multichannel orthogonal signalling, selects phase according to selecting control signal
Adjacent two-way orthogonal signalling, and described two-way orthogonal signalling are carried out phase error judgement, output phase error judges signal；Shape
State machine module, for sequentially producing the described selection control signal of described phase error detection module, and receives corresponding phase place by mistake
Difference judges signal, judges signal to produce described in a road corresponding with described selection control signal according to described phase error and postpones to control
Signal, thus order produces delayed control signal described in multichannel.
Alternatively, described multipath delay module includes multiple delay cell, and the plurality of delay cell is to corresponding each road
Input signal carries out delay disposal, and described delay cell individually can be controlled by described state machine module.
Alternatively, described multipath delay module controls the plurality of delay cell according to delayed control signal described in multichannel, cyclically
Reduce the phase error of the adjacent phase signal of any two to zero or minima.
Alternatively, described phase error detection module includes organizing wave filter, a signal selector and a comparator more；Institute
State wave filter for described orthogonal signalling being filtered process；Described signal selector is for according to selecting control signal to select phase
Adjacent two-way orthogonal signalling；Described comparator is for processing described adjacent two-way orthogonal signalling, and output phase error is sentenced
Break signal.
Alternatively, described phase error detection module includes for described orthogonal signalling are filtered the wave filter processed, described
Wave filter includes single order RC low pass filter.
Alternatively, described orthogonal signalling phase error correction device receives 4 tunnel input signals, exports 4 tunnel orthogonal signalling.
The present invention also provides for a kind of orthogonal signalling phase error correction approach, and described orthogonal signalling phase error correction approach includes:
According to multipath delay control signal, multichannel input signal carried out delay disposal and obtain signal after multipath delay；Prolong according to described multichannel
The signal that lags carries out orthogonal processing and generates multichannel orthogonal signalling；Orthogonal to the adjacent two-way of all phase places in described multichannel orthogonal signalling
Signal carries out phase error judgement, generates multichannel phase error and judges signal；Judge that signal feedback generates according to multichannel phase error
Delayed control signal described in multichannel is to correct described multichannel input signal further.
Alternatively, after described multipath delay, implementing of multichannel orthogonal signalling of signal generation includes: according to signal after multipath delay
In many groups of adjacent two-way postpone after signal generate multichannel orthogonal signalling；Wherein, by differentiating described arbitrary group of adjacent two-way
The phase contrast of signal after delay, generates road orthogonal signalling.
Alternatively, judge that signal generates implementing of delayed control signal described in multichannel and includes according to multichannel phase error: produce
Many group selections control signal is to be sequentially generated multipath delay control signal；Wherein, what each road delayed control signal generated is concrete real
Now include: selecting control signal to generate one group of phase error described in selected one group and judge signal, the phase error according to being generated is sentenced
Break signal and the selection control signal selected generate a road delayed control signal.
Alternatively, include with described the implementing of multichannel input signal of correction further according to described delayed control signal: according to
Described delayed control signal cyclically reduces the phase error of the adjacent phase signal of any two to zero or minima.
Alternatively, described orthogonal signalling phase error correction approach also includes: be filtered described multichannel orthogonal signalling processing.
As it has been described above, a kind of orthogonal signalling phase error correction device and method of the present invention, have the advantages that at ring
Under the negative feedback characteristic effect on road, the phase error of the phase signal that any two is adjacent will be regulated most zero or minimum by circulation
Value.After loop stability, the phase error of the N road orthogonal signalling of final output minimizes.
Accompanying drawing explanation
Fig. 1 is shown as the module diagram of an embodiment of the orthogonal signalling phase error correction device of the present invention.
Fig. 2 is shown as the module diagram of an embodiment of the orthogonal signalling phase error correction device of the present invention.
Fig. 3 is shown as the electrical block diagram of an embodiment of the orthogonal signalling phase error correction device of the present invention.
The workflow of the state machine module that Fig. 4 is shown as an embodiment of the orthogonal signalling phase error correction device of the present invention is shown
It is intended to.
Fig. 5 is shown as the schematic flow sheet of an embodiment of the orthogonal signalling phase error correction approach of the present invention.
Element numbers explanation
1 orthogonal signalling phase error correction system
11 multipath delay modules
12 quadrature phase generation modules
13 phase error detection modules
14 state machine module
S1～S4 step
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by disclosed by this specification
Content understand other advantages and effect of the present invention easily.The present invention can also be added by the most different detailed description of the invention
To implement or application, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modification or change is carried out under god.
It should be noted that the diagram provided in the present embodiment illustrates the basic conception of the present invention the most in a schematic way, the most graphic
In component count, shape and size time only display with relevant assembly in the present invention rather than is implemented according to reality draw, its reality
During enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
The present invention provides a kind of orthogonal signalling phase error correction device.In one embodiment, as it is shown in figure 1, described orthogonal
Signal phase error correcting unit 1 includes multipath delay module 11, quadrature phase generation module 12, phase error detection module
13 and state machine module 14.Wherein:
Multipath delay module 11 is for carrying out delay disposal according to multipath delay control signal to multichannel input signal one_to_one corresponding, defeated
Go out signal after multipath delay.Described multichannel is N road, N >=3, i.e. multichannel is at least three tunnels.In one embodiment, described many
Road Postponement module includes multiple delay cell, and corresponding each road input signal is carried out at delay by the plurality of delay cell
Reason, described delay cell individually can be controlled by described state machine module.Described multipath delay module is according to postponing control described in multichannel
Signal processed controls the plurality of delay cell, cyclically reduces the phase error of the adjacent phase signal of any two to zero or minimum
Value.
Quadrature phase generation module 12 is connected with described multipath delay module 11, and after being used for receiving described multipath delay, signal is carried out
Orthogonal processing, output multi-channel orthogonal signalling.In one embodiment, described quadrature phase generation module 12 includes multiple by anti-phase
The phase demodulation unit that device is constituted with gate, each described phase demodulation unit receives signal after adjacent two-way postpones, exports a road orthogonal
Signal.Phase demodulation refers to identify the difference of input signal；Phase demodulation unit refers to identify the device cell of the difference of input signal.
In one embodiment, described quadrature phase generation module 12 is also connected with load blocks, described quadrature phase generation module 12
Described multichannel orthogonal signalling are exported described load blocks, and described load blocks can include frequency mixer or doubler etc..Preferably
Ground, described load blocks is arrived in the output after buffering driver drives of described multichannel orthogonal signalling.Control signal after the delay of N road
After adjacent two-way postpones, signal is total to N group, such as when N is 4, and signal after having [0:3] road to postpone, wherein, adjacent two-way
Signal totally four groups after delay, are respectively [0] and [1], [1] and [2], [2] and [3], [3] and [0].
Phase error detection module 13 is connected with described quadrature phase generation module 12, is used for receiving described multichannel orthogonal signalling,
And the two-way orthogonal signalling of arbitrary neighborhood are carried out phase error judgement, output multi-channel phase error judges signal.Specifically, N
The adjacent two-way orthogonal signalling of road orthogonal signalling N group altogether, such as, when N is 4, have [0:3] road orthogonal signalling, wherein, phase
Adjacent two-way orthogonal signalling (referring to the two-way orthogonal signalling that phase place is adjacent) totally four groups, are respectively [0] and [1], [1] and [2], [2] with
[3], [3] and [0].
State machine module 14 is connected with described phase error detection module 13 and described multipath delay module 11, is used for receiving many
Phase error described in road judges that signal, feedback generate delayed control signal described in multichannel and export multipath delay module with further school
The most described multichannel input signal.By the algorithm preset in state machine module 14, judge signal according to described phase error, instead
Feedback generates delayed control signal described in multichannel, to control the digital delay elements on each branch road of input signal further, thus adjusts
Save the time delay of each road input signal.Feedback compensation by orthogonal signalling phase error correction device 1 so that it is final
The multichannel orthogonal signalling (being referred to as quadrature phase) of output do not have phase error.
In one embodiment, described phase error detection module 13 is used for receiving described multichannel orthogonal signalling, according to selecting control
The two-way orthogonal signalling that signal behavior is adjacent, and described two-way orthogonal signalling are carried out phase error judgement, output phase error is sentenced
Break signal；State machine module 14 is for sequentially producing the described selection control signal of described phase error detection module, and receives phase
The phase error produced by phase error detection module 13 answered judges signal, judges that signal produces and institute according to described phase error
State delayed control signal described in the selection corresponding road of control signal, thus order produces delayed control signal described in multichannel.One
In individual embodiment, described phase error detection module 13 includes for described orthogonal signalling are filtered the wave filter processed, institute
State wave filter and include single order RC low pass filter.
In one embodiment, described phase error detection module 13 includes organizing wave filter, a signal selector and one more
Comparator；Described wave filter for being filtered process to described orthogonal signalling；Described signal selector is for according to selecting control
The two-way orthogonal signalling that signal behavior is adjacent；Described comparator, for processing described adjacent two-way orthogonal signalling, exports
Phase error judges signal.
In one embodiment, as in figure 2 it is shown, described orthogonal signalling phase error correction device 1 receives 4 tunnel input signals,
Export 4 tunnel orthogonal signalling.Described orthogonal signalling phase error correction device 1 is the phase error correction ring of four phase quadrature signals
Road, by delay cell array (multipath delay module 11), four phase quadrature signals makers (quadrature phase generation module 12),
Driver, phase error detector (phase error detection module 13) and state machine (state machine module 14) composition.Wherein
Delay cell array is made up of four identical digital control delay subelements, and the digital controlled signal of four subelements (i.e. postpones
Control signal) independently controlled by state machine timesharing.Four phase quadrature signals makers are made up of, often four identical phase demodulation unit
The functional schematic of individual phase demodulation unit forms by phase inverter with gate, for the phase contrast of the adjacent Two-phases signal of phase demodulation.Just
The multipath output signals handing over signal generator output enters buffering driver (Buffer), buffering driver output OUT<3:0>(defeated
Go out signal) for driving the load (such as frequency mixer or doubler) in actual application, multipath output signals enters phase error simultaneously
Testing circuit.Phase error detection circuit is made up of wave filter, signal selector and comparator three part.Wave filter therein
Implementation forms including but not limited to four single order RC low pass filters, and wave filter exports after being filtered by multipath output signals
Signal mux_in<3:0>amplitude and OUT<3:0>dutycycle be directly proportional, also with OUT<3:0>adjacent phase signals between phase
Potential difference is directly proportional.Filter output signal mux_in<3:0>entering signal selector.Selector is operated in selection control signal
Sel<1:0>the lower circulation of effect select two adjacent input signals to enter comparators.Such as sel<1:0>equal to<00>time,
Mux_in<0>with mux_in<1>respectively enter vip Yu the vin port of comparator, comparator output logic signal comp (phase place
Error judgment signal) when being high level " 1 ", represent mux_in<0>amplitude higher than mux_in<1>, also illustrate that OUT<0>
Dutycycle bigger than OUT<1>dutycycle, OUT<0 in other words>and OUT<1>between phase contrast than OUT<1>with
OUT<2>between phase contrast big.So, the comp signal of comparator output enters state machine, by the output cc2 of state machine
(delayed control signal 2) controls a delay cell in delay cell array, i.e. reduces the time delay of In<1>branch road always
To COMP, low level " 0 " occurs so that OUT<0>dutycycle equal with OUT<1>dutycycle.Otherwise, as sel<1:0>
During equal to<00>, when comparator output logic signal comp is low level " 0 ", then increase In's<1>branch road by state machine
Time delay until COMP occur that high level " 1 " makes OUT<0>dutycycle equal with OUT<1>dutycycle.When
Sel<1:0>equal to<00>time, the delay cell on In<0>branch road in state machine regulation multichannel input signal In<3:0>so that
OUT<0>dutycycle equal with OUT<1>dutycycle after；State machine arranges sel<1:0>equal to<01>time, phase error detection
Device detection mux_in<1>with mux_in<2>, then regulate In<1 according to the result of comparator>road on delay cell so that
OUT<1>dutycycle equal with OUT<2>dutycycle.By that analogy, when state machine will circulate the delay regulating each branch road
Between so that the dutycycle of final output signal OUT<3:0>is the most equal, now, and the phase place between output signal OUT<3:0>
Difference is also equal, thus reaches the purpose of phase error correction.In another embodiment, described orthogonal signalling phase error
The circuit structure of correcting unit 1 is as shown in Figure 3.In this embodiment, input receives 8 signal in<7:0>, in<7:0>pass through
Del<7:0 is exported after the processing of circuit of delay cell>, after leggy phase discriminator processes and drives, final outfan exports
8 signal out<7:0>.Out<7:0>export in load, process through phase error detection circuit and state machine simultaneously, produce
Delayed control signal feedback control delay cell described in raw multichannel.It is finally reached the purpose of phase error correction.
In one embodiment, the specific works flow process of described state machine module 14 is as shown in Figure 4.Phase error in this embodiment
Wave filter 4 signal mux_in<0-3 of output of testing circuit>.Its workflow is as follows: initialize cc0, cc1 during beginning,
Cc2, cc3.Cc0, cc1, cc2, cc3 are respectively used to corresponding to 4 signal mux_in<0>, mux_in<1>, mux_in<2>,
The delayed control signal of the delay cell to input signal that mux_in<3>process produces.According to selecting control signal Sel<1:0>
Adjacent two-way output signal (orthogonal signalling processed after filtering) is selected to be input to comparator, and to described two-way output letter
Number carrying out phase error judgement, output phase error judges signal；Signal Comp, comp_last is judged according to described phase error
Value, produce (be included in initial value on the basis of change) and delay described in the described corresponding road of selection control signal Sel<1:0>
Control signal.When described selection control signal Sel<1:0>=<00>, adjacent two-way output signal is selected (to process after filtering
Orthogonal signalling) mux_in<0>and mux_in<1>be input to comparator, corresponding produce delayed control signal cc1 described in a road
Value.When working as Comp, comp_last=<11>, cc1 subtracts 1；When working as Comp, comp_last=<11>, cc1 subtracts 1；When
During Comp, comp_last=<00>, cc1 adds 1；When working as Comp, comp_last=<10>or<01>, cc1 continues to have.Similar
Ground, is controlled cc1, cc2, cc3.When described selection control signal Sel<1:0>=<01>, select adjacent two-way defeated
Go out signal (orthogonal signalling processed after filtering) mux_in<1>and mux_in<2>it is input to comparator, corresponding generation one tunnel
The value of described delayed control signal cc2.When described selection control signal Sel<1:0>=<10>, select adjacent two-way output letter
Number (orthogonal signalling processed after filtering) mux_in<2>and mux_in<3>it is input to comparator, corresponding produce described in a road
The value of delayed control signal cc3.When described selection control signal Sel<1:0>=<11>, select adjacent two-way output signal (warp
Cross the orthogonal signalling of Filtering Processing) mux_in<3>and mux_in<0>it being input to comparator, corresponding generation postpones control described in a road
The value of signal cc0 processed.In the present embodiment, described state machine module 14 also includes that one controls switch stop, when controlling switch
During stop=1, state machine terminates above-mentioned workflow.
The present invention also provides for a kind of orthogonal signalling phase error correction approach.As it is shown in figure 5, described orthogonal signalling phase error school
Correction method includes:
Step S1, carries out delay disposal according to multipath delay control signal and obtains signal after multipath delay multichannel input signal.
Step S2, carries out orthogonal processing and generates multichannel orthogonal signalling signal after described multipath delay.In one embodiment, institute
After stating multipath delay, signal generates implementing of multichannel orthogonal signalling and includes: adjacent according to many groups in signal after multipath delay
After two-way postpones, signal generates multichannel orthogonal signalling；Wherein, the phase of signal after being postponed by the described arbitrary group of adjacent two-way of discriminating
Potential difference, generates road orthogonal signalling.
All phase places adjacent two-way orthogonal signalling in described multichannel orthogonal signalling are carried out phase error judgement by step S3, generate
Multichannel phase error judges signal.
According to multichannel phase error, step S4, judges that signal feedback generates delayed control signal described in multichannel described with correction further
Multichannel input signal.By default algorithm, judge that signal feedback generates according to multichannel phase error and control delayed control signal,
To control the digital delay elements on each branch road of input signal, thus regulate the time delay of each road input signal so that it is
The multichannel orthogonal signalling (being referred to as quadrature phase) of whole output do not have phase error.According to described delayed control signal with
Correct described implementing of multichannel input signal further to include: cyclically reduce any two according to described delayed control signal
The phase error of adjacent phase signal is to zero or minima.
In one embodiment, judge that what signal generated delayed control signal described in multichannel implements bag according to multichannel phase error
Include: produce many group selections control signal to be sequentially generated multipath delay control signal；Wherein, each road delayed control signal generates
Implement and include: select control signal to generate one group of phase error described in selected one group and judge signal, according to the phase generated
Position error judgment signal and the selection control signal selected generate a road delayed control signal.
In one embodiment, described orthogonal signalling phase error correction approach also includes: filter described multichannel orthogonal signalling
Ripple processes.Specifically, before described multichannel orthogonal signalling being carried out phase error and judges, described multichannel orthogonal signalling are filtered
Process.
Technical scheme can apply to general quadrature phase generative circuit, frequency synthesizer, frequency mixer, doubler,
In the circuit such as quasi-sine-wave maker.
In sum, a kind of orthogonal signalling phase error correction device and method of the present invention, have the advantages that at ring
Under the negative feedback characteristic effect on road, the phase error of the phase signal that any two is adjacent will be regulated most zero or minimum by circulation
Value.After loop stability, the phase error of the N road orthogonal signalling of final output minimizes.The present invention can make leggy input letter
Number, the phase error of the introducing such as each finger delays unit and quadrature phase maker can be corrected；This technology is real at physics
Now or matching is required to be substantially reduced by laying out pattern cabling；The mismatch between each components and parts can be tolerated, it is simple to circuit spirit simultaneously
Live and design.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any it is familiar with this skill
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage of art.Therefore, such as
All that in art, tool usually intellectual is completed under without departing from disclosed spirit and technological thought etc.
Effect is modified or changes, and must be contained by the claim of the present invention.
Claims (14)
1. an orthogonal signalling phase error correction device, it is characterised in that described orthogonal signalling phase error correction device includes:
Multipath delay module, for carrying out at delay multichannel input signal one_to_one corresponding according to multipath delay control signal
Reason, signal after output multi-channel delay；
Quadrature phase generation module, is connected with described multipath delay module, for believing after the described multipath delay received
Number carry out orthogonal processing, output multi-channel orthogonal signalling；
Phase error detection module, is connected with described quadrature phase generation module, is used for receiving described multichannel orthogonal signalling,
And the two-way orthogonal signalling of arbitrary neighborhood are carried out phase error judgement, output multi-channel phase error judges signal；
State machine module, is connected with described phase error detection module and described multipath delay module, is used for receiving many
Phase error described in road judges that signal, feedback generate the output of multipath delay control signal to multichannel Postponement module with further
Correction multichannel input signal.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described quadrature phase generates
Module is also connected with load blocks, and described multichannel orthogonal signalling are exported described load by described quadrature phase generation module
Module.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described quadrature phase generates
Module includes multiple phase demodulation unit being made up of phase inverter and gate, and each described phase demodulation unit receives adjacent two-way
Signal after delay, exports road orthogonal signalling.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described phase error detection
Module is used for receiving described multichannel orthogonal signalling, according to selecting control signal to select adjacent two-way orthogonal signalling and right
Described two-way orthogonal signalling carry out phase error judgement, and output phase error judges signal；State machine module, for suitable
Sequence produces the described selection control signal of described phase error detection module, and receives corresponding phase error judgement letter
Number, judge signal to produce described in a road corresponding with described selection control signal according to described phase error and postpone to control letter
Number, thus order produces delayed control signal described in multichannel.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described multipath delay module
Including multiple delay cells, the plurality of delay cell carries out delay disposal to corresponding each road input signal,
Described delay cell individually can be controlled by described state machine module.
Orthogonal signalling phase error correction device the most according to claim 5, it is characterised in that: described multipath delay module
Control the plurality of delay cell according to delayed control signal described in multichannel, cyclically reduce the phase place that any two is adjacent
The phase error of signal is to zero or minima.
Orthogonal signalling phase error correction device the most according to claim 4, it is characterised in that: described phase error detection
Module includes organizing wave filter, a signal selector and a comparator more；Described wave filter is for described orthogonal
Signal is filtered processing；Described signal selector is for according to selecting control signal to select the adjacent orthogonal letter of two-way
Number；Described comparator is for processing described adjacent two-way orthogonal signalling, and output phase error judges signal.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described phase error detection
Module includes that described wave filter includes single order RC low pass for described orthogonal signalling are filtered the wave filter processed
Wave filter.
Orthogonal signalling phase error correction device the most according to claim 1, it is characterised in that: described orthogonal signalling phase place
Error correction device receives 4 tunnel input signals, exports 4 tunnel orthogonal signalling.
10. an orthogonal signalling phase error correction approach, it is characterised in that: described orthogonal signalling phase error correction approach includes:
According to multipath delay control signal, multichannel input signal carried out delay disposal and obtain signal after multipath delay；
Signal after described multipath delay is carried out orthogonal processing and generates multichannel orthogonal signalling；
All phase places adjacent two-way orthogonal signalling in described multichannel orthogonal signalling are carried out phase error judgement, and generation is many
Road phase error judges signal；
Judge that signal feedback generates delayed control signal described in multichannel according to multichannel phase error described with correction further
Multichannel input signal.
11. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: after described multipath delay
Signal generates implementing of multichannel orthogonal signalling and includes: prolong according to many groups of adjacent two-way in signal after multipath delay
The signal that lags generates multichannel orthogonal signalling；Wherein, the phase of signal after being postponed by the described arbitrary group of adjacent two-way of discriminating
Potential difference, generates road orthogonal signalling.
12. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: according to multichannel phase place by mistake
Difference judges that signal generates implementing of delayed control signal described in multichannel and includes: produce many group selections control signal with suitable
Sequence generates multipath delay control signal；Wherein, implementing that each road delayed control signal generates includes: selected one
Organize described selection control signal to generate one group of phase error and judge signal, according to the phase error generated judge signal with
And the selection control signal selected generates a road delayed control signal.
13. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: postpone control according to described
Signal processed includes with described the implementing of multichannel input signal of correction further: circulate according to described delayed control signal
Ground reduces the phase error of the adjacent phase signal of any two to zero or minima.
14. orthogonal signalling phase error correction approach according to claim 10, it is characterised in that: described orthogonal signalling phase
Position error calibration method also includes: be filtered described multichannel orthogonal signalling processing.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899290A (en) * | 2017-02-16 | 2017-06-27 | 电子科技大学 | A kind of high accuracy multi-phase clock correcting circuit |
| CN111274178A (en) * | 2018-12-05 | 2020-06-12 | 三星电子株式会社 | Quadrature detection and correction apparatus and method |
| CN113114227A (en) * | 2019-12-25 | 2021-07-13 | 澜至电子科技（成都）有限公司 | Multi-phase clock signal phase difference detection circuit and method and digital phase modulation system |
| CN117353748A (en) * | 2023-09-28 | 2024-01-05 | 深圳市鼎阳科技股份有限公司 | Delay correction method and related equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614878A (en) * | 2004-12-10 | 2005-05-11 | 清华大学 | Locking-phase loop style orthogonal signal phase calibrator |
| CN101729468A (en) * | 2008-10-27 | 2010-06-09 | 夏普株式会社 | IQ mismatch correction circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
-
2015
- 2015-05-20 CN CN201510259855.0A patent/CN106301356B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614878A (en) * | 2004-12-10 | 2005-05-11 | 清华大学 | Locking-phase loop style orthogonal signal phase calibrator |
| CN101729468A (en) * | 2008-10-27 | 2010-06-09 | 夏普株式会社 | IQ mismatch correction circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899290A (en) * | 2017-02-16 | 2017-06-27 | 电子科技大学 | A kind of high accuracy multi-phase clock correcting circuit |
| CN111274178A (en) * | 2018-12-05 | 2020-06-12 | 三星电子株式会社 | Quadrature detection and correction apparatus and method |
| CN111274178B (en) * | 2018-12-05 | 2024-09-13 | 三星电子株式会社 | Quadrature detection and correction apparatus and method |
| CN113114227A (en) * | 2019-12-25 | 2021-07-13 | 澜至电子科技（成都）有限公司 | Multi-phase clock signal phase difference detection circuit and method and digital phase modulation system |
| CN113114227B (en) * | 2019-12-25 | 2023-07-18 | 澜至电子科技（成都）有限公司 | Multi-phase clock signal phase difference detection circuit and method and digital phase modulation system |
| CN117353748A (en) * | 2023-09-28 | 2024-01-05 | 深圳市鼎阳科技股份有限公司 | Delay correction method and related equipment |
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|---|---|
| CN106301356B (en) | 2019-04-16 |
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