CN110262609B - Circuit driving control method, system, power regulation system and equipment terminal - Google Patents
Circuit driving control method, system, power regulation system and equipment terminal Download PDFInfo
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- CN110262609B CN110262609B CN201910586309.6A CN201910586309A CN110262609B CN 110262609 B CN110262609 B CN 110262609B CN 201910586309 A CN201910586309 A CN 201910586309A CN 110262609 B CN110262609 B CN 110262609B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention relates to a circuit driving control method, a system, a power regulation system and a device terminal, wherein the circuit driving control method comprises the steps of obtaining respective switch control signal sequences of each group of voltages in a preset power grid period, determining respective real-time voltage phase zero points of each group of voltages, transmitting the respective switch control signal sequences of each group of voltages to a data latch unit for latching through a data transmission unit before the corresponding time of each real-time voltage phase zero point, determining respective driving output enabling signals of each group of voltages according to the respective real-time phase zero points of each group of voltages, transmitting the respective switch control signal sequences from the data latch unit to the respective driving output units according to the respective driving output enabling signals of each group of voltages so as to output the corresponding switch control driving signals, realizing multi-group multi-path control driving output, and simplifying the design of a plurality of controllers required by a plurality of load loops, hardware cost is effectively saved.
Description
Technical Field
The invention relates to the technical field of power regulation, in particular to a circuit driving control method, a circuit driving control system, a power regulation system and a device terminal.
Background
At present, a power controller is often used for regulating load power in a power regulation process, wherein the power controller controls load output of each loop by controlling a driving signal through an output switch, however, in practical application occasions, a user may have input of a plurality of voltage levels, which respectively correspond to load output of multiple channels; or the voltage of a three-phase power grid of a user is input, each phase needs to carry a multi-channel load, so that a plurality of loops exist, and because the number of driving output paths corresponding to the current controller corresponds to the number of power adjusting units one by one, a huge number of controllers and power adjusting units are obviously needed, further, centralized networking control design needs to be implemented, more power cables need to be arranged to connect each power unit, and the expansibility is poor and the expansion cost is high.
Disclosure of Invention
In view of the above, the present application provides a circuit driving control method, system, power regulating system and device terminal.
A circuit drive control method, comprising:
acquiring a switch control signal sequence of each group of voltage in a preset power grid period;
determining respective real-time voltage phase zero points of each group of voltages;
before the time corresponding to each real-time voltage phase zero point, transmitting the respective switch control signal sequence of each group of voltages to a data latch unit through a data transmission unit for latching;
determining respective drive output enable signals of each group of voltages according to respective real-time phase zeros of each group of voltages;
and transmitting the respective switch control signal sequence of each group of voltages from the data latch unit to the respective drive output unit according to the respective drive output enable signal of each group of voltages so as to output the corresponding switch control drive signal.
In one embodiment, the step of determining the respective real-time voltage phase zero for each set of voltages comprises:
performing synchronous phase locking on each input group of voltages to obtain respective real-time phases of each group of voltages;
and determining the real-time voltage phase zero point corresponding to each group of voltages according to the real-time phase of each group of voltages.
In one embodiment, the data transmission unit adopts a plurality of registers which are transmitted in parallel, and the step of transmitting the respective switch control signal sequence of each group of voltages to the data latch unit through the data transmission unit for latching comprises the following steps:
and transmitting the respective switch control signal sequences to the respective data latch units through the respective registers for latching.
In one embodiment, the data transmission unit uses a shift register, and the step of transmitting the respective switch control signal sequence of each group of voltages to the data latch unit through the data transmission unit for latching comprises:
all switch control signal sequences are sequentially and serially input into a shift register;
and outputting the respective switch control signal sequence of each group of voltage to the data latch unit for latching through the shift register in parallel.
Further, there is provided a circuit drive control system including: the device comprises a controller, a data transmission unit, a data latch unit and a drive output unit;
the controller is used for acquiring a respective switch control signal sequence of each group of voltages in a preset power grid period, sending the sequence to the data transmission unit, determining a respective real-time voltage phase zero point of each group of voltages, determining a respective drive output enable signal of each group of voltages according to the respective real-time phase zero point of each group of voltages, and sending the respective drive output enable signal of each group of voltages to the drive output unit;
the data transmission unit is used for outputting the respective switch control signal sequence of each group of voltage to the data latch unit before the time corresponding to each real-time voltage phase zero point;
the data latch unit is used for latching the switch control signals of each group of voltages respectively;
the driving output unit is used for acquiring the respective switch control signal sequence of each group of voltages from the data latch unit according to the respective driving output enable signal of each group of voltages so as to output the corresponding switch control driving signal.
In one embodiment, the data transfer unit employs a shift register or a plurality of parallel transfer registers.
In one embodiment, the data latch unit employs a D flip-flop.
In addition, a power regulating system is also provided, which comprises the circuit driving control system and a power regulating unit;
the circuit driving control system is used for outputting switch control driving signals corresponding to each group of voltages and sending the switch control driving signals to the power regulating unit;
the power adjusting unit is used for adjusting the power of the corresponding load according to the switch control driving signal corresponding to each group of voltage.
In addition, the device terminal comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor runs the computer program to enable the device terminal to execute the circuit driving control method.
A storage medium stores a computer program used by a device terminal.
According to the circuit driving control method, the circuit driving control system, the power regulation system and the equipment terminal, the respective real-time voltage phase zero point of each group of voltage in the preset power grid period is determined by obtaining the respective switch control signal sequence of each group of voltage, the respective switch control signal sequence of each group of voltage is transmitted to the data latch unit for latching through the data transmission unit before the corresponding moment of each real-time voltage phase zero point, the respective driving output enabling signal of each group of voltage is determined according to the respective real-time phase zero point of each group of voltage, the respective switch control signal sequence is transmitted to the respective driving output unit from the data latch unit according to the respective driving output enabling signal of each group of voltage so as to output the corresponding switch control driving signal, the control driving output of multiple groups of multiple paths can be realized, and the power system, the power regulation system and the equipment terminal, The three-phase power grid, even a multi-phase power system and the like can be easily expanded according to needs, the number of theoretical driving circuits is not limited, the expandability is strong, the control driving output of the power controller can be achieved without complex software driving programming logic design, the design of a plurality of controllers required when a plurality of load loops are simplified, and the hardware cost is effectively saved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
FIG. 1 is a flow chart illustrating a circuit driving control method according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a method for obtaining a real-time voltage phase zero according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating a method for transmitting a sequence of switch control signals for each set of voltages to a data latch unit according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating a circuit driving control method according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a data transmission unit and a data latch unit according to an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating a circuit driving control method according to another embodiment of the present invention;
FIG. 7 is a block diagram of a circuit driving control system according to an embodiment of the present invention;
fig. 8 is a block diagram of a power conditioning system in an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Various embodiments of the present disclosure will be described more fully hereinafter. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the disclosure.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Fig. 1 is a circuit driving control method provided in an embodiment, and the circuit driving control method includes:
and step S110, acquiring respective switch control signal sequences of each group of voltages in a preset power grid period.
In the current power grid, the output voltage, current and power of a multi-loop generally need to be controlled and regulated, at the moment, a single-phase power grid and a multi-phase power grid both need to be controlled for driving output, and the multi-phase power grid is generally a three-phase power grid.
In a single-phase power grid, different grid voltage levels may exist, and loads of multiple loops may exist in each different voltage level; likewise, for each phase grid voltage in a three-phase grid, there may also be a plurality of load paths.
Therefore, aiming at the power grid voltage corresponding to each loop load, the controller acquires an externally input switch control signal, and further acquires a respective switch control signal sequence of each group of voltage in a preset power grid period.
The preset grid cycle is generally selected from a half grid cycle or a grid cycle, but is not limited to this, and the preset grid cycle is set and selected according to specific situations.
And step S120, determining respective real-time voltage phase zero points of each group of voltages.
And each group of voltages respectively has a corresponding real-time voltage phase zero point, and the respective real-time voltage phase zero point of each group of voltages can be obtained by utilizing the timing function of the control processor.
The silicon controlled rectifier is used as one of AC components, including bidirectional and unidirectional silicon controlled rectifiers, and the bidirectional silicon controlled rectifier can be conducted in both positive and negative power supplies, so that the silicon controlled rectifier is often used in AC load regulating circuit.
In one implementation, for example, to accomplish the above power regulation for each loop, the power regulation for each loop is often accomplished by adjusting the average output power of the thyristors. The triggering of the thyristor has two modes, generally called zero-cross triggering or phase-shift triggering. When zero-crossing triggering is adopted, the alternating current passes through zero points from the positive half cycle to the negative half cycle or from the negative half cycle to the positive half cycle because of the positive and negative half cycles, and the output average power of the controllable silicon is changed by changing the conduction cycle number within a certain time, so that the effect of adjusting the load power is realized, wherein the cycle number refers to the time that the alternating current completes one complete change, namely one cycle is elapsed by one sine waveform. This type of PWM signal adjusts the motor output, the more times the motor is turned on during a given period the greater the average output power.
Therefore, the subsequent driving control is provided with a basis by determining the respective real-time voltage phase zero point of each group of voltages.
Step S130, before the time corresponding to each real-time voltage phase zero point, transmitting the switch control signal sequence of each group of voltages to the data latch unit through the data transmission unit for latching.
The reason why the drive output unit still keeps the original output unchanged before the zero-point time corresponding to the real-time phase zero point and only updates the drive output unit at the zero-point time corresponding to the real-time phase zero point is that the data transmission unit cannot directly send the respective switch control signal sequence of each group of voltages to the drive output unit for output before the zero-point time corresponding to each real-time phase zero point, but needs to send the respective switch control signal sequence of each group of voltages to the data latch unit for latching.
The data transmission unit may be a dedicated chip, or may also be a CPLD (Complex Programmable logic Device) or an FPGA (Field-Programmable Gate Array).
The time corresponding to the time when the switch control signal sequence of the group of grid voltages is transmitted to the data latch unit through the data transmission unit for latching is called an update data time, the corresponding signal is called an update data signal, and the update data time is generally set at a certain time position before the real-time voltage phase zero time so as to complete the data transmission and latching of the switch control signal sequence.
And step S140, determining respective drive output enable signals of each group of voltages according to respective real-time phase zero points of each group of voltages.
Each group of voltages corresponds to a respective drive output unit, the update time of the drive output units needs to be determined according to respective real-time phase zero points of each group of voltages, the drive output still keeps the original output before the zero point time corresponding to the real-time phase zero points, the drive output units are updated only at the zero point time corresponding to the real-time phase zero points, therefore, the drive output enable signals corresponding to each drive output unit often need to be set corresponding to the respective real-time phase zero point time of each group of voltages, and when the respective real-time phase zero point time of each group of voltages arrives, the drive output enable signals just are in an effective output state.
For example, in one embodiment, the output enable signal is driven to the low-level inactive output state before the respective real-time phase zero of each set of voltages, and the output enable signal is driven to the high-level active output state just after the respective real-time phase zero of each set of voltages is reached.
And step S150, transmitting the respective switch control signal sequence of each group of voltages from the data latch unit to the respective drive output unit according to the respective drive output enable signal of each group of voltages to output the corresponding switch control drive signal.
Each group of voltages corresponds to a respective driving output unit, and each driving output unit is controlled by a corresponding driving output enable signal.
When the respective drive output enable signal of each group of voltages is in an effective output state, the drive output unit can receive the respective switch control signal sequence of each group of voltages sent by the data latch unit and further output the corresponding switch control drive signal to a subsequent circuit.
In one embodiment, the driving output unit may receive the respective switch control signal sequence of each set of voltages sent by the data latch unit, and further output the corresponding switch control driving signal to control the scr power adjustment circuit to adjust the power level of the corresponding loop load.
The circuit driving control method can realize multi-group and multi-path control driving output, is suitable for a single-phase power grid system, can be expanded to power systems with different input voltage levels, three-phase power grids, even multi-phase power systems and the like, can be easily expanded according to needs, is not limited by the theoretical driving path number, has strong expandability, can achieve the control driving output of the power controller without complex software driving programming logic design, simplifies the design of a plurality of controllers when a plurality of load loops are needed, facilitates the grouping and wiring of users, and effectively saves the hardware cost.
In one embodiment, as shown in fig. 2, step S120 includes:
and S122, performing synchronous phase locking on each input group of voltages respectively to obtain respective real-time phases of each group of voltages.
The phase-locked loop is used for performing synchronous phase locking on each group of input voltages respectively, and then the real-time phase of each group of voltages is obtained.
And S124, determining the real-time voltage phase zero point corresponding to each group of voltages according to the real-time phase of each group of voltages.
The real-time phases can be tracked at regular time by utilizing the timing function of the control processor, and then the real-time voltage phase zero point corresponding to each group of voltages is determined.
In one embodiment, the data transmission unit employs a plurality of registers for parallel transmission, and the step of transmitting the respective switch control signal sequence of each set of voltages through the data transmission unit to the data latch unit for latching in step S130 includes:
and transmitting the switch control signal sequence of each group of voltage to the data latch unit for latching through the register.
The switch control signal sequence corresponding to each group of voltage is transmitted to the data latch unit for temporary storage through the corresponding independent register, and the registers corresponding to each group of voltage are mutually independent and do not influence each other.
In one embodiment, the data transmission unit adopts a shift register, and as shown in fig. 3, the step of transmitting the respective switch control signal sequence of each set of voltages to the data latch unit through the data transmission unit in step S130 for latching includes:
in step S132, all the switch control signal sequences are sequentially input to the shift register in series.
When the data transmission unit adopts a shift register, all switch control signal sequences are arranged into a whole according to a combination sequence, and a character string code is input to the shift register in series.
In step S134, the respective switch control signal sequences of each group of voltages are output in parallel to the data latch unit through the shift register for latching.
Here, after step S132, the shift register may output the respective switch control signal sequences of each group of voltages in parallel, and latch the signals to be stored in the data latch unit.
When the switch control signal sequence of any group of power grid voltages needs to be updated independently, the switch control signal sequence corresponding to the group of power grid voltages is updated through shifting of the shift register, and meanwhile, the switch control signal sequence stored by the data latch unit is updated correspondingly.
In one embodiment, as shown in fig. 4, the grid voltage is a single-phase grid voltage, the switch control signal sequence of each loop is shown as CH1 and CH2 … CHn in fig. 4, the number N of the corresponding loop channels is greater than or equal to 2, and N ∈ N is equal to N ∈ N+) The input voltage waveform is a sine waveform, the phase-locked loop shown in fig. 4 can be used for performing phase-locked synchronization on the input group of grid voltages respectively, so as to obtain the real-time phase of the group of grid voltages, and further, the timing function of the controller is used for obtaining the zero point (including the time coordinate of the zero point) of the real-time voltage phase of the grid voltages.
Further, before the time corresponding to the real-time voltage phase zero point, the switching control signal sequence of the set of grid voltages is transmitted to the data latch unit through the data transmission unit for latching, wherein the time corresponding to the switching control signal sequence of the set of grid voltages transmitted to the data latch unit through the data transmission unit for latching is referred to as an update data time, and the corresponding signal is referred to as an update data signal, as shown in an update data signal waveform in fig. 4.
In addition, the respective driving output enable signal of each group of voltages can be further determined according to the respective real-time phase zero point of each group of voltages, as shown by the waveform of the driving output enable signal in fig. 4.
The respective switch control signal sequence of each group of voltages is transmitted from the data latch unit to the respective drive output unit to output the corresponding switch control drive signal according to the respective drive output enable signal of each group of voltages, and the switch output drive signals corresponding to the drive output unit are shown as CH1 output and CH2 output … CHn output in fig. 4.
Fig. 5 shows a schematic circuit structure diagram of the DATA transmission unit and the DATA latch unit, in this embodiment, the DATA transmission unit adopts a shift register composed of n D flip-flops, the DATA latch unit adopts a DATA latch composed of n D flip-flops, the shift register adopts a serial input and parallel output connection mode, where OUT _ EN represents a driving output enable signal, DATA _ LOCK represents a DATA update signal, DATA represents an input switch control signal sequence, DATA _ CLK represents a shift trigger pulse, RST represents a reset signal, and Q1 to Qn represent output switch control driving signals.
When the switch control signal sequence of any group of voltage needs to be updated independently, the shift register is used for shifting to update the switch control signal sequence corresponding to the group of power grid voltage, and the switch control signal sequence stored by the DATA updating latch unit is updated correspondingly.
As shown in fig. 6, OUT _ EN is defined at the grid zero crossing position at the start timing, and at the end of the time period, the data update of the input switching control signal sequence is performed during any time period before the grid zero crossing. DATA is shifted by matching DTAT _ CLK with DATA, a switch control signal sequence of the next power grid half period is input in series through a preceding stage shift register, and is latched into a subsequent stage DATA latch by a DATA _ LOCK rising edge. After the switching sequence for the next power grid half cycle is prepared, the output is turned on at the zero crossing point of the next power grid half cycle by the output enable signal OUT _ EN, and the output is updated to the driving output unit for output.
In an embodiment, the grid voltage is a three-phase grid voltage, and for convenience, it is assumed that the phase grid voltage includes n loops, and a processing procedure of the phase grid voltage is substantially the same as that of the single-phase grid voltage, and is not described herein again.
By adopting the circuit driving control method, the circuit driving control method can be expanded to any multi-path power circuit, the theoretical driving circuit number is not limited, the expandability is strong, the control driving output of the power controller can be achieved without complex software driving programming logic design, the circuit driving control method is not only suitable for a single-phase power grid system, but also can be expanded to power systems with different input voltage levels, three-phase power grids, even multi-phase power systems and the like, the design that a plurality of controllers are needed when a plurality of load circuits are simplified, the difficulty of control networking is reduced, convenience is brought to a user to group cabinets and wire connection, and the hardware cost is effectively saved.
It should be noted that, for a conventional three-phase power grid, the circuit driving control method can well balance the output of a three-phase bus, reduce the unbalance degree of the power grid, and reduce the energy input of a user power grid.
Further, as shown in fig. 7, there is also provided a circuit drive control system 200, the circuit drive control system 200 including: a controller 210, a data transmission unit 220, a data latch unit 230, and a driving output unit 240.
The controller 210 is configured to obtain a respective switch control signal sequence of each group of voltages in a preset power grid period, determine a respective real-time voltage phase zero of each group of voltages, and determine a respective drive output enable signal of each group of voltages according to the respective real-time phase zero of each group of voltages;
the data transmission unit 220 is configured to output a sequence of switch control signals of each group of voltages to the data latch unit 230 before a time corresponding to each real-time voltage phase zero;
the data latch unit 230 is configured to latch the respective switch control signal of each group of voltages;
the driving output unit 240 is configured to obtain a respective sequence of switching control signals of each group of voltages from the data latch unit 230 according to a respective driving output enable signal of each group of voltages to output a corresponding switching control driving signal.
In one embodiment, the data transfer unit employs a shift register or a plurality of parallel transfer registers.
In one embodiment, the data latch unit employs a D flip-flop.
In addition, as shown in fig. 8, a power conditioning system 300 is further provided, where the power conditioning system 300 includes the above circuit driving control system 200 and a power conditioning unit 310, and the power conditioning unit 310 is connected to a load 320;
the circuit driving control system 200 is configured to output a switch control driving signal corresponding to each group of voltages and send the switch control driving signal to the power adjusting unit 310;
the power adjusting unit 310 is configured to perform power adjustment on the respective loads 320 according to the switch control driving signal corresponding to each group of voltages.
The power adjusting unit 310 usually employs a thyristor circuit, and a switch control driving signal output by the circuit driving control system 200 can trigger and drive the thyristor circuit in the power adjusting unit 310, thereby completing the power adjustment of the load 320.
The power regulation system 300 can be expanded to any multi-circuit loop for driving by adopting the circuit driving control system 200, the theoretical driving circuit number is not limited, the expandability is strong, the control driving output of the power controller can be achieved without complex software driving programming logic design, the power regulation system is suitable for a single-phase power grid system, and can also be expanded to power systems with different input voltage levels, a three-phase power grid or even a multi-phase power system and the like, the design of a plurality of controllers is needed when a plurality of load loops are simplified, the difficulty of control networking is reduced, convenience is brought to the user for cabinet combination and wiring, and the hardware cost is effectively saved.
In addition, the device terminal comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor runs the computer program to enable the device terminal to execute the circuit driving control method.
A storage medium stores a computer program used by a device terminal.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (10)
1. A circuit driving control method, characterized by comprising:
acquiring a switch control signal sequence of each group of voltage in a preset power grid period;
determining respective real-time voltage phase zero points of each group of voltages;
before the time corresponding to each real-time voltage phase zero point, transmitting the respective switch control signal sequence of each group of voltages to a data latch unit through a data transmission unit for latching;
determining respective drive output enable signals of each group of voltages according to respective real-time phase zeros of each group of voltages;
and transmitting the respective switch control signal sequence of each group of voltages from the data latch unit to the respective drive output unit according to the respective drive output enable signal of each group of voltages so as to output the corresponding switch control drive signal.
2. The circuit drive control method of claim 1 wherein the step of determining the respective real-time voltage phase zero for each set of voltages comprises:
performing synchronous phase locking on each input group of voltages to obtain respective real-time phases of each group of voltages;
and determining the real-time voltage phase zero point corresponding to each group of voltages according to the real-time phase of each group of voltages.
3. The circuit driving control method according to claim 1, wherein the data transmission unit employs a plurality of registers for parallel transmission, and the step of transmitting the respective switch control signal sequence for each group of voltages through the data transmission unit to the data latch unit for latching comprises:
and transmitting the respective switch control signal sequences to the respective data latch units through the respective registers for latching.
4. The circuit driving control method according to claim 1, wherein the data transmission unit employs a shift register, and the step of transmitting the respective switch control signal sequence of each group of voltages to the data latch unit through the data transmission unit for latching comprises:
all switch control signal sequences are sequentially and serially input into the shift register;
and outputting the respective switch control signal sequence of each group of voltage to a data latch unit in parallel through the shift register for latching.
5. A circuit drive control system, comprising: the device comprises a controller, a data transmission unit, a data latch unit and a drive output unit;
the controller is used for acquiring a respective switch control signal sequence of each group of voltages in a preset power grid period, sending the sequence to the data transmission unit, determining a respective real-time voltage phase zero point of each group of voltages, determining a respective drive output enable signal of each group of voltages according to the respective real-time phase zero point of each group of voltages, and sending the respective drive output enable signal of each group of voltages to the drive output unit;
the data transmission unit is used for transmitting the respective switch control signal sequence of each group of voltage to the data latch unit before the time corresponding to each real-time voltage phase zero point;
the data latch unit is used for latching the switch control signals of each group of voltages;
the driving output unit is used for acquiring the respective switch control signal sequence of each group of voltages from the data latch unit according to the respective driving output enable signal of each group of voltages so as to output the corresponding switch control driving signal.
6. The circuit driving control system according to claim 5, wherein the data transmission unit employs a shift register or a plurality of parallel transmission registers.
7. The circuit driving control system according to claim 5, wherein the data latch unit employs a D flip-flop.
8. A power conditioning system comprising a power conditioning unit and the circuit drive control system of any one of claims 5 to 7;
the circuit driving control system is used for outputting switch control driving signals corresponding to each group of voltages and sending the switch control driving signals to the power regulating unit;
and the power regulating unit is used for regulating the power of the corresponding load according to the switch control driving signal corresponding to each group of voltage.
9. A device terminal, comprising a memory for storing a computer program and a processor for executing the computer program to cause the device terminal to execute the circuit driving control method according to any one of claims 1 to 4.
10. A storage medium characterized by storing said computer program for use by the device terminal of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910586309.6A CN110262609B (en) | 2019-07-01 | 2019-07-01 | Circuit driving control method, system, power regulation system and equipment terminal |
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| CN103282990A (en) * | 2011-01-12 | 2013-09-04 | 三菱电机株式会社 | Power switching control device and closing control method thereof |
| CN102891500A (en) * | 2012-09-25 | 2013-01-23 | 株洲南车时代电气股份有限公司 | Parallel control method of three-phase two-level inverter with isolation transformers |
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