CN106299108B - Resistance-variable storing device and preparation method thereof - Google Patents
Resistance-variable storing device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a kind of resistance-variable storing devices, first electrode, the resistive material layer, second electrode being set on substrate including successively lamination further include the conductive bumps array that interval is formed in first electrode and resistive material layer interface or/and second electrode and resistive material layer interface.The resistance-variable storing device in the preparation of the interface of first electrode or/and second electrode and resistive material layer by being evenly distributed and controllable conductive bumps array, concentrate on electric field on conductive bumps array, increase the probability that conductive channel is formed at conductive bumps array, to improve the stability of resistance-variable storing device work, the homogeneity of resistance-variable storing device is improved.The invention also discloses the preparation methods of above-mentioned resistance-variable storing device, comprising: A, prepares the step of first electrode, resistive material layer, second electrode on substrate；B, the step of first electrode and resistive material layer interface or/and second electrode and resistive material layer interface prepare conductive bumps array.
Description
Technical field
The invention belongs to technical field of integrated circuits, in particular, being related to a kind of resistance-variable storing device homogeneity of can be improved
Resistance-variable storing device and preparation method thereof.
Background technique
Resistance-variable storing device (RRAM) have structure is simple, read or write speed is fast, operation is low in energy consumption, storage density is big, with it is existing
CMOS (complementary metal oxide semiconductor) technology is compatible, potentiality further scaled down are big, multivalue can be achieved deposits
The features such as storage, therefore, it is the contenders of next-generation general-purpose storage.
Traditional resistance-variable storing device is typical sandwich structure: one layer of resistive material layer is added between upper and lower electrode,
Its working principle is that the voltage different in resistive material layer both ends application size or polarity, controls the resistance value of resistive material layer
It is converted between high resistance and low resistance state, to realize the write-in and erasing of data.The conductive filament theory being widely recognized as thinks,
During resistive, Lacking oxygen or metal ion in resistive material layer occur migration and form conductive filament, when conductive filament connects
When leading to upper and lower electrode, resistance-variable storing device enters low resistive state；When applying a certain appropriate voltage again, conductive filament fracture, into
Enter high-impedance state, so the variation of resistance value is derived from the fracture and formation of conductive filament.Since this fracture is random with formation
, during multiple resistive, the pattern of conductive filament and distribution are different, so electrical parameter (the set electricity of resistive material layer
Pressure, reset voltage, high low resistance state resistance value etc.) there is very big fluctuation, seriously reduce the stabilization of resistance-variable storing device work
Property and reliability.Therefore how to effectively control the key cores for being formed with being broken into raising memory device performance of conductive filament
Problem.
Summary of the invention
To solve the above-mentioned problems of the prior art, the present invention provides a kind of resistive resistor and preparation method thereof,
The resistive resistor effectively improves the homogeneity of resistance-variable storing device by preparing conductive bumps array.
In order to achieve the above object of the invention, present invention employs the following technical solutions:
A kind of resistance-variable storing device, substrate, first electrode, resistive material layer, second electrode including the setting of successively lamination, also
It include: that interval is formed in the first electrode and resistive material layer interface or/and the second electrode and resistive material stratum boundary
Conductive bumps array at face.
Further, any one of the material of the conductive bumps array in Pt, Cu, Al, Ti, Ni, Au.
Further, the height of the conductive bumps array is 1nm~5nm；
Further, the spacing of the conductive bumps array is 50nm~50 μm.
Further, the resistive material layer with a thickness of 5nm~200nm.
Further, the material of the resistive material layer be selected from hafnium oxide, titanium oxide, zirconium oxide, zinc oxide, tungsten oxide,
At least one of tantalum oxide；Any one of the material of the substrate in silicon substrate, glass substrate, flexible substrate；Institute
State any one of the material of lower electrode in Pt, Cu, Al, Ti, Ni, TiN；The material of the top electrode be selected from Pt, Cu,
Any one in Al, Ti, Ni, TiN.
Another object of the present invention, which also resides in, provides a kind of preparation method of resistance-variable storing device as described above, comprising: A,
The step of preparing first electrode, resistive material layer, second electrode on substrate；B, in the first electrode and resistive material stratum boundary
At face or/and the step of the second electrode prepares conductive bumps array with resistive material layer interface.
Further, the step of preparing conductive bumps array specifically includes: using spin-coating method in the first electrode and resistance
Change material layer interface or/and the second electrode and resistive material layer interface are coated with nanometer ball array；Using self assembly skill
The nanometer ball array is self-assembly of a nanometer layers of balls by art；Using the nanometer layers of balls as exposure mask, sink in the nanometer layers of balls
Product forms metallic film；Wherein, the deposition method is selected from chemical vapor deposition, physical vapour deposition (PVD), electron beam evaporation, splashes
It penetrates, atomic layer deposition, any one in thermal evaporation；Nanometer layers of balls described in erosion removal forms the conductive bumps array.
Further, the number of plies of the nanometer layers of balls is 1~2 layer.
Further, any one of the material of the nanometer layers of balls in polystyrene, silica.
The present invention is by using nanosphere lithography technology at the interface of first electrode or/and second electrode and resistive material layer
Place's preparation is evenly distributed and controllable conductive bumps array, concentrates on electric field on conductive bumps array, increases in conductive stud
The probability for forming conductive channel at array is played, to improve the stability that the resistance-variable storing device works, improves resistance-change memory
The homogeneity of device.
Detailed description of the invention
What is carried out in conjunction with the accompanying drawings is described below, above and other aspect, features and advantages of the embodiment of the present invention
It will become clearer, in attached drawing:
Fig. 1 is the structural schematic diagram of the resistance-variable storing device of embodiment according to the present invention 1；
Fig. 2 is the step flow chart of the preparation method of the resistance-variable storing device of embodiment according to the present invention 1；
Fig. 3 is the structural schematic diagram of the nanometer layers of balls of embodiment according to the present invention 1；
Fig. 4 is the structural schematic diagram of the conductive bumps array of embodiment according to the present invention 1；
Fig. 5 is the structural schematic diagram of the resistance-variable storing device of embodiment according to the present invention 2；
Fig. 6 is the step flow chart of the preparation method of the resistance-variable storing device of embodiment according to the present invention 2；
Fig. 7 is the structural schematic diagram of the nanometer layers of balls of embodiment according to the present invention 2；
Fig. 8 is the structural schematic diagram of the conductive bumps array of embodiment according to the present invention 2.
Specific embodiment
Hereinafter, with reference to the accompanying drawings to detailed description of the present invention embodiment.However, it is possible to come in many different forms real
The present invention is applied, and the present invention should not be construed as limited to the specific embodiment illustrated here.On the contrary, providing these implementations
Example is in order to explain the principle of the present invention and its practical application, to make others skilled in the art it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.In the accompanying drawings, for the sake of clarity, element can be exaggerated
Shape and size, and identical label will be used to indicate the same or similar element always.
Embodiment 1
Fig. 1 is the structural schematic diagram of the resistance-variable storing device of embodiment according to the present invention 1.
Referring to Fig.1, the resistance-variable storing device of embodiment according to the present invention 1 includes substrate 10；Successively lamination is set to substrate
First electrode 20, resistive material layer 30, second electrode 40 on 10；And it is set to first electrode 20 and resistive material layer 30
Between and be spaced and be formed in the conductive bumps array 50 on 20 surface of first electrode.
In the present embodiment, the material of above-mentioned conductive bumps array 50 is Pt, and the height of conductive bumps array is 5nm left
The right side, spacing 50nm；But the present invention is not restricted to this, and the material of conductive bumps array is further selected from Cu, Al, Ti, Ni, Au
Any one, and the height limitation of conductive bumps array is between 1nm~5nm, spacing control be 50nm~50 μm it
Between.
Being formed in first electrode 20 and the conductive bumps array 50 of 30 interface of resistive material layer can make electric field concentrate on leading
In electric array of protrusions 50, the probability for forming conductive channel at conductive bumps array 50 is increased, is deposited to improve the resistive
The stability of reservoir work, improves the homogeneity of resistance-variable storing device.
Preferably, in the present embodiment, substrate 10 is silicon substrate；The material for the first electrode 20 being formed on silicon substrate is
Pt；The material for being formed in the resistive material layer 30 in first electrode 20 is zirconium oxide, and it is with a thickness of 60nm；It is formed in resistive material
The material of second electrode 40 on the bed of material 30 is Pt；But the present invention is not restricted to this, as the material of substrate 10 can also be glass
The material of glass substrate or flexible substrate etc., first electrode 20 and second electrode 40 is also selected from Cu, Al, Ti, Ni, TiN
Any one, the material of resistive material layer 30 is also selected from titanium oxide, hafnium oxide, zinc oxide, tungsten oxide, appointing in tantalum oxide
Anticipate or mixtures thereof one kind, and the thickness of the resistive material layer 30 is not restricted to 60nm, need to only be controlled 5nm~
In the range of 200nm.
Below with reference to resistance-variable storing device shown in Fig. 2 preparation method step flow chart to above-mentioned resistance-variable storing device
Preparation method is described in detail.
Referring to Fig. 2, the step flow chart of the preparation method of the resistance-variable storing device of embodiment according to the present invention 1 includes as follows
Step:
In step 110, deposited metal Pt forms first electrode 20 on substrate 10.Specifically, substrate 10 using
Silicon substrate.
In the step 120, nanosphere is formed in first electrode 20, and nanometer ball array is formed using self-assembling technique,
Form nanometer layers of balls 61.Specifically, nanosphere is formed using spin-coating method, and the material of nanosphere is polystyrene.
In the present embodiment, the number of plies of nanometer layers of balls 61 is one layer, and the top view of this nanometer of layers of balls 61 is as shown in figure 3, Fig. 3
In, the gap a 62 and 63 two kinds of the gap b gap are formd between the polystyrene nanospheres of array arrangement.
In step 130, the deposited metal Pt in nanometer layers of balls 61, in 61 surface of nanometer layers of balls, the gap a 62 and the gap b
Metallic film is formed at 63.Specifically, using electron beam evaporation method in nanometer layers of balls 61 deposited metal Pt.
It is worth noting that depositing the method for forming metallic film in nanometer layers of balls 61 can also be chemical vapor deposition
Any one in product, physical vapour deposition (PVD), sputtering method, atomic layer deposition method, thermal evaporation etc..
In step 140, erosion removal nanometer layers of balls 61 forms conductive bumps array 50 in first electrode 20.Also
It is to say, in the present embodiment, it is exposure mask with nanometer layers of balls 61 that it is substantially conductive bumps array 50, in the gap a 62 and the gap b 63
Locate the Pt metal of deposition, the structural schematic diagram of the conductive bumps array 50 is as shown in Figure 4.
The height for the conductive bumps array 50 being prepared through step 120-140 is 5nm, spacing 50nm.It is worth explanation
, range of the height control of conductive bumps array 50 in 1nm~5nm, range of the spacing control in 50nm~50 μm
, and the regulation of the height of conductive bumps array 50 and spacing can be expired by the partial size of control polystyrene nanospheres
Foot, therefore that is the conductive bumps array 50 is to be evenly distributed and controllable array.
Material as conductive bumps array 50 is not restricted to Pt metal, other such as Cu, Al, Ti, Ni, Au metals are equal
It can.
In step 150, resistive material layer 30 is formed in first electrode 20 and conductive bumps array 50.Specifically, it hinders
The forming method of change material layer 30 is using sputtering method.
Specifically, resistive material layer 30 is the zirconium oxide layer with a thickness of 60nm.
In a step 160, second electrode 40 is formed in resistive material layer 30.
Specifically, the material of second electrode 40 is Pt metal, the forming method of second electrode 40 using photoetching process and
Stripping method.
In the present embodiment, the mistake of first electrode 20, resistive material layer 30 and second electrode 40 is successively formed on substrate 10
Cheng Jun belongs to those skilled in the art's customary means, no longer repeats one by one the process herein.
The resistance-variable storing device being prepared through above-mentioned steps 110-160 passes through in first electrode 20 and 30 boundary of resistive material layer
Conductive bumps array 50 is prepared at face, electric field can be made to concentrate on conductive bumps array 50, is increased in conductive bumps array 50
Place forms the probability of conductive channel, to improve the stability of resistance-variable storing device work, improves the equal of resistance-variable storing device
One property.
Embodiment 2
In the description of embodiment 2, details are not described herein with the something in common of embodiment 1, only describes with embodiment 1 not
Same place.Embodiment 2 difference from example 1 is that, referring to Fig. 5, the resistance-variable storing device of embodiment according to the present invention 2
Including substrate 10；Successively lamination is set to first electrode 20, resistive material layer 30, second electrode 40 on substrate 10；And if
It is placed between second electrode 40 and resistive material layer 30 and is spaced the conductive bumps array for being formed in 30 surface of resistive material layer
50。
Referring to the step flow chart of the preparation method of the resistance-variable storing device of embodiment according to the present invention 2 in Fig. 6.
In step 210, deposited metal Pt forms first electrode 20 on substrate 10, forms resistive in first electrode 20
Material layer 30.Specifically, substrate 10 is atomic layer deposition using glass substrate, the forming method of resistive material layer 30.
In the present embodiment, resistive material layer 30 is with a thickness of the aluminium oxide of 5nm and the mixed layer of hafnium oxide.
In a step 220, nanosphere is formed in resistive material layer 30, and nanometer spherical array is formed using self-assembling technique
Column form nanometer layers of balls 61.Specifically, nanosphere is formed using spin-coating method, and the material of nanosphere is silica.
In the present embodiment, the number of plies of nanometer layers of balls 61 is two layers, and the top view of this nanometer of layers of balls 61 is as shown in fig. 6, Fig. 7
In, a kind of gap in the gap c 64 is formd between the silica nanosphere of array arrangement.
In step 230, the deposited metal Pt in nanometer layers of balls 61 is formed at 61 surface of nanometer layers of balls and the gap c 64
Metallic film.Specifically, using electron beam evaporation method in nanometer layers of balls 61 deposited metal Pt.
In step 240, erosion removal nanometer layers of balls 61 forms conductive bumps array 50 in resistive material layer 30.?
That is it is exposure mask with nanometer layers of balls 61 that it is substantially conductive bumps array 50 in the present embodiment, deposited at the gap c 64
The structural schematic diagram of Pt metal, the conductive bumps array 50 is as shown in Figure 8.
The height for the conductive bumps array 50 being prepared through step 220-240 is 1nm, and spacing is 50 μm.
In step 250, second electrode 40 is formed in resistive material layer 30 and conductive bumps array 50.
Specifically, the material of second electrode 40 is Pt metal, the forming method of second electrode 40 using photoetching process and
Stripping method.
In the present embodiment, the mistake of first electrode 20, resistive material layer 30 and second electrode 40 is successively formed on substrate 10
Cheng Jun belongs to those skilled in the art's customary means, no longer repeats one by one the process herein.
The resistance-variable storing device being prepared through above-mentioned steps 210-250 passes through in second electrode 40 and 30 boundary of resistive material layer
Conductive bumps array 50 is prepared at face, electric field can be made to concentrate on conductive bumps array 50, is increased in conductive bumps array 50
Place forms the probability of conductive channel, to improve the stability of resistance-variable storing device work, improves the equal of resistance-variable storing device
One property.
It is worth noting that preparing conductive bumps in first electrode 20 or second electrode 40 and 30 interface of resistive material layer
Array 50 is to increase to concentrate on electric field on conductive bumps array 50 and form conductive lead at conductive bumps array 50
The probability in road improves the homogeneity of resistance-variable storing device to improve the stability of resistance-variable storing device work；Therefore, if
One electrode 20 prepares conductive bumps with 30 interface of resistive material layer and second electrode 4 and 30 interface of resistive material layer
Array 50 equally can reach the purpose of the homogeneity of raising resistance-variable storing device of the invention, still belong to institute's protection scope of the present invention.
Although the present invention has shown and described referring to specific embodiment, it should be appreciated by those skilled in the art that:
In the case where not departing from the spirit and scope of the present invention being defined by the claims and their equivalents, can carry out herein form and
Various change in details.
Claims (8)
1. a kind of preparation method of resistance-variable storing device, which is characterized in that the resistance-variable storing device includes the lining of successively lamination setting
Bottom, first electrode, resistive material layer, second electrode and be formed in the first electrode and resistive material layer interface or/and
The conductive bumps array of the second electrode and resistive material layer interface；The preparation method includes:
A, the step of preparing first electrode, resistive material layer, second electrode on substrate；
B, it is prepared in the first electrode and resistive material layer interface or/and the second electrode and resistive material layer interface
The step of conductive bumps array；
Wherein, the step of preparing conductive bumps array specifically includes:
Using spin-coating method in the first electrode and resistive material layer interface or/and the second electrode and resistive material stratum boundary
Nanometer ball array is coated at face；
The nanometer ball array is self-assembly of by a nanometer layers of balls using self-assembling technique；
Using the nanometer layers of balls as exposure mask, metallic film is formed using depositing in the nanometer layers of balls；Wherein, the deposition side
Method is any one in chemical vapor deposition, physical vapour deposition (PVD), electron beam evaporation, sputtering, atomic layer deposition, thermal evaporation
Kind；
Nanometer layers of balls described in erosion removal forms the conductive bumps array.
2. preparation method according to claim 1, which is characterized in that the material of the conductive bumps array be selected from Pt, Cu,
Any one in Al, Ti, Ni, Au.
3. preparation method according to claim 1, which is characterized in that the height of the conductive bumps array be 1nm~
5nm。
4. preparation method according to claim 1, which is characterized in that the spacing of the conductive bumps array is 50nm~50
μm。
5. preparation method according to claim 1, which is characterized in that the resistive material layer with a thickness of 5nm~
200nm。
6. preparation method according to claim 1, which is characterized in that the material of the resistive material layer be selected from hafnium oxide,
At least one of titanium oxide, zirconium oxide, zinc oxide, tungsten oxide, tantalum oxide；The material of the substrate is selected from silicon substrate, glass
Any one in substrate, flexible substrate；The material of the first electrode is any one in Pt, Cu, Al, Ti, Ni, TiN
Kind；Any one of the material of the second electrode in Pt, Cu, Al, Ti, Ni, TiN.
7. -6 any preparation method according to claim 1, which is characterized in that the number of plies of the nanometer layers of balls is 1~2
Layer.
8. preparation method according to claim 7, which is characterized in that the material of the nanometer layers of balls be selected from polystyrene,
Any one in silica.
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| CN108389964B (en) * | 2018-04-03 | 2021-05-25 | 集美大学 | Method for preparing resistive random access memory by using nano shielding layer to perform ion positioning injection |
| CN111293221B (en) * | 2020-04-08 | 2022-04-01 | 电子科技大学 | Preparation method of high-performance memristor |
| CN111463347A (en) * | 2020-04-08 | 2020-07-28 | 电子科技大学 | Method for preparing high-performance memristor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157692A (en) * | 2011-03-22 | 2011-08-17 | 复旦大学 | Organic resistive random access memory (RRAM) with peak shaped bottom electrode and manufacture method thereof |
| CN103035840A (en) * | 2012-12-19 | 2013-04-10 | 北京大学 | Resistive random access memory and preparation method thereof |
| US8963114B2 (en) * | 2013-03-06 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157692A (en) * | 2011-03-22 | 2011-08-17 | 复旦大学 | Organic resistive random access memory (RRAM) with peak shaped bottom electrode and manufacture method thereof |
| CN103035840A (en) * | 2012-12-19 | 2013-04-10 | 北京大学 | Resistive random access memory and preparation method thereof |
| US8963114B2 (en) * | 2013-03-06 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers |
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