CN106298825A - Imageing sensor and preparation method thereof - Google Patents
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- CN106298825A CN106298825A CN201610835403.7A CN201610835403A CN106298825A CN 106298825 A CN106298825 A CN 106298825A CN 201610835403 A CN201610835403 A CN 201610835403A CN 106298825 A CN106298825 A CN 106298825A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 98
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 238000000407 epitaxy Methods 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 44
- 229910052732 germanium Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 24
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 23
- 230000007547 defect Effects 0.000 claims description 16
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 7
- 230000005622 photoelectricity Effects 0.000 claims description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical group [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 9
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
- H01L27/14669—Infrared imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Abstract
Present invention is disclosed a kind of imageing sensor and preparation method thereof, including: provide the first wafer, described first wafer to include the first silicon substrate, the first silicon epitaxy layer and the interconnection layer stacked gradually；It is thinned to described first silicon epitaxy layer from the side of described silicon substrate to described first wafer；The second wafer, described second wafer is provided to include the second wafer substrate and are positioned at the semiconductor layer of described second wafer substrate side；By described second wafer with thinning after the first wafer be bonded, described semiconductor layer is towards described first silicon epitaxy layer；Described second wafer substrate is peeled off from described second wafer；In the described semiconductor layer exposed, prepare the second isolation structure, and in described semiconductor layer, form the second photodiode region.Wherein, the energy gap of described semiconductor layer is less than the energy gap of silicon, it is possible to preferably absorbs near infrared light, can be effectively improved cmos image sensor conversion quantum efficiency.
Description
Technical field
The present invention relates to image sensor technologies field, particularly relate to a kind of imageing sensor and preparation method thereof.
Background technology
Developing rapidly along with mobile Internet, people are the hugest to the demand of intelligent terminal, and have intelligence
The imageing sensor of the title of terminal " eyes " has also welcome unprecedented development space.Traditional CCD (Charge-coupled
Device, charge coupled cell) imageing sensor due to its power consumption relatively big, market is confined in high performance digital camera；
Cmos image sensor (CMOS Image Sensor is called for short CIS) is the most low in energy consumption, and speed is fast, and is prone to and existing half
Semiconductor process is mutually compatible, and production cost is relatively low, and this makes cmos image sensor occupy the half river in imageing sensor market
Mountain.
The subject matter that cmos image sensor runs into is quantum efficiency (QE, the quantum of near infrared light
Efficiency) relatively low.Quantum efficiency refers to that a photon is transformed into the probability of light induced electron in PD.In order to improve infrared light
Quantum efficiency, prior art often increases the integral thickness of silicon substrate, but, adopt obtain in this way CMOS figure
As the performance of sensor is the best.
Summary of the invention
It is an object of the invention to, it is provided that a kind of imageing sensor and preparation method thereof, the amount of near infrared light can be improved
Sub-efficiency, improves the performance of cmos image sensor simultaneously.
For solving above-mentioned technical problem, the present invention provides the preparation method of a kind of imageing sensor, including:
The first wafer, described first wafer is provided to include the first silicon substrate and first silicon epitaxy layer of stacking, described first
Silicon epitaxy layer has the first photodiode area and for isolating the first isolation junction of described first photodiode area
Structure；
It is thinned to described first silicon epitaxy layer from the side of described silicon substrate to described first wafer；
The second wafer, described second wafer is provided to include the second wafer substrate and are positioned at described second wafer substrate side
Semiconductor layer, the energy gap of described semiconductor layer is less than the energy gap of described silicon substrate；
By described second wafer with thinning after the first wafer be bonded, wherein, described semiconductor layer is towards described
One silicon epitaxy layer；
Described second wafer substrate is peeled off from described second wafer；And
In the described semiconductor layer exposed, prepare the second isolation structure, and in described semiconductor layer, form the second light
Photodiode region, described second isolation structure isolates described second photodiode region, described second isolation structure and described the
The position of one isolation structure is corresponding, and described second photodiode region is corresponding with the position of described first photodiode region
Further, the preparation method of described imageing sensor also includes: carry out ion implanting at described second wafer lining
Bottom surface forms defect layer to the surface of described semiconductor layer side.
Further, by described second wafer substrate from the step that described second wafer is peeled off, will along described defect layer
Described second wafer substrate is peeled off from the side of described semiconductor layer.
Further, described defect layer is hydrogen ion doped layer.
Further, described semiconductor layer is germanium-silicon layer.
Further, the step of described offer the second wafer includes:
Described second wafer substrate is provided；
Carry out ion implanting in described second wafer substrate and form the second wafer doped layer；
Epitaxy technique is utilized to form germanium layer in the side of described second wafer substrate, and at described second wafer substrate and germanium
Forming described germanium-silicon layer between Ceng, described germanium-silicon layer is described semiconductor layer；
Circle heat treatment is utilized to be advanced to by the germanium in described germanium layer in described second wafer substrate, the most described
Silicon in two wafer substrate diffuses in described germanium layer, forms thicker described semiconductor layer；
Remove described germanium layer.
Further, the degree of depth of described defect layer is more than the degree of depth of described second wafer doped layer.
Further, described circle heat treatment includes the process that multiple first temperature and the second temperature cycles process,
Described first temperature is 750 DEG C～950 DEG C, and described second temperature is 650 DEG C～850 DEG C.
Further, described second wafer substrate includes the second silicon substrate and is positioned at the second of described second silicon substrate side
Silicon epitaxy layer, described second wafer doped layer is positioned in described second silicon epitaxy layer, and described germanium-silicon layer is positioned at outside described second silicon
Prolonging layer and deviate from the side of described second silicon substrate, described second wafer doped layer is positioned at described second silicon epitaxy layer.
Further, described first photodiode area includes first kind doped region and Second Type doped region
Territory, described Second Type doped region is arranged towards described first silicon substrate, the doping type of described second photodiode region
For Second Type.
The present invention also provides for a kind of imageing sensor, including:
First wafer, described first wafer includes the first silicon epitaxy layer, has the first photoelectricity in described first silicon epitaxy layer
Diode area and for isolating the first isolation structure of described first photodiode area；
Second wafer, described second wafer includes semiconductor layer, and the energy gap of described semiconductor layer is less than monocrystal silicon
Energy gap, has the second photodiode region and for isolating the of described second photodiode region in described semiconductor layer
Two isolation structures；
Together, wherein, described semiconductor layer is towards described first silicon epitaxy for described second wafer and the first wafer bonding
Layer arrange, described second isolation structure is corresponding with the position of described first isolation structure, described second photodiode region and
The position of described first photodiode region is corresponding.
Compared with prior art, imageing sensor that the present invention provides and preparation method thereof has the advantage that
In described imageing sensor and preparation method thereof, by the method for wafer bonding, at the of described first wafer
One silicon epitaxy layer (i.e. photodiode area) has been bonded semi-conductor layer, and the energy gap of described semiconductor layer is less than described silicon
The energy gap of substrate, it is possible to preferably absorb near infrared light, can be effectively improved cmos image sensor conversion quantum efficiency.
Further, germanium and silicon epitaxial technique can to make technique the most compatible with present silicon single crystal, thus is easier
Apply in current cmos image sensor technique.
Accompanying drawing explanation
Fig. 1 is the flow chart of the preparation method of imageing sensor in one embodiment of the invention；
Fig. 2 to Figure 11 be the imageing sensor of one embodiment of the invention preparation method in the schematic diagram of device architecture.
Detailed description of the invention
Existing imageing sensor improves the quantum efficiency of near infrared light by increasing the integral thickness of silicon substrate, so
And, the performance adopting the cmos image sensor obtained in this way is the best.The research of existing imageing sensor is sent out by inventor
Existing, existing imageing sensor improves the quantum efficiency of near infrared light by increasing the integral thickness of silicon substrate, from present
2um～3um increase to 5um～10um.The simple monocrystal silicon thickness that increases can improve conversion quantum efficiency, but thereupon
Process challenge the most constantly aggravate, ratio is if desired for deeper ion implanting, and deeper ion implanting may require that thicker light
Photoresist, and the photoresist of thickness can reduce the resolution of minimum dimension, eventually affects the performance of cmos image sensor.In addition
Thick monocrystal silicon can bring again the technological problems of lithography alignment, needs to increase extra technique to realize Alignment Process.
Inventor further study show that, due to the inherent character of band structure, near infrared light is existed by silicon single crystal material
The problems such as absorptance is low, absorption length length.Submicron, deep-submicron model is entered especially with feature sizes of semiconductor devices
Enclosing, running voltage is more and more less, and transistor P-N junction is more and more shallow, depletion region from surface increasingly close to, thickness more and more thinner, very
Difficulty effectively absorbs incident optical signal, and the photo-generated carrier produced in substrate depths is due to can not be quickly by electrical field draw
Compound, photoelectric current is not contributed, causes the cmos image sensor quantum conversion made the lowest.
Inventor furthers investigate discovery, and the energy gap of germanium silicon material is less than the energy gap of silicon, if by germanium silicon material
Apply in cmos image sensor product, it is possible to preferably absorb near infrared light, cmos image sensor can be effectively improved
Conversion quantum efficiency.
According to the studies above, the present invention provides the preparation method of a kind of imageing sensor, it is provided that a kind of imageing sensor
Preparation method, as it is shown in figure 1, comprise the steps:
Step S11, it is provided that the first wafer, described first wafer includes the first silicon substrate and first silicon epitaxy layer of stacking,
Described first silicon epitaxy layer has the first photodiode area and for isolating the of described first photodiode area
One isolation structure；
Step S12, is thinned to described first silicon epitaxy layer from the side of described silicon substrate to described first wafer；
Step S13, it is provided that the second wafer, described second wafer includes the second wafer substrate and is positioned at described second wafer lining
The semiconductor layer of side, the end, the energy gap of described semiconductor layer is less than the energy gap of described silicon substrate；
Step S14, by described second wafer with thinning after the first wafer be bonded, wherein, described quasiconductor aspect
To described first silicon epitaxy layer；And
Step S15, peels off described second wafer substrate from described second wafer.
Step S16, prepares the second isolation structure, and shape in described semiconductor layer in the described semiconductor layer exposed
The second photodiode region, described second isolation structure is become to isolate described second photodiode region, described second isolation structure
Corresponding with the position of described first isolation structure, described second photodiode region and the position of described first photodiode region
Put corresponding.
By the method for wafer bonding, the first silicon epitaxy layer (i.e. photodiode area) at described first wafer is bonded
Semi-conductor layer, the energy gap of described semiconductor layer is less than the energy gap of described silicon substrate, it is possible to preferably absorb near
Infrared light, can be effectively improved cmos image sensor conversion quantum efficiency.
Further, germanium and silicon epitaxial technique can to make technique the most compatible with present silicon single crystal, thus is easier
Apply in current cmos image sensor technique.
Below in conjunction with schematic diagram, imageing sensor of the present invention and preparation method thereof is described in more detail, wherein
Illustrate the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise invention described herein, and still
So realize the advantageous effects of the present invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art,
And it is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make to due to the fact that unnecessary details and chaotic.Will be understood that opening in any practical embodiments
In Faing, it is necessary to make a large amount of implementation detail to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, an embodiment change into another embodiment.Additionally, it should think that this development is probably complexity and consuming
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
Below in conjunction with Fig. 2 to Figure 11, illustrating the preparation method of the imageing sensor of the present invention, Fig. 2 to Figure 11 is this
The schematic diagram of device architecture in the preparation method of the imageing sensor inventing an embodiment.
First, carrying out step S11, as shown in Figure 2, it is provided that the first wafer 100, described first wafer 100 includes layer successively
The first folded silicon substrate 110 and the first silicon epitaxy layer 120, has multiple first photoelectricity two pole in described first silicon epitaxy layer 120
Territory, area under control 121 and for isolating the first isolation structure 122 of described first photodiode area 121, wherein, described first light
Photodiode area 121 is used for preparing photodiode.
Additionally, described first wafer 100 can also include that interconnection layer 130, described interconnection layer 130 are positioned at outside described first silicon
Prolonging layer 120 and deviate from the side of described first silicon substrate 110, described interconnection layer 130 includes pel array, the knot of described pel array
Structure can include the structures such as grid, connecting hole structure, interconnection line.Described first silicon substrate the 110, first silicon epitaxy layer 120 and mutually
Even the preparation process of layer 130 can use standard semi-conductor processes, and this is it will be appreciated by those skilled in the art that, at this not
Repeat.
In the present embodiment, described first silicon substrate 110 and the first silicon epitaxy layer 120 are p-type doping, implement at other
In example, described first silicon substrate 110 and the first silicon epitaxy layer 120 can also be n-type doping.Described first silicon epitaxy layer 120
Doping content less than the doping content of described first silicon substrate 110, the resistance of described first silicon epitaxy layer 120 is about 1ohm/
Cm～50ohm/cm, the resistance of described first silicon substrate 110 is about 0.01ohm/cm～0.1ohm/cm.
It is also preferred that the left described first photodiode area 121 includes that first kind doped region 1211 and Second Type are mixed
Miscellaneous region 1212, described Second Type doped region 1212 is arranged, wherein, at the present embodiment towards described first silicon substrate 110
In, the first kind is p-type, and Second Type is N-type, in other embodiments, it is also possible to the first kind is N-type, and Second Type is P
Type.In the present embodiment, described first isolation structure 122 is ion implanting isolation structure, mixing of described first isolation structure 122
Miscellany type is p-type, in other embodiments, described first isolation structure 122 can also be dielectric isolation (such as shallow-trench isolation or
Deep trench isolation) etc. structure.
Then, carry out step S12, as it is shown on figure 3, carry out from the side of described silicon substrate 110 to described first wafer 100
It is thinned to described first silicon epitaxy layer 120.Concrete, described first silicon epitaxy layer 120 can be deviated from described interconnection layer 130
Side and a bonding wafer 300 are bonded, and then grind the side of described silicon substrate 110 to described first wafer 100
Mill.During thinning, suitable thickness, thinning can be thinned to by the first silicon epitaxy layer 120 described to part
The thickness of one silicon epitaxy layer can be 2 μm～10 μm.
Afterwards, carrying out step S13, as shown in Figure 4, it is provided that the second wafer 200, described second wafer 200 includes that second is brilliant
Circle substrate and the semiconductor layer being positioned at described second wafer substrate side.In the present embodiment, described step S13 includes following son
Step S131～sub-step S135:
Sub-step S131, as shown in Figure 4, it is provided that described second wafer substrate 210, in the present embodiment, described second is brilliant
Circle substrate 210 includes the second silicon substrate 211 and is positioned at the second silicon epitaxy layer 212 of described second silicon substrate 212 side:
Sub-step S132, forms the second wafer mix as it is shown in figure 5, carries out ion implanting in described second wafer substrate 210
Diamicton 213, described second wafer doped layer 213 is positioned in described second silicon epitaxy layer 212.In the present embodiment, described second
Wafer doped layer 213 is n-type doping, and in other embodiments, described second wafer doped layer 213 can also adulterate for p-type.Tool
Body, phosphonium ion can be injected on described second silicon epitaxy layer 212, thus formed highly concentrated on described second wafer 200 surface
Second wafer doped layer 213 described in the N-type of degree；
Sub-step S133, as shown in Figure 6, utilizes epitaxy technique to form germanium layer in the side of described second wafer substrate 210
230, when forming described germanium layer 230, part germanium ion can enter in described second silicon epitaxy layer 212, thus described second
Forming described germanium-silicon layer 220 between wafer substrate 210 and germanium layer 230, described germanium-silicon layer 220 is as described semiconductor layer, described
The energy gap of germanium-silicon layer 220 is less than the energy gap of described silicon substrate, and in other embodiments, described semiconductor layer is all right
For other material, numerous to list herein；
In order to convenient in subsequent step, described germanium-silicon layer 220 is peeled off with the second wafer substrate 210, it is also preferred that the left
In the present embodiment, also include: as it is shown in fig. 7, carry out ion implanting in described second wafer substrate 210 towards described quasiconductor
The surface of layer 220 side forms defect layer 214, and the degree of depth of described defect layer 214 is deep more than described second wafer doped layer 213
Degree.It is also preferred that the left described defect layer 214 is hydrogen ion doped layer, i.e. in described second wafer substrate 210 towards described semiconductor layer
H ion is injected on the surface of 220 sides, and described H ion can destroy the lattice of crystal in described second wafer substrate 210, to be formed
Described defect layer 214, can peel off easily.
Sub-step S134, as shown in Figure 8, utilizes circle heat treatment to be advanced to by the germanium in described germanium layer 230 described
In second wafer substrate 210, the silicon in the most described second wafer substrate 210 diffuses to, in described germanium layer 230, be formed thicker
Described semiconductor layer (described germanium-silicon layer 220).In the present embodiment, remaining described second wafer doped layer 213 and part institute
State germanium layer 230 and become described germanium-silicon layer 220.Further, described circle heat treatment includes multiple first temperature and second
The process that temperature cycles processes, described first temperature is 750 DEG C～950 DEG C, and described second temperature is 650 DEG C～850 DEG C, each
Circulate about 1 minute～10 minutes, through 5～15 cycle heat treatment processes, i.e. can form the suitable described SiGe of thickness
Layer 220；
Sub-step S135, as it is shown in figure 9, remove described germanium layer 230, concrete, grinding technics can be used described germanium
Layer 230 is removed.
Afterwards, carry out step S14, as shown in Figure 10, by described second wafer 200 with thinning after the first wafer 100 enter
Line unit closes, and wherein, described semiconductor layer 220 is bonded towards described first silicon epitaxy layer 220.
Then, carry out step S15, as shown in figure 11, described second wafer substrate 210 is shelled from described second wafer 200
From, expose described semiconductor layer 220, in the present embodiment, owing to being prepared for described defect layer 214, in described defect layer 214
Crystal has defect, when heated, can along described defect layer 214 by described second wafer substrate 210 from described quasiconductor
The side of layer 220 is peeled off.
Subsequently, carry out step S16, with continued reference to Figure 11, the described semiconductor layer 220 exposed is prepared the second isolation
Structure 222, and in described semiconductor layer 220, form multiple second photodiode region 221, described second isolation structure 222
Isolating described second photodiode region, described second isolation structure 222 is relative with the position of described first isolation structure 122
Should, described second photodiode 221 district is corresponding with the position of described first photodiode region 121.In the present embodiment,
Formed described second isolation structure 222 time, self-assembling formation isolated by described second isolation structure 222 multiple described second
Photodiode region 221.
Owing to described second wafer doped layer 213 is n-type doping, so the doping of described first photodiode region 1211
Type is n-type doping, and in the present embodiment, described second isolation structure 222 is deep groove isolation structure.
Further, it is also possible to deviate from the side of described first silicon epitaxy layer 120 at described semiconductor layer 220 to form a P-type layer,
And can go out described bonding wafer 300.
In imageing sensor as shown in figure 11, described imageing sensor includes the first wafer 100 and the second wafer 200,
Described first wafer 100 includes the first silicon epitaxy layer 120, has the first photodiode region in described first silicon epitaxy layer 120
Territory 121 and for isolating the first isolation structure 122 of described first photodiode area 121；Described second wafer 200 includes
Semiconductor layer 220, the energy gap of described semiconductor layer 220, less than the energy gap of monocrystal silicon, has in described semiconductor layer 220
There is the second photodiode region 221 and for isolating the second isolation structure 222 of described second photodiode region 221；Described
Second wafer 100 and the first wafer 200 are bonded together, and wherein, described semiconductor layer 220 is towards described first silicon epitaxy layer
120 are arranged, and described second isolation structure 222 is corresponding with the position of described first isolation structure 122, described second photoelectricity two pole
Area under control 221 is corresponding with the position of described first photodiode region 121.Described second photodiode region 221 and described the
One photodiode region 121 forms photodiode 2, and described second isolation structure 222 is common with described first isolation structure 122
Isolate adjacent described photodiode 2.
In the structure ultimately formed, it is used for being formed photodiode, described semiconductor layer at described semiconductor layer 220
The energy gap of 220 is less than the energy gap of silicon, it is possible to preferably absorb near infrared light, can be effectively improved cmos image sensing
Device conversion quantum efficiency.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. the preparation method of an imageing sensor, it is characterised in that including:
The first wafer, described first wafer is provided to include the first silicon substrate and first silicon epitaxy layer of stacking, outside described first silicon
Prolong and layer has the first photodiode area and for isolating the first isolation structure of described first photodiode area；
It is thinned to described first silicon epitaxy layer from the side of described silicon substrate to described first wafer；
The second wafer, described second wafer is provided to include the second wafer substrate and are positioned at partly leading of described second wafer substrate side
Body layer, the energy gap of described semiconductor layer is less than the energy gap of described silicon substrate；
By described second wafer with thinning after the first wafer be bonded, wherein, described semiconductor layer is towards described first silicon
Epitaxial layer；
Described second wafer substrate is peeled off from described second wafer；And
In the described semiconductor layer exposed, prepare the second isolation structure, and in described semiconductor layer, form the second photoelectricity two
Area under control, pole, described second isolation structure isolate described second photodiode region, described second isolation structure with described first every
Corresponding from the position of structure, described second photodiode region is corresponding with the position of described first photodiode region.
2. the preparation method of imageing sensor as claimed in claim 1, it is characterised in that the preparation side of described imageing sensor
Method also includes: carry out ion implanting described second wafer substrate towards described semiconductor layer side surface formed defect layer.
3. the preparation method of imageing sensor as claimed in claim 2, it is characterised in that by described second wafer substrate from institute
State in the step that the second wafer is peeled off, along described defect layer, described second wafer substrate is shelled from the side of described semiconductor layer
From.
4. the preparation method of imageing sensor as claimed in claim 2, it is characterised in that described defect layer is hydrogen ion doped
Layer.
5. the preparation method of the imageing sensor as described in any one in claim 1-4, it is characterised in that described quasiconductor
Layer is germanium-silicon layer.
6. the preparation method of imageing sensor as claimed in claim 5, it is characterised in that the step of described offer the second wafer
Including:
Described second wafer substrate is provided；
Carry out ion implanting in described second wafer substrate and form the second wafer doped layer；
Utilize epitaxy technique to form germanium layer in the side of described second wafer substrate, and described second wafer substrate and germanium layer it
Between form described germanium-silicon layer, described germanium-silicon layer is described semiconductor layer；
Utilizing circle heat treatment to be advanced to by the germanium in described germanium layer in described second wafer substrate, the most described second is brilliant
Silicon in circle substrate diffuses in described germanium layer, forms thicker described semiconductor layer；
Remove described germanium layer.
7. the preparation method of imageing sensor as claimed in claim 6, it is characterised in that the degree of depth of described defect layer is more than institute
State the degree of depth of the second wafer doped layer.
8. the preparation method of imageing sensor as claimed in claim 6, it is characterised in that described circle heat treatment includes
The process that multiple first temperature and the second temperature cycles process, described first temperature is 750 DEG C～950 DEG C, described second temperature
It it is 650 DEG C～850 DEG C.
9. the preparation method of imageing sensor as claimed in claim 1, it is characterised in that described first photodiode area
Including first kind doped region and Second Type doped region, described Second Type doped region is towards described first silicon substrate
Arranging, the doping type of described second photodiode region is Second Type.
10. an imageing sensor, it is characterised in that including:
First wafer, described first wafer includes the first silicon epitaxy layer, has the first photoelectricity two pole in described first silicon epitaxy layer
Territory, area under control and for isolating the first isolation structure of described first photodiode area；
Second wafer, described second wafer includes semiconductor layer, and the energy gap of described semiconductor layer is less than the forbidden band of monocrystal silicon
Width, described semiconductor layer has the second photodiode region and for isolate the second of described second photodiode region every
From structure；
Together, wherein, described semiconductor layer sets towards described first silicon epitaxy layer for described second wafer and the first wafer bonding
Putting, described second isolation structure is corresponding with the position of described first isolation structure, and described second photodiode region is with described
The position of the first photodiode region is corresponding.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080067499A1 (en) * | 2006-09-15 | 2008-03-20 | Sharp Laboratories Of America, Inc. | Silicon/germanium superlattice thermal sensor |
| CN103441132A (en) * | 2013-07-10 | 2013-12-11 | 上海新储集成电路有限公司 | Method for preparing back-illuminated CMOS image sensor through low-temperature silicon wafer breaking |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080067499A1 (en) * | 2006-09-15 | 2008-03-20 | Sharp Laboratories Of America, Inc. | Silicon/germanium superlattice thermal sensor |
| CN103441132A (en) * | 2013-07-10 | 2013-12-11 | 上海新储集成电路有限公司 | Method for preparing back-illuminated CMOS image sensor through low-temperature silicon wafer breaking |
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