CN106298786B

CN106298786B - Integrated circuit and its production and operating method

Info

Publication number: CN106298786B
Application number: CN201510317842.4A
Authority: CN
Inventors: 叶腾豪; 胡志玮; 林立颖
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2015-06-11
Filing date: 2015-06-11
Publication date: 2019-05-07
Anticipated expiration: 2035-06-11
Also published as: CN106298786A

Abstract

A kind of integrated circuit includes three-dimensional NAND memory array, multiple bit lines containing memory transistors, and different bit lines is coupled to the different parts of three-dimensional NAND memory array, and multiple transistors pair in semiconductor laminated.Different layers in semiconductor laminated include the different transistors pair of multiple pair of transistors.Each transistor is to including the first transistor and second transistor.Wherein, the first transistor includes first and third source/drain endpoint；Second transistor includes second and third source/drain endpoint.First source/drain terminal is electrically coupled to an erasing voltage line.Second source/drain terminal is electrically coupled in a plurality of write-in/reading pressure-wire corresponding one.Third source/drain terminal is electrically coupled in multiple bit lines corresponding one.

Description

Integrated circuit and its production and operating method

Technical field

The present invention relates to a kind of nonvolatile memory device (non-volatile memory devices), especially It is related to a kind of system vertical gate memory array (3D vertical gate memory array).

Background technique

NAND memory array is isolated from array and from sensing amplifier using high voltage switching transistor Erasing voltage.Although reading and writing using relatively low voltage, erasing operation has coupled a high-intensitive voltage To array.Therefore use high voltage switching transistor by array and the electrically isolated (electrically of sensing amplifier Decouple), to prevent PN junction from collapsing (junction breakdown).

In general, among the erasing operation of plane NAND memory array (2D NAND memory array), three The current potential in the highest region PWI of p-type doping concentration can increase in weight well (triple-well).Typical Planar nand memory member The arrangement mode of part is placed in outside the region PWI using 4 one group of high-tension switch field-effect transistor (MOSFETs), thus will Array is electrically isolated with erasing voltage.

In the arrangement of another plane NAND memory array, memory array is shared with 4 switch field-effect transistors The region PWI to prevent biggish pressure difference, and allows low-pressure designs rule to be suitable for this 4 switch field-effect transistors.Newest peace Row's mode is that a high-voltage switch gear field-effect transistor is added additional except the region PWI, and by high-voltage switch gear field-effect transistor Number be reduced to 1 by 4.Thus while additionally increasing a transistor, but entire area is made to become smaller.

Three-dimensional nand memory structure equally benefits from the configuration of high voltage switching transistor, to protect sensing circuit to exempt from In the injury of high-intensitive erasing voltage.But, three-dimensional nand memory may lack in plane nand memory structure, be used to High voltage switch circuit is provided to reduce the region PWI of area consumption.

Therefore, in three-dimensional nand memory structure, high voltage switching transistor route consumes a large amount of area.At one In memory array embodiment with 8 bit lines, two XY switch transistors of every bit line configuration need 16 planes to open It closes transistor and these bit lines is electrically coupled to erasing voltage line or write-in reading pressure-wire.

Therefore, the area consumed in the switching transistor in need for reducing three-dimensional NAND memory array.

Summary of the invention

Difference embodiment disclosed in this invention reduces consumed in the switching transistor of three-dimensional NAND memory array Area.This three-dimensional NAND memory array has three-dimensional voltage switching transistor, this three-dimensional voltage switching transistor and plane electricity The transistor (such as the transistor being formed among substrate) that compresses switch is compared, and has lower stacking area (aggregate area).In some embodiments, three-dimensional NAND memory array and three-dimensional voltage switching transistor are all stored using vertical gate Device structure.

In one aspect of the invention, this integrated circuit includes the three-dimensional nand memory with multiple memory transistors Array, multiple bit lines wherein different bit lines is coupled to the different parts of three-dimensional NAND memory array, and are located at one and half Multiple transistors pair in conductor lamination (stack of semiconductor layers).Different layers in semiconductor laminated Different transistors pair including multiple pair of transistors.Each of multiple pair of transistors includes the first transistor and second Transistor, and this two has the first, second, and third source/drain endpoint.Wherein, the first transistor includes first and third Source/drain endpoint；Second transistor includes second and third source/drain endpoint.First source/drain endpoint electric property coupling To an erasing voltage line.Second source/drain terminal is electrically coupled in a plurality of write-in/reading pressure-wire corresponding one. Third source/drain terminal is electrically coupled in multiple bit lines corresponding one.

Among some embodiments of the present invention, first grid controls all the first transistors of multiple pair of transistors； And second grid controls all second transistors of multiple pair of transistors.

Among some embodiments of the present invention, whether first grid control multiple bit lines are coupled to multiple pair of transistors The first source/drain endpoint；And second grid control multiple bit lines whether be coupled to the second source electrode of multiple pair of transistors/ Drain terminal.

Among some embodiments of the present invention, three-dimensional NAND memory array includes multiple semiconducting tape laminated construction (stacks of semiconductor strips), setting come as memory transistors different in three-dimensional NAND memory array Transistor channels.It includes: the first semiconducting tape laminated construction that this is semiconductor laminated, and configuration comes as multiple pair of transistors The transistor channels of different the first transistors；And the second semiconducting tape laminated construction, configuration come as multiple transistors pair The transistor channels of middle difference second transistor.

A plurality of semiconductor bar among some embodiments of the present invention, in the first semiconducting tape laminated construction Band, a plurality of semiconducting tape in the second semiconducting tape laminated construction and be located at multiple conductive strap laminated construction in A plurality of semiconducting tape, share multiple plan-positions (plane positions).

Among some embodiments of the present invention, the not corresponding lines in multiple bit lines is electrically coupled to three-dimensional nand memory The Different Plane position of array.

Some embodiments of the present invention further include being used to erasing voltage line first group of voltage of generation, and to write-in/reading Pressure-wire is taken to generate the circuit of second group of voltage.

A plurality of semiconducting tape among some embodiments of the present invention, in the first semiconducting tape laminated construction It is electrically coupled to bit line adjacent thereto in multiple bit lines.

A plurality of semiconducting tape among some embodiments of the present invention, in the first semiconducting tape laminated construction It is electrically coupled on bit line not adjacent thereto in multiple bit lines.

Some embodiments of the present invention further include the circuit for executing following actions:

(i) multiple the first transistors are opened；And close multiple second transistors；And

(ii) multiple second transistors are opened；And close multiple the first transistors.

Another aspect of the present invention is the method for operating multiple bit lines.These bit lines are electrically coupled to brilliant comprising multiple storages The three-dimensional NAND memory array of body pipe, wherein different bit lines is electrically coupled to the different portions of three-dimensional NAND memory array Position, the method include

Switchably bit line is electrically coupled to one of following by (switchably):

(i) first group of voltage passes through the of an at least first memory operational configurations in three-dimensional NAND memory array One group of multiple transistor is coupled, wherein first group of multiple transistor has first semiconducting tape laminated construction； And

(ii) second group of voltage passes through the of an at least second memory operational configurations in three-dimensional NAND memory array Two groups of multiple transistors are coupled, wherein second group of multiple transistor has second semiconducting tape laminated construction； And second memory operational configurations are different with first memory operational configurations.

Among some embodiments of the present invention, semiconducting tape in the first semiconducting tape laminated construction, quilt The transistor channels come as different crystal pipe in first group of multiple transistor are set；Positioned at the second semiconducting tape laminated construction In semiconducting tape, be provided to the transistor channels as different crystal pipe in second group of multiple transistor；And it is three-dimensional NAND memory array includes multiple semiconducting tape laminated construction, is arranged to deposit as difference in three-dimensional NAND memory array Store up the transistor channels of transistor.It is a plurality of in the first semiconducting tape lamination among some embodiments of the present invention Semiconducting tape, a plurality of semiconducting tape in the second semiconducting tape laminated construction and to be located at multiple conductive straps folded A plurality of semiconducting tape in layer structure, shares multiple plan-positions.Wherein, it is logical to correspond to different crystal pipe for different plan-positions Road is arranged.

Among some embodiments of the present invention, first memory operational configurations include erasing；And second memory operates Kenel includes at least one of both write-in and reading.Among some embodiments of the present invention, first memory operational configurations Including erasing；And second memory operational configurations include write-in and read.

Among some embodiments of the present invention, the not corresponding lines in multiple bit lines is coupled to three-dimensional NAND memory array In Different Plane position.

Some embodiments of the present invention, further include generate be suitable for first memory operational configurations first group of voltage and The circuit of second group of voltage suitable for second memory operational configurations.

A plurality of semiconducting tape among some embodiments of the present invention, in the first semiconducting tape laminated construction It is electrically coupled to the bit line adjacent thereto connect in multiple bit lines.

A plurality of semiconducting tape among some embodiments of the present invention, in the first semiconducting tape laminated construction It is electrically coupled to the bit line not adjacent thereto connect in multiple bit lines.For example, write-in and/or reading storage operation, Ke Yitong Odd number or even bitlines/whole bit line are crossed to execute.

Some embodiments of the present invention further include executing following actions with circuit:

(i) first group of multiple transistor is opened, and closes second group of multiple transistor, thus couples first group of voltage To multiple bit lines at least to carry out first memory operational configurations；And

(ii) multiple second transistors are opened, and close multiple the first transistors, are thus coupled to second group of voltage Multiple bit lines are at least to carry out second memory operational configurations.

An additional aspect of the present invention is a kind of integrated circuit, comprising:

One three-dimensional NAND memory array, has multiple memory transistors, multiple bit lines, wherein the difference in multiple bit lines Bit line is electrically coupled to the different parts, multiple in the first semiconducting tape laminated construction of three-dimensional NAND memory array The first transistor, and multiple second transistors in the second semiconducting tape laminated construction.Multiple bit lines are switchably The only one being coupled in multiple groups voltage.This multiple groups voltage includes at least:

(i) first group of voltage is by least one of three-dimensional NAND memory array first memory operational configurations First group of multiple transistor coupled；And

(ii) second group of voltage passes through at least one of three-dimensional NAND memory array second memory operational configurations Second group of multiple transistor are coupled, and second memory operational configurations and first memory operational configurations are different.

Another aspect of the invention is the method for making this integrated circuit.

To enable the above embodiment of the present invention and other objects, features and advantages to be clearer and more comprehensible, spy lifts several preferred Embodiment, and cooperate appended attached drawing, it is described in detail below:

Detailed description of the invention

Fig. 1 is painted the integrated circuit with three-dimensional NAND memory array and the voltage switching transistor in substrate Block diagram；

Fig. 2 is painted another block diagram of the integrated circuit of Fig. 1, will be located at the voltage switching transistor in substrate It is depicted as that there is relatively large size；

Fig. 3 is painted a kind of structural perspective of system vertical gate NAND flash memory cubic memory array, can use Carry out the embodiment of the cubic memory array as Fig. 1；

Fig. 4 is painted a pair of structural perspective for being located at and can be applied to the voltage switching transistor in Fig. 1 in substrate；

Fig. 5 is painted the structural perspective of the multipair voltage switching transistor that can be applied in Fig. 1 and be located in substrate；

Fig. 6 is painted the side of the integrated circuit with three-dimensional NAND memory array and vertical gate voltage switching transistor Frame schematic diagram；

Fig. 7 is painted another block diagram of the integrated circuit of Fig. 6, and vertical gate voltage switching transistor is painted At with relatively small size；

Fig. 8 is painted the more detailed block diagram of the integrated circuit of Fig. 6, also shows that multiple groups vertical gate voltage switch is brilliant Body pipe and multiple groups fall pad (landing pads)；

Fig. 9 is painted the structural perspective of an embodiment of the integrated circuit of Fig. 8；

Figure 10 is painted bit line in the integrated circuit of Fig. 9 and bit line falls the structural perspective of pad；

Figure 11 is painted the structure perspective of first group of vertical gate voltage switching transistor in the integrated circuit of Fig. 9 Figure；

Figure 12 is painted the write-in of the integrated circuit in Fig. 9 and reads pressure-wire and write-in and read pressure-wire and falls The structural perspective of pad；

Figure 13 is painted the structure perspective of second group of vertical gate voltage switching transistor of the integrated circuit in Fig. 9 Figure；

The structure that Figure 14 is painted the erasing voltage line of the integrated circuit in Fig. 9 and erasing voltage line falls pad is had an X-rayed Figure；

Figure 15 is painted another detailed block diagram of the integrated circuit of Fig. 6, shows that it passes through odd number or even bitlines It is accessed, rather than is as shown in Figure 8 accessed by whole bit lines；

Figure 16 is painted the write-in of the integrated circuit in Figure 15 and reads pressure-wire and write-in and read pressure-wire and falls Pad structural perspective, accessed by even bitlines, rather than deposited as shown in figure 12 by whole bit lines It takes；

Figure 17 is painted the write-in of the integrated circuit in Figure 15 and reads pressure-wire and write-in and read pressure-wire and falls Pad structural perspective, accessed by odd bit lines, rather than deposited as shown in figure 12 by whole bit lines It takes；

The structure that Figure 18 is painted the erasing voltage line of the integrated circuit in Figure 15 and erasing voltage line falls pad is saturating View is accessed by even bitlines, rather than is accessed as shown in figure 14 by whole bit lines；

The structure that Figure 19 is painted the erasing voltage line of the integrated circuit in Figure 15 and erasing voltage line falls pad is saturating View is accessed by odd bit lines, rather than is accessed as shown in figure 14 by whole bit lines；

The even number that Figure 20 is painted the integrated circuit in Figure 15 falls the structural perspective of pad, is used to alternate figures 16 and figure Even number depicted in 18 falls pad；

The odd number that Figure 21 is painted the integrated circuit in Figure 15 falls the structural perspective of pad, is used to alternate figures 17 and figure Odd number depicted in 19 falls pad；

Figure 22 is painted the wiring layer (routing in the integrated circuit that Fig. 8 is accessed with whole bit lines Layer wiring (routing conductive lines) block diagram).

The wiring box that Figure 23 is painted another wiring layer in the integrated circuit that Fig. 8 is accessed with whole bit lines shows It is intended to；

Figure 24 is painted the wiring box of the wiring layer of the integrated circuit accessed positioned at Figure 15 with even number and odd bit lines Schematic diagram；

Figure 25 is painted the wiring of another wiring layer of the integrated circuit accessed positioned at Figure 15 with even number and odd bit lines Block diagram；

Figure 26 is painted the simplified electrical circuit diagram that can be utilized for a pair of of vertical gate switching transistor of write-in or read operation；

Figure 27 is painted in the integrated circuit that Fig. 8 is accessed with whole bit lines, can be utilized for being written or reading behaviour The simplified electrical circuit diagram for the multipair vertical gate switching transistor made；

Figure 28 is painted in the integrated circuit that Figure 15 is accessed with even number and odd bit lines, can be utilized for write-in or The simplified electrical circuit diagram of the multipair vertical gate switching transistor of read operation；

Figure 29 is painted the simplified electrical circuit diagram that can be utilized for a pair of of vertical gate switching transistor of erasing operation；

Figure 30 is painted in the integrated circuit that Fig. 8 is accessed with whole bit lines, can be utilized for the more of erasing operation To the simplified electrical circuit diagram of vertical gate switching transistor；

Figure 31 is painted in the integrated circuit that Figure 15 is accessed with even number and odd bit lines, can be utilized for erasing behaviour The simplified electrical circuit diagram for the multipair vertical gate switching transistor made；

Figure 32 is painted the simplified electrical circuit diagram of the integrated circuit with vertical gate switching transistor；

Figure 33 is painted the cross-sectional view of the structure that can produce the different mask combinations in the area Luo Zhe of different depth.

[symbol description]

20: laminated construction 22,22.0-22.7: dielectric layer

24,24.0-24.7: conductive layer 26: dielectric substrate

28: etch stop layer 30: hard exposure mask

32,32.0-32.7: contact openings 38: opening etching area

40: closing 52: the first photoresist exposure mask of exposure mask

54: the second photoresist exposure mask, 56: the second photoresist exposure mask

100: three-dimensional NAND memory array

112,113,114,115: semiconductor circuits

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A: bit line contact pad

109,119: tandem selection gate structure 120: global bit line

125-1 ... 125-N: wordline 126,127: ground connection selection line

130,160-167: voltage switching transistor 132: pressure-wire is read

134: erasing/precharge/masking pressure-wire

140,146,148: conductive plunger

142: first crystal tube grid 144: second transistor grid

150,152,154: source/drain

230: vertical gate voltage switching transistor

232: global bit line falls pad

234: the first groups of vertical gate voltage switching transistors

236: write-in and reading pressure-wire fall pad

238: the second groups of vertical gate voltage switching transistors

240,265: erasing/precharge/masking pressure-wire falls pad

244: the first odd number group vertical gate voltage switching transistors

245: the first even number set vertical gate voltage switching transistors

246: odd number write-in and reading pressure-wire fall pad

247: even number write-in and reading pressure-wire even number fall pad

248: the second odd number group vertical gate voltage switching transistors

249: the second even number set vertical gate voltage switches

250: odd number fall erasing/precharge/masking pressure-wire pad

251: even number erasing/precharge/masking pressure-wire falls pad

252: odd number write-in and reading pressure-wire

253,255 even number erasings/precharge/masking pressure-wire

254: odd number erasing/precharge/masking voltage erasing/precharge/masking pressure-wire

BIAS_SEL 262、BIAS_SEL 255、BIAS_SEL 272、BIAS_SEL 273、BIAS_SEL 274、 BIAS_SEL 275, BIAS_SEL 310, BIAS_SEL 320: pressure-wire

312,314,322,324: transistor 322: second transistor

350,351: sensing amplifier BL_BIAS 340: pressure-wire

300,301,330,459, BL1-BL8: bit line

458: plane decoder

460: three-dimensional NAND Flash memory array

461: line decoder 462: wordline

463: page buffer 464: tandem selection line

465: bus

466: column decoder data go out/input structure

468: bias arranges voltage 469: state machine

471: Data In-Line 474: other circuits

472: DOL Data Output Line 475: integrated circuit

BLi1, BLi3, BLi5, BLi7: pressure-wire is read

P1-P8: semiconducting tape ML1, ML2, ML3: metal layer

Specific embodiment

The following description content will be referring to specific constructive embodiment and method.But it must be noted that as disclosed below Content, not to limit the invention to specific constructive embodiment and method, other features, member are still can be used in the present invention Part, method and embodiment are implemented.The disclosure of preferred embodiment is not used merely to clearly illustrate technical characteristic of the invention To limit appended claims protection scope of the present invention.Persond having ordinary knowledge in the technical field of the present invention is not taking off From in the spirit and scope of the present invention, when various change and modification can be made.Among different embodiments, identical element will be with Identical component symbol is indicated.

Fig. 1 is painted the integrated circuit with three-dimensional NAND memory array and the voltage switching transistor in substrate Block diagram.

Three-dimensional NAND memory array 100 is coupled to the voltage switching transistor in substrate by global bit line 120 130.According to the switching mode of transistor 130, by global bit line 120 be coupled to for carry write-in and read voltage write-in and Pressure-wire 132 is read, or is coupled to the erasing voltage line 134 for carrying erasing voltage.

Fig. 2 is painted another block diagram of the integrated circuit of Fig. 1, will be located at the voltage switching transistor in substrate It is depicted as that there is relatively large size.

Voltage switching transistor 130 in substrate is depicted as the size (X- with an X-direction Dimension), corresponding with the size of X-direction of three-dimensional NAND memory array 100.Voltage switch in substrate Transistor 130 is depicted as the aggregation size (aggregate Y-dimension) of the Y direction with about 150 microns (μm).

Fig. 3 is painted a kind of structural perspective of system vertical gate NAND flash memory cubic memory array, can use Carry out the embodiment of the cubic memory array as Fig. 1.

This element includes laminated construction (the stacks of active of the active lines in the active layers of array Lines it), and with insulated circuit (insulating lines) intermeshes.Insulating materials is removed in attached drawing, thus Expose other structures.Such as it will be exhausted between the semiconductor circuits (semiconductor lines) for being located at same tier structure Edge route, and insulated circuit between different semiconductor circuits laminated construction are removed.

In the present embodiment, multiple tier array is formed on an insulating layer, and including a plurality of wordline 125-1 ..., 125-N, It is conformal with above-mentioned multiple laminated construction.Above-mentioned multiple laminated construction include being located on multiple plane layers (multiple planes) A plurality of semiconductor circuits 112,113,114 and 115.Semiconductor circuits on same level layer pass through bit line contact pad (such as bit line contact pads 102B) mutual electric property coupling.

Bit line contact pad 112A, 113A, 114A and 115A positioned at attached drawing proximal end is by semiconductor circuits, such as semiconductor line Road 112,113,114 and 115 disconnects.As shown, bit line contact pad 112A, 113A, 114A and 115A pass through inter-layer connectors (interlayer connectors) is electrically connected to the not corresponding lines being located above in patterned metal layer (such as ML3), and Decoding circuit is connected to via high-voltage switch transistor to select the plane layer in array.These bit line contacts pad 112A, 113A, 114A and 115A can be formed on ladder-like matrix structure.And by pattern while defining multiple laminated construction Change.

Bit line contact pad 102B, 103B, 104B and 105B positioned at attached drawing distal end is by semiconductor circuits, such as semiconductor line Road 112,113,114 and 115 disconnects.As shown, bit line contact pad 102B, 103B, 104B and 105B pass through inter-layer connectors It is electrically connected to the not corresponding lines being located above in patterned metal layer (such as ML3), and is connected via high-voltage switch transistor Decoding circuit is connected to select the plane layer in array.These bit line contacts pad 102B, 103B, 104B and 105B can be formed in On ladder-like matrix structure.And it is patterned while defining multiple laminated construction.

In the present embodiment, each semiconductor circuits laminated construction be electrically coupled to bit line contact pad 112A, 113A, 114A and 115A or bit line contact pad one of 102B, 103B, 104B and 105B, rather than two.Semiconductor circuits (bit line) Laminated construction (stack of semiconductor lines) has bit line end-to-source electrode line end and source electrode line end-to-position One of two kinds of line end opposite trends.For example, semiconductor circuits laminated construction 112,113,114 and 115 has bit line end- Extremely-source electrode line end trend；And semiconductor circuits laminated construction 102,103,104 and 105 has source electrode line end-to-bit line end Trend.

Semiconductor circuits laminated construction 112,113,114 and 115 one end by bit line contact pad 112A, 113A, 114A and 115A is disconnected, and is passed through tandem selection gate structure 119, ground connection selection line 126, wordline and (is selected by 125-1 to 125-N), ground connection Line 127, the other end are disconnected by source electrode line 128.Semiconductor circuits laminated construction 112,113,114 and 115 does not touch bit line and connects Touch pad 102B, 103B, 104B and 105B.

Semiconductor circuits laminated construction 102,103,104 and 105 one end by bit line contact pad 102B, 103B, 104B and 105B is disconnected, and is passed through tandem selection gate structure 109, ground connection selection line 127, wordline and (is selected by 125-1 to 125-N), ground connection Line 126, the other end are disconnected by source electrode line (being covered by the other parts of attached drawing).Semiconductor circuits laminated construction 102,103, 104 and 105 do not touch bit line contact pad 112A, 113A, 114A and 115A.

One storage material layer is configured at the table of semiconductor circuits 12-115 and 102-105 Yu wordline 125-1 to both 125-N In the interface area in face crosspoint.It is similar with wordline to be grounded selection line 126 and 127, it is all conformal with these laminated construction.

One end of each semiconductor circuits laminated construction is disconnected by bit line contact pad, and the other end is disconnected by source electrode line.Example As one end of semiconductor circuits laminated construction 112,113,114 and 115 is broken by bit line contact pad 112A, 113A, 114A and 115A It opens, the other end is disconnected by source electrode line 128.

Bit line and tandem selection line are formed on metal layer ML1, ML2 and ML3.Bit line is coupled by high voltage switching transistor To the plane decoder (not being painted) for being located at circuit peripheral region.Tandem selection line is coupled to the tandem selection positioned at circuit peripheral region Line decoder (is not painted).

Being grounded selection line 126 and 127 can be in the same processing step for defining wordline 125-1 to 125-N by pattern Change.Ground connection selection element is formed in multiple laminated construction and is grounded the interface area of the surface crosswise point of the two of selection line 126 and 127 On.Tandem selection gate structure 119 and 109 can be in the same processing step for defining wordline 125-1 to 125-N by pattern Change.Tandem selection element is formed in the surface crosswise point of both multiple laminated construction and tandem selection gate structure 119 and 109 In the area of interface.These elements are coupled to decoding circuit, and thus selection is located at the tandem in array in specific laminated construction.

Fig. 4 is painted a pair of structural perspective for being located at and can be applied to the voltage switching transistor in Fig. 1 in substrate.

Conductive plunger 140 couples the voltage between universe wordline and source/drain 150.

First crystal tube grid 142 switchably electric property coupling source/drain 150 and source/drain 152.When the first crystalline substance When body tube grid 142 receives a cut-in voltage, the first transistor electric property coupling conductive plunger 140 to conductive plunger 146.When first When transistor gate 142 receives a closing voltage, the first transistor is electrically isolated by conductive plunger 140 and conductive plunger 146.It leads Electric plug 146 is electrically coupled to for carrying write-in and reading write-in and the reading pressure-wire of voltage.

Second transistor grid 144 switchably electric property coupling source/drain 150 and source/drain 154.When the second crystalline substance When body tube grid 144 receives a cut-in voltage, second transistor electric property coupling conductive plunger 140 to conductive plunger 148.When second When transistor gate 144 receives a closing voltage, second transistor is electrically isolated by conductive plunger 140 and conductive plunger 148.It leads Electric plug 148 is electrically coupled to the erasing voltage line for carrying erasing voltage.

The first crystal tube grid 142 and second transistor grid 144 of voltage switching transistor in substrate are drawn It is shown as the Y direction size with about 1.6 microns.This Y direction size is corresponding with the size of grid length.Source/drain 150, source/drain 152 and source/drain 154 are depicted as the Y direction size with about 2.1 microns.

Fig. 5 is painted the structural perspective of the multipair voltage switching transistor that can be applied in Fig. 1 and be located in substrate.

It is each that the single to voltage of drawn formula in Fig. 4 can be to the voltage switching transistor 160-167 being located in substrate The embodiment of switching transistor is electrically coupled to an erasing voltage line, respective bit lines, a other write-in and reading pressure-wire. The case of these multipair voltage switching transistors highlights the total amount that the voltage switching transistor in substrate accounts for chip area.

Fig. 6 is painted the side of the integrated circuit with three-dimensional NAND memory array and vertical gate voltage switching transistor Frame schematic diagram.

Three-dimensional NAND memory array 100 is coupled to vertical gate voltage switching transistor 230 by global bit line 120. According to the switching mode of transistor 230, global bit line 120 is coupled to for carrying write-in and reading the write-in and reading of voltage Pressure-wire 132, or be coupled to for carrying erasing/precharge/masking (erase/pre-charge/shielding) voltage Erasing/precharge/masking pressure-wire 134.Wherein, it is pre-charged and covers voltage and be also applied for write-in and/or read mode.

In some other embodiments, for carrying erasing/precharge/masking voltage erasing/precharge/masking voltage Line can be used to carrying erasing/precharge erasing/precharge voltage line, for carrying the erasing/screening of erasing/masking voltage Cover pressure-wire or for carrying replaced the erasing voltage line of erasing voltage.In some other embodiments, pre-charge pressure and/or Masking voltage can be carried by other one or more groups of pressure-wires.

Vertical gate voltage switching transistor 230 can separate erasing voltage and other circuits, such as sensing amplifier.

Fig. 7 is painted another block diagram of the integrated circuit of Fig. 6, by vertical gate voltage switching transistor 230 It is depicted as with relatively small size.

Vertical gate voltage switching transistor 230 is depicted as the size with an X-direction, with three-dimensional nand memory The size of the X-direction of array 100 is corresponding.Vertical gate voltage switching transistor 230 is depicted as the Y with about 2 microns The aggregation size of axis direction is essentially less than located at about 150 microns of embodiment of Y-axis of the voltage switching transistor 130 in substrate Direction adds up size.

Semiconductor laminated structure in three-dimensional NAND memory array 100 and it is located at vertical gate voltage switching transistor Semiconductor laminated structure in 230 can share the processing steps such as formation and patterning, therefore vertical gate voltage switch crystal Pipe 230 is not needed beyond additional technical steps needed for making three-dimensional NAND memory array 100.

Fig. 8 is painted the more detailed block diagram of the integrated circuit of Fig. 6, more shows that multiple groups vertical gate voltage switch is brilliant Body pipe and multiple groups fall pad.

Three-dimensional NAND memory array 100 is coupled to global bit line by global bit line 120 and falls pad 232.Global bit line It falls pad 232 and is electrically coupled to first group of vertical gate voltage switching transistor 234 and second group of vertical gate voltage switch crystalline substance One of source/drain endpoint in 238 the two of body pipe.

Switchably electric property coupling global bit line falls pad 232 and writes first group of vertical gate voltage switching transistor 234 Enter and read pressure-wire and falls pad 236.When first group of vertical gate voltage switching transistor 234 is turned on, first group vertical Grid voltage switching transistor 234 by global bit line fall pad 232 be electrically coupled to write-in and read pressure-wire fall pad 236； When first group of vertical gate voltage switching transistor 234 is closed, first group of vertical gate voltage switching transistor 234 will be complete Domain bit line falls pad 232 and write-in and reads pressure-wire to fall pad 236 electrically isolated.It reads pressure-wire and falls the electrical coupling of pad 236 It is connected to for carrying write-in and reading write-in and the reading pressure-wire 132 of voltage.

Switchably electric property coupling global bit line falls pad 232 and wipes second group of vertical gate voltage switching transistor 238 Except/precharge/masking pressure-wire falls pad 240.When second group of vertical gate voltage switching transistor 238 is turned on, second Global bit line is fallen pad 232 and is electrically coupled to erasing/precharge/masking voltage by group vertical gate voltage switching transistor 238 Line falls pad 240；When second group of vertical gate voltage switching transistor 238 is closed, second group of vertical gate voltage switch It is electrically isolated that global bit line is fallen pad 232 and erasing/precharge/masking pressure-wire falls pad 240 by transistor 238.Erasing/pre- Charging/masking pressure-wire fall pad 240 be electrically coupled to for carry the erasing/precharge of erasing/precharge/masking voltage/ Cover pressure-wire 134.

First group of vertical gate voltage switching transistor 234 and second group of vertical gate voltage switching transistor 238 will be used It is separated to carry erasing/precharge/masking voltage erasing/precharge/masking pressure-wire 134 with other circuits.Other circuits It can be, such as the sensing amplifier connected via being written and reading pressure-wire 132.

Fig. 9 is painted the structural perspective of an embodiment of the integrated circuit of Fig. 8.

Accumulation block (aggregated blocks) in Fig. 9 is depicted as the simplified perspective view of Figure 10 to Figure 14 respectively. Three-dimensional NAND memory array (not being painted) is coupled to global bit line by global bit line 120 and falls pad 232.Global bit line is fallen Pad 232 is electrically coupled to first group of vertical gate voltage switching transistor 234 and second group of vertical gate voltage switching transistor One of source/drain endpoint in 238 the two.First group of vertical gate voltage switching transistor 234 switchably electric property coupling Global bit line, which falls pad 232 and write-in and reads pressure-wire, falls pad 236.Write-in and reading pressure-wire fall the electrical coupling of pad 236 It is connected to for carrying write-in and reading write-in and the reading pressure-wire 242 of voltage.Second group of vertical gate voltage switching transistor 238 switchably electric property coupling global bit line falls pad 232 and erasing/precharge/masking pressure-wire falls pad 240.Erasing/pre- Charging/masking pressure-wire fall pad 240 be electrically coupled to for carry the erasing/precharge of erasing/precharge/masking voltage/ Cover pressure-wire 265.

In the structure of different blocks, such as in semiconducting tape laminated construction, insulating layer can be with other layer of phase It is same or different.Adoptable representativeness insulating materials includes Si oxide, silicon nitride, silicon oxynitride, silicate or other materials Material.Low-k (low-k) material with the dielectric constant less than silica, such as SiCHO can be used_x.It can also To use the high dielectric constant material with the dielectric constant higher than silica, such as hafnium oxide (HfO_x), nitrogen oxidation hafnium (HfON), aluminium oxide (AlO_x), ru oxide (RuO_x) or titanium oxide (TiO_x)。

In the structure of different blocks, such as the semiconductor layer in semiconducting tape laminated construction, it can be with other layers It is identical or different.Can be used to be contained in the representative materials in semiconductor includes that doped or undoped polysilicon is (workable Dopant, such as arsenic (As), phosphorus (P), boron (B)), the combination of semiconductor structure, metal silicide (silicides, including silication Titanium (TiSi), cobalt silicide (CoSi)), conductor oxidate (including indium zinc oxide (InZnO), indium gallium zinc (InGaZnO)) And the combination of semiconductor and metal silicide.

In the structure of different blocks, such as in bit line and conductive plunger, conductor layer can be metal, conductive compound Or the combination of materials described below, including aluminium (Al), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN), nitrogen Change tantalum (TaN), tantalum nitride aluminium (TaAlN) or other materials.Conductor layer can be doping after it is conductive without semiconductor The semiconductor layer of characteristic.

Fall pad, semiconducting tape and pressure-wire quantity can according to the capacity of three-dimensional NAND memory array come into Row adjustment.

Figure 10 is painted bit line in the integrated circuit of Fig. 9 and bit line falls the structural perspective of pad.

Three-dimensional NAND memory array (not being painted) is coupled to global bit line by a plurality of global bit line 120 and falls pad 232. These global bit lines 120 are to be electrically coupled to the conducting wire that a global bit line falls pad 232 respectively by one group of conductive plunger.Example Such as, each in bit line BL1-BL8 is electrically coupled to falls wherein one and half leading in pad 232 positioned at global bit line respectively Body band P1-P8.Semiconducting tape P1-P8 adjacent in pad 232 is fallen by intermediate insulation band each other positioned at global bit line It is electrically insulated.

Figure 11 is painted the structure perspective of first group of vertical gate voltage switching transistor in the integrated circuit of Fig. 9 Figure.

Switchably electric property coupling global bit line falls pad 232 and writes first group of vertical gate voltage switching transistor 234 Enter and read pressure-wire and falls pad 236.First group of vertical gate voltage switching transistor 234 includes semiconducting tape P1-P8, It is electrically insulated from by intermediate insulation band.First group of vertical gate voltage switching transistor 234 can cover oxide, by This will be used to be isolated as the semiconducting tape P1-P8 of channel layer with the conductive gate material of top.This oxide can be more Layer structure, such as Si oxide/silicon nitride/Si oxide (ONO), Si oxide/low dielectric layer with high dielectric constant/Si oxide (O/high-k/O), it is possible to provide high dielectric constant and the doubt for reducing capacity fall off.

Figure 12 is painted the write-in of the integrated circuit in Fig. 9 and reads pressure-wire and write-in and read pressure-wire and falls The structural perspective of pad.

Write-in and reading pressure-wire 242 are to be electrically coupled to one of write-in respectively by one group of conductive plunger and read Pressure-wire falls the conducting wire of pad 236.It falls semiconducting tape P1-P8 adjacent in pad 236 positioned at write-in and reading pressure-wire and borrows Intermediate insulation band is helped to be electrically insulated from.

When first group of vertical gate voltage switching transistor 234, which receives one, opens grid voltage, universe position can will be located at The semiconducting tape P1-P8 that line is fallen in pad 232, which is electrically coupled to, falls partly leading in pad 236 positioned at write-in and reading pressure-wire Body band P1-P8.For example, will be located at the semiconducting tape P1 that falls in pad 232 of global bit line be electrically coupled to positioned at write-in and It reads pressure-wire and falls the semiconducting tape P1 in pad 236.Other plane layers of semiconducting tape also electrical property coupling in a manner of one by this It connects.

When first group of vertical gate voltage switching transistor 234, which receives one, closes grid voltage, universe position can will be located at The semiconducting tape P1-P8 and fall the semiconducting tape in pad 236 positioned at being written and reading pressure-wire that line is fallen in pad 232 P1-P8 is electrically isolated.For example, the semiconducting tape P and be located at write-in and reading voltage that global bit line is fallen in pad 232 will be located at It is electrically isolated that line falls the semiconducting tape P1 in pad 236.Other plane layers of semiconducting tape also by this in a manner of one electrically point From.

Figure 13 is painted the structure perspective of second group of vertical gate voltage switching transistor of the integrated circuit in Fig. 9 Figure.

Switchably electric property coupling global bit line falls pad 232 and wipes second group of vertical gate voltage switching transistor 238 Except/precharge/masking pressure-wire falls pad 240.In addition to this, second group of vertical gate voltage switching transistor 238 and first What the structure of group vertical gate voltage switching transistor 234 can be similar to.

Figure 14 is painted erasing/precharge/masking pressure-wire and the erasing/precharge/screening of the integrated circuit in Fig. 9 Cover the structural perspective that pressure-wire falls pad.

Erasing/precharge/masking pressure-wire 265 is to be electrically coupled to one of wiping respectively by one group of conductive plunger Except/precharge/masking pressure-wire falls the conducting wire of pad 240.It is fallen positioned at erasing/precharge/masking pressure-wire adjacent in pad 240 Semiconducting tape P1-P8 be electrically insulated from by intermediate insulation band.

When second group of vertical gate voltage switching transistor 238, which receives one, opens grid voltage, universe position can will be located at The semiconducting tape P1-P8 that line is fallen in pad 232 is electrically coupled to be fallen in pad 240 positioned at erasing/precharge/masking pressure-wire Semiconducting tape P1-P8.It is located at for example, the semiconducting tape P1 that global bit line is fallen in pad 232 will be located at and be electrically coupled to Erasing/precharge/masking pressure-wire falls the semiconducting tape P1 in pad 240.Other plane layers of semiconducting tape are also with this One mode electric property coupling.

When second group of vertical gate voltage switching transistor 238, which receives one, closes grid voltage, universe position can will be located at The semiconducting tape P1-P8 and the semiconductor in pad 240 is fallen positioned at erasing/precharge/masking pressure-wire that line is fallen in pad 232 Band P1-P8 is electrically isolated.For example, the semiconducting tape P1 and be located at erasing/preliminary filling that global bit line is fallen in pad 232 will be located at It is electrically isolated that electricity/masking pressure-wire falls the semiconducting tape P1 in pad 240.Other plane layers of semiconducting tape also with this one Mode is electrically isolated.

Figure 15 is painted another detailed block diagram of the integrated circuit of Fig. 6, shows that it passes through odd number or even bitlines It is accessed, rather than is as shown in Figure 8 accessed by whole bit lines.

Three-dimensional NAND memory array 100 is coupled to global bit line by global bit line 120 and falls pad 232.Global bit line Pad 232 is fallen to be electrically coupled on one of source/drain of following four group transistors.This four group transistor are as follows: the first odd number group Vertical gate voltage switching transistor 244, the first even number set vertical gate voltage switching transistor 245, the second odd number group are vertical Grid voltage switching transistor 248 and the second even number set vertical gate voltage switching transistor 249.

Switchably electric property coupling global bit line falls pad 232 to first odd number group vertical gate voltage switching transistor 244 Pressure-wire is written and read with odd number falls pad 246.When the first odd number group vertical gate voltage switching transistor 244 is opened, First odd number group vertical gate voltage switching transistor 244 can by global bit line fall pad 232 be electrically coupled to odd number write-in and It reads pressure-wire and falls pad 246.When the first odd number group vertical gate voltage switching transistor 244 is closed, the first odd number group is hung down Global bit line can be fallen pad 232 and write-in and read pressure-wire odd number by straight grid voltage switching transistor 244 falls 246 electricity of pad Property separation.Odd number write-in and read pressure-wire fall pad 246 be electrically coupled to for carry write-in and read voltage odd number write Enter and read pressure-wire 252.

Switchably electric property coupling global bit line falls pad 232 to first even number set vertical gate voltage switching transistor 245 Pressure-wire even number is written and read with even number falls pad 247.When the first even number set vertical gate voltage switching transistor 245 is opened When, global bit line can be fallen pad 232 and be electrically coupled to even number write-in by the first even number set vertical gate voltage switching transistor 245 And it reads pressure-wire even number and falls pad 247.When the first even number set vertical gate voltage switching transistor 245 is closed, first is even Global bit line can be fallen pad 232 by array vertical gate voltage switching transistor 245 and even number is written and reads pressure-wire even number It is electrically isolated to fall pad 247.Even number write-in and reading pressure-wire even number fall pad 247 and are electrically coupled to for carrying write-in and reading The even number of voltage is taken to be written and read pressure-wire 253.

Switchably electric property coupling global bit line falls pad 232 to second odd number group vertical gate voltage switching transistor 248 Pad 250 is fallen with odd number erasing/precharge/masking pressure-wire.When the second odd number group vertical gate voltage switching transistor 248 is opened Global bit line can be fallen pad 232 and be electrically coupled to odd number wiping by Qi Shi, the second odd number group vertical gate voltage switching transistor 248 Except/precharge/masking pressure-wire falls pad 250.When the second odd number group vertical gate voltage switching transistor 248 is closed, the Global bit line can be fallen pad 232 and odd number erasing/precharge/masking by two odd number group vertical gate voltage switching transistors 248 It is electrically isolated that pressure-wire falls pad 250.Odd number erasing/precharge/masking pressure-wire falls pad 250 and is electrically coupled to for carrying Erasing/precharge/masking voltage odd number erasing/precharge/masking pressure-wire 254.

Switchably electric property coupling global bit line falls pad 232 to second even number set vertical gate voltage switching transistor 249 Pad 251 is fallen with erasing/precharge/masking pressure-wire.When the second even number set vertical gate voltage switching transistor 249 is opened When, global bit line can be fallen pad 232 and be electrically coupled to even number wiping by the second even number set vertical gate voltage switching transistor 249 Except/precharge/masking pressure-wire falls pad 251.When the second even number set vertical gate voltage switching transistor 249 is closed, the Global bit line can be fallen pad 232 and even number erasing/precharge/masking by two even number set vertical gate voltage switching transistors 249 It is electrically isolated that pressure-wire falls pad 251.Even number erasing/precharge/masking pressure-wire falls pad 251 and is electrically coupled to for carrying Erasing/precharge/masking voltage even number erasing/precharge/masking pressure-wire 255.

First odd number group vertical gate voltage switching transistor 244, the first even number set vertical gate voltage switching transistor 245, the second odd number group vertical gate voltage switching transistor 248 and the second even number set vertical gate voltage switching transistor 249 It can be with second group of vertical gate depicted in first group of vertical gate voltage switching transistor 234 depicted in Figure 11 and Figure 13 Pole tension switching transistor 238 is identical.In addition, because only needing the semiconducting tape of even number or odd number, it is other each half Conductive strap can be replaced with other materials.

First odd number group vertical gate voltage switching transistor 244, the first even number set vertical gate voltage switching transistor 245, the second odd number group vertical gate voltage switching transistor 248 and the second even number set vertical gate voltage switching transistor 249 By the erasing/precharge/masking voltage and other circuits on odd number erasing/precharge/masking pressure-wire 254 and 255, such as through By being written and reading the sensing amplifier of the connection of pressure-wire 252 and 253, separation.

Figure 16 is painted the write-in of the integrated circuit in Figure 15 and reads pressure-wire and write-in and read pressure-wire and falls Pad structural perspective, accessed by even bitlines, rather than deposited as shown in figure 12 by whole bit lines It takes.

Even number write-in and reading pressure-wire 253 are to be electrically coupled to one of even number respectively by one group of conductive plunger to write Enter and read the conducting wire that pressure-wire falls pad 247.Even number write-in and read pressure-wire fall pad 247 include semiconducting tape P2, P4, P6 and P8.

In addition to this, even number write-in and reading pressure-wire 253 are similar with being written and reading pressure-wire 242.Even number write-in and Read pressure-wire fall pad 247 can with write-in shown in Figure 12 and read pressure-wire to fall pad 236 similar.In addition, semiconductor Band P2, P4, P6 and P8 can be replaced with other materials.

Figure 17 is painted the write-in of the integrated circuit in Figure 15 and reads pressure-wire and write-in and read pressure-wire and falls Pad structural perspective, accessed by odd bit lines, rather than deposited as shown in figure 12 by whole bit lines It takes.

Odd number write-in and reading pressure-wire 252 are to be electrically coupled to one of odd number respectively by one group of conductive plunger to write Enter and read the conducting wire that pressure-wire falls pad 246.Odd number write-in and read pressure-wire fall pad 246 include semiconducting tape P1, P3, P5 and P7.

In addition to this, odd number write-in and reading pressure-wire 252 are similar with being written and reading pressure-wire 242.Odd number write-in and Read pressure-wire fall pad 246 can with write-in shown in Figure 12 and read pressure-wire to fall pad 236 similar.In addition, semiconductor Band P1, P3, P5 and P7 can be replaced with other materials.

Figure 18 be painted the integrated circuit in Figure 15 erasing/precharge/masking pressure-wire and erasing/precharge/ Masking pressure-wire falls the structural perspective of pad, is accessed by even bitlines, rather than passes through whole as shown in figure 14 Bit line is accessed.

Even number erasing/precharge/masking pressure-wire 255 is to be electrically coupled to one of them respectively by one group of conductive plunger Even number erasing/precharge/masking pressure-wire falls the conducting wire of pad 251.Even number erasing/precharge/masking pressure-wire falls pad 251 Including semiconducting tape P2, P4, P6 and P8.

In addition to this, even number erasing/precharge/masking pressure-wire 255 and erasing/precharge/masking voltage odd number are wiped Except/precharge/masking pressure-wire 254 is similar.Even number erasing/precharge/masking pressure-wire fall pad 251 can with shown in Figure 14 Erasing/precharge/that masking pressure-wire falls pad 240 is similar.In addition, semiconducting tape P2, P4, P6 and P8 can use other materials Material replaces.

The structure that Figure 19 is painted the erasing voltage line of the integrated circuit in Figure 15 and erasing voltage line falls pad is saturating View is accessed by odd bit lines, rather than is accessed as shown in figure 14 by whole bit lines.

Odd number erasing/precharge/masking pressure-wire 254 is to be electrically coupled to one of them respectively by one group of conductive plunger Odd number erasing/precharge/masking pressure-wire falls the conducting wire of pad 250.Odd number erasing/precharge/masking pressure-wire falls pad 250 Including semiconducting tape P1, P3, P5 and P7.

In addition to this, odd number erasing/precharge/masking pressure-wire 254 and the erasing of erasing/precharge/masking voltage/pre- Charging/masking pressure-wire 265 is similar.Odd number erasing/precharge/masking pressure-wire falls pad 250 can be with wiping shown in Figure 14 Except/precharge/masking pressure-wire falls pad 240 is similar.In addition, semiconducting tape P1, P3, P5 and P7 can be taken with other materials Generation.

The even number that Figure 20 is painted the integrated circuit in Figure 15 falls the structural perspective of pad, is used to alternate figures 16 and figure Even number depicted in 18 falls pad.

Unlike depicted in Figure 16 and Figure 18, even number is fallen into pad P2, P4, P6 and P8 and is arranged in a straight line, depicted in Figure 20 Even number falls pad P2, P4, P6 and P8 and is arranged in checkerboard pattern.In addition to this, even number falls pad P2, P4, P6 and P8 and Figure 16 It is similar with 251 that pad 247 is fallen with even number depicted in Figure 18.In addition, even number, which falls pad P2, P4, P6 and P8, can use other materials Material replaces.

The odd number that Figure 21 is painted the integrated circuit in Figure 15 falls the structural perspective of pad, is used to alternate figures 17 and figure Odd number depicted in 19 falls pad.

Unlike depicted in Figure 16 and Figure 18, even number is fallen into pad P2, P4, P6 and P8 and is arranged in a straight line, depicted in Figure 20 Even number falls pad P1, P3, P5 and P7 and is arranged in checkerboard pattern.In addition to this, even number falls pad P1, P3, P5 and P7 and Figure 16 It is similar with 250 that pad 246 is fallen with odd number depicted in Figure 18.In addition, even number, which falls pad P1, P3, P5 and P7, can use other materials Material replaces.

The wiring box that Figure 22 is painted on the wiring layer in the integrated circuit that Fig. 8 is accessed with whole bit lines shows It is intended to.

Figure 22 is painted a plurality of parallel digit lines BL1-BL8120 on metal layer ML2, is coupled to global bit line 232.

Figure 23 is painted the wiring box on another wiring layer in the integrated circuit that Fig. 8 is accessed with whole bit lines Schematic diagram.

Figure 23 is painted a plurality of parallel write-in on metal layer ML1 and reading pressure-wire BLi1-BLi8242 is coupled to and writes Enter and read pressure-wire and falls pad 236.Although being located on different metal layer, walking for pressure-wire BLi1-BLi8242 is written and read Line direction is identical as bit line BL1-BL8120.BL_BIAS line 265 is coupled to erasing/precharge/masking pressure-wire and falls pad 240 erasing/precharge/masking pressure-wire.The carrying of BIAS_SEL 262 is used to control whether second group of vertical gate voltage The grid voltage that switching transistor 238 opens or closes.The carrying of BIAS_SEL line 264 is used to control whether first group of vertical gate The grid voltage that pole tension switching transistor 234 opens or closes.Wherein BL_BIAS line 265, BIAS_SEL line 262 and BIAS_ SEL line 264 is all arranged in parallel on metal layer ML1.BL_BIAS line 265, BIAS_SEL line 262 and BIAS_SEL line 264 Direction of routing is directly handed over bit line BL1-BL8120 and write-in and reading pressure-wire BLi1-BLi8242.

In another embodiment, the position of metal layer ML1 and ML2 can change.Such as one or both of can be with It is placed on metal layer ML3 or higher position.In another embodiment, the direction of above-mentioned metal wire can be rotated one Angle.

Figure 24 is painted the wiring on a wiring layer of Figure 15 integrated circuit accessed with even number and odd bit lines Block diagram.

Figure 24 is painted a plurality of parallel digit lines BL1-BL8120 on metal layer ML2, is coupled to global bit line 232.

Figure 25 is painted the cloth on another wiring layer of Figure 15 integrated circuit accessed with even number and odd bit lines Line block diagram.

Figure 25 be painted a plurality of parallel odd number write-in on metal layer ML1 and read pressure-wire BLi1, BLi3, BLi5 and BLi7252, is coupled to odd number write-in and reading pressure-wire falls pad 246, and a plurality of on metal layer ML1 Parallel even number write-in and reading pressure-wire BLi2, BLi4, BLi6 and BLi8252, is coupled to write-in and reads pressure-wire coupling number Fall pad 247.Unlike as depicted in Figure 23, write-in and reading pressure-wire herein is all distinguished into odd and even number group. Although being located on different metal layer, there are also even number write-ins by odd number write-in and reading pressure-wire BLi1, BLi3, BLi5 and BLi7252 And the direction of routing of reading pressure-wire BLi2, BLi4, BLi6 and BLi8252 are identical as bit line BL1-BL8120.

BL_BIAS line 254 be coupled to odd number fall erasing/precharge/masking pressure-wire the odd number erasing of pad 250/pre- Charging/masking pressure-wire.BIAS_SEL line 255 be coupled to even number fall erasing/precharge/masking pressure-wire the idol of pad 251 Number erasing/precharge/masking pressure-wire.Unlike as depicted in Figure 23, these erasing/precharge/masking pressure-wires all by It is distinguished into odd and even number group.

The carrying of BIAS_SEL line 262 is used to control whether to open the second odd number group vertical gate voltage switching transistor 248 The grid voltage for opening or closing.The carrying of BIAS_SEL line 273 is used to control whether the second even number set vertical gate voltage switch The grid voltage that transistor 249 opens or closes.The BIAS_SEL line 262 unlike depicted in Figure 23, these BIAS_SEL lines are all It is distinguished into odd and even number group.

The carrying of BIAS_SEL line 274 is used to control whether to open the first odd number group vertical gate voltage switching transistor 244 The grid voltage for opening or closing.The carrying of BIAS_SEL line 275 is used to control whether the first even number set vertical gate voltage switch The grid voltage that transistor 245 opens or closes.The BIAS_SEL line 264 unlike depicted in Figure 23, these BIAS_SEL lines are all It is distinguished into odd and even number group.

BL_BIAS line 254, BIAS_SEL line 255, BIAS_SEL line 272, BIAS_SEL line 273, BIAS_SEL line 274 It is all arranged in parallel on metal layer ML1 with BIAS_SEL line 275.BL_BIAS line 254, BIAS_SEL line 255, BIAS_SEL Line 272, BIAS_SEL line 273, BIAS_SEL line 274 and BIAS_SEL line 275 direction of routing and bit line BL1-BL8120 and Odd number write-in and the write-in of reading pressure-wire BLi1, BLi3, BLi5 and BLi7252 even number and reading pressure-wire BLi2, BLi4, BLi6 It is directly handed over BLi8.

Figure 26 is painted the simplified electrical circuit diagram that can be utilized for a pair of of vertical gate switching transistor of write-in or read operation.

The first transistor 312 is opened by gate voltage BL_SEL 310, makes sequentially to be electrically coupled to sensing amplifier 350 The electric property coupling each other of bit line 300 and 330.Second transistor 322 is opened by gate voltage BL_SEL 320, thus from BL_ BIAS 340 is electrically coupled to bit line 300.When for carrying out write operation, the write-in voltage that numerical value is 0V or Vdd passes through first Transistor 312 reaches bit line 300.When for being read, numerical value is about~and the reading voltage of 1V passes through the first transistor 312 reach sensing amplifier 350.

Figure 27 is painted in the integrated circuit that Fig. 8 is accessed with whole bit lines, can be utilized for being written or reading behaviour The simplified electrical circuit diagram for the multipair vertical gate switching transistor made.

Circuit depicted in Figure 27 is substantially similar with Figure 26, the difference is that switching transistor and the quantity of induction amplifier with The increase of bit line quantity and increase.For control bit line 301, the first transistor 314, second transistor 324, bit line are increased 331 and sensing amplifier 351.Bit line 301, the first transistor 314, second transistor 324, bit line 331 and sensing amplifier 351 Effect it is similar with bit line 300, the first transistor 312, second transistor 322, bit line 330 and sensing amplifier 350 respectively.

Figure 28 is painted in the integrated circuit that Figure 15 is accessed with even number and odd bit lines, can be utilized for write-in or The simplified electrical circuit diagram of the multipair vertical gate switching transistor of read operation.

Circuit depicted in Figure 28 is substantially similar with Figure 27, is accessed the difference is that a bit line need to be spaced, therefore only There are even bitlines or odd bit lines that can be accessed.When in the present embodiment, for carrying out write operation, numerical value is 0V or Vdd Write-in voltage reach bit line BL 300 by the first transistor 312；Or when for being read, numerical value is about~1V Reading voltage reach sensing amplifier 350 by the first transistor 312.In the same time, when write operation or behaviour is read When just being executed by bit line 300, do not executed by any operation by bit line 301.The first transistor 312 is opened, and second transistor 324 closes It closes, bit line 301 is coupled to 0V to be covered, or be pre-charged to it, thus by bit line 301 and just in adjacent bit lines The write-in carried out in 300 or read operation isolation.

Figure 29 is painted the simplified electrical circuit diagram of a pair of vertical gate switching transistor that can be utilized for erasing operation.

The first transistor 312 is opened by gate voltage BL_SEL 310, makes sequentially to be electrically coupled to sensing amplifier 350 Bit line 300 and 330 it is electrically isolated from each other.Second transistor 322 is opened by gate voltage BL_SEL line 320, thus by position Line 300 is electrically coupled to BL_BIAS line 340.When being used to carry out erasing operation, high-intensitive erasing voltage passes through the second crystal Pipe 322 reaches bit line BL 300.

Figure 30 is painted in the integrated circuit that Fig. 8 is accessed with whole bit lines, can be utilized for the more of erasing operation To the simplified electrical circuit diagram of vertical gate switching transistor.

Circuit depicted in Figure 30 is substantially similar with Figure 29, the difference is that switching transistor and the quantity of induction amplifier with The increase of bit line quantity and increase.For control bit line 301, the first transistor 314, second transistor 324, bit line are increased 331 and sensing amplifier 351.Bit line 301, the first transistor 314, second transistor 324, bit line 331 and sensing amplifier 351 Effect respectively with bit line 300, the first transistor 312,350 phase of second transistor 322, bit line BLi 330 and sensing amplifier Seemingly.

Figure 31 is painted in the integrated circuit that Figure 15 is accessed with even number and odd bit lines, can be utilized for erasing behaviour The simplified electrical circuit diagram for the multipair vertical gate switching transistor made.

Circuit depicted in Figure 31 is substantially similar with Figure 28, the difference is that only erasing operation, and write-not or read operation, It must be carried out in the integrated circuit with even number or singular bit line.Unlike depicted in Figure 28, erasing operation depicted in Figure 31, Even number and singular bit line apply similar bias.Therefore bit line BL 300 and BLi 330 has been applied high-intensitive erasing bias.

Figure 32 is painted the simplified electrical circuit diagram of the integrated circuit with vertical gate switching transistor.

This integrated circuit 475 includes three-dimensional NAND Flash memory array 460 described in above-described embodiment, and being located at has On the semiconductor substrate of conductor laminated construction, and there is capacitor made of conductor laminated construction.Line decoder 461 is coupled to more The wordline 462 that item is arranged along the row of memory array 460.Column decoder in box 466 is coupled to a plurality of tandem selection line 464, it is arranged along the column of the laminated construction in corresponding memory array 460, for from the storage unit of memory array 460 Read or be written data.Plane decoder 458 is coupled to multiple plane layers of memory array 460 via multiple bit lines 459.Position Location is then provided to line decoder 461, column decoder and plane decoder 458 by bus 465.463 side of being coupled to of page buffer Column decoder and memory array 460 in frame 466.Page buffer 463 includes that three-dimensional height described in above-described embodiment presses off Close transistor.463 pairs of page buffer are directed toward the bit line of memory array 460 and are directed toward the bit line of sensing amplifier or are used to The pressure-wire of carrying erasing bias is multiplexed (multiplexes).This multiplexing can be distinguished into odd and even number Route.Page buffer 463 may include for being read out the sensing amplifier with verification operation.Page buffer 463 can To include other circuits, such as fault detection circuit (fail detection circuitry), for detect verification operation it (pass/retry/fail) whether pass through/is retried/failed afterwards, senses the data quick note of the reading/writing data of write operation Recall (data cache) and caching data decoding (cache decoding)/output buffering (output buffer).Data warp By Data In-Line 471 from the input/output connecting pin on integrated circuit 475, or from its inside or outside integrated circuit 475 His data source is provided to the data input structure in box 466.In the present embodiment, other circuits 474, such as general procedure Device (general purpose processor) or special-purpose applications circuit (special purpose application Circuitry it is supported) or by NAND Flash memory array and the mould group group of system on chip (system-on-a-chip) is provided Conjunction is also incorporated herein on integrated circuit.Data are defeated from the data in 475 upper box 466 of integrated circuit via DOL Data Output Line 472 Structure is provided to the input/output connecting interface on integrated circuit 475 out, or from other inside or outside integrated circuit 475 Data endpoint.

In the present embodiment, the controller that state machine 469 is arranged using bias, is controlled by 468 institute of voltage source or power supply The bias for generating or providing arranges the application of voltage, such as reading, write-in, erasing, erasing verifying and write verification；And it controls System is used to control the grid voltage of first group and second group vertical gate voltage switching transistor.This controller can be using known Special purpose logic circuitry realized.In another embodiment, controller includes being implemented in identical integrated circuit, is used To execute the general processor that operation program is operated with control element.In another embodiment, specific use logic can be used This controller is realized in the combination of circuit and general processor.

In some embodiments, can by wiring and it is decoded change come change respectively plane decoder, column decoder and The position of line decoder.

Adjective used in aforementioned, such as top (above), lower section (below), top (top), bottom (bottom), above (over) or following (under) etc. are only for description explanation to help to understand, not to limit this The range of invention.

Figure 33 is painted the cross-sectional view of the structure that can produce the different mask combinations in the area Luo Zhe of different depth.In order to be formed herein Described falls plot structure, and dielectric layer 22 and the staggered laminated construction 20 of conductive layer 24 are formed on dielectric substrate 26.In this reality It applies in example, includes 8 groups of dielectric layers 22 and conductive layer 24, indicated respectively with 22.0 to 22.7 and 24.0 to 24.7. Hard exposure mask 30, etch stop layer 28 and the first dielectric layer 22 are covered on laminated construction 20.According to using the first photoresist exposure mask 52, the closing mask regions 40 for the multiple etching step that the second photoresist exposure mask 54 and the second photoresist exposure mask 56 are carried out and opening The combination of etching region 38 etches the contact openings 32.0 to 32.7 of different depth.

First photoresist exposure mask 52 have opening etching area 38 cover half contact openings 32 (such as 4, herein In embodiment) and hard exposure mask 30 between opening etching area 38 and contact openings 32.First photoresist exposure mask 52 has simultaneously There are a closing mask regions 40 to cover other contact openings 32 and covering between closing mask regions 40 and contact openings 32 firmly Film 30.There are second photoresist exposure mask 54 2 opening etching areas 38 and 2 interlaced with each other to close mask regions 40, cover four points One of contact openings 32 (such as 2, in this embodiment) and be located at these opening etching areas 38 and closing mask regions 40 and Hard exposure mask 30 between contact openings 32.There are third photoresist exposure mask 56 4 opening etching areas 38 and 4 interlaced with each other to seal Mask regions 40 are closed, eighth contact openings 32 (such as 1, in this embodiment) are covered and are located at these opening etching areas Hard exposure mask 30 between 38 and closing mask regions 40 and contact openings 32.

Reactive ion etching can be used, such as include tetrafluoromethane/nitrogen/difluoromethane/hydrogen bromide/helium-oxygen/helium Gas (CF₄/N₂/CH₂F₂/HBr/He-O₂/ He) chemical etchant, stop at the top of suitable conductive layer 24.0 to 24.7.

In the present embodiment, it falls pad to be arranged in a straight line, corresponds to the closing mask regions being arranged in a straight line in exposure mask 40 and opening etching area 38.In other embodiments of the invention, closes mask regions 40 and opening etching area 38 is arranged in that The checkerboard pattern of this adjoining, thus generating, there is the odd number of checkerboard pattern adjacent to each other or even number to fall pad.

More information that the method and technology that fall pad are connected in relation to forming connection conductor have been disclosed in number US 13/ 049,303 U.S. patent application case, the applying date are on March 16th, 2011, entitled " REDUCED NUMBER OF MASK The U.S. Patent application of FOR IC DEVICE WITH STACKED CONTACT LEVELS " and number US 13/114,931 Case, the applying date are on May 24th, 2011, entitled " MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD ", wherein the content of these application cases will be incorporated by reference into the mode of (incorporated by reference), This full patent texts is recorded among present disclosure.These application cases and this case have co-inventor.

Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention.Work described herein Skill step and structure are not covered by the complete manufacturing process of production over all Integration circuit.The present invention can be currently known with many or The different production of integrated circuits technologies that future is developed, which merge, to be implemented.There is usual knowledge in the technical field of the invention Person, without departing from the spirit and scope of the present invention, when various change and modification can be made.Therefore, protection scope of the present invention Subject to the protection scope defined depending on appended claims.

Claims

1. a kind of integrated circuit, comprising:

One three-dimensional NAND memory array, including multiple memory transistors；

Multiple bit lines are electrically coupled to the solid NAND memory array；And

Multiple transistors pair, have one it is semiconductor laminated, multiple and different layers during this is semiconductor laminated include these multiple crystalline substances Multiple source/drain endpoints of the multiple and different transistor pair of body pipe centering；Each of these multiple pair of transistors includes One the first transistor and a second transistor, and the first transistor and the second transistor have one first source/drain terminal Point, one second source/drain endpoint and a third source/drain endpoint；Wherein:

The first transistor has the first source/drain endpoint and the third source/drain endpoint；And the second transistor has There are the second source/drain endpoint and the third source/drain endpoint；And first source/drain terminal is electrically coupled to one Erasing voltage line；Second source/drain terminal is electrically coupled in a plurality of write-in/reading pressure-wire corresponding one；It should Third source/drain terminal is electrically coupled in these multiple bit lines corresponding one；

One first grid, for controlling all these the first transistors of these multiple pair of transistors；And

One second grid, for controlling all these second transistors of these multiple pair of transistors.

2. integrated circuit as described in claim 1, wherein the first grid controls whether these multiple bit lines are coupled to these These the first source/drain endpoints of multiple pair of transistors；And the second grid controls whether these multiple bit lines are coupled to These two source/drains endpoints of these multiple pair of transistors.

3. integrated circuit as described in claim 1, wherein the solid NAND memory array includes that multiple semiconducting tapes are folded Layer structure, setting carry out a plurality of transistor channels as the different memory transistors of these in the solid NAND memory array；

And this semiconductor laminated includes:

One first semiconducting tape laminated construction, configuration to be different from these the first transistors as these multiple pair of transistors Transistor channels；And

One second semiconducting tape laminated construction, configuration to be different from these second transistors as these multiple pair of transistors Transistor channels.

4. integrated circuit as claimed in claim 3, wherein be located in the first semiconducting tape laminated construction a plurality of partly leads Body band, a plurality of semiconducting tape in the second semiconducting tape laminated construction and be located at these multiple conductive straps A plurality of semiconducting tape in laminated construction, shares multiple plan-positions.

5. integrated circuit as described in claim 1 further includes a circuit, it is used to generate the erasing voltage line one first group of electricity Pressure, and be written/read pressure-wire to these and generate one second group of voltage.

6. integrated circuit as claimed in claim 3, wherein these being located in the first semiconducting tape laminated construction are partly led Body band is electrically coupled to these bit lines adjacent with these semiconducting tapes in these multiple bit lines.

7. integrated circuit as claimed in claim 3, wherein these being located in the first semiconducting tape laminated construction are partly led Body band is electrically coupled in these multiple bit lines not these bit lines adjacent with these semiconducting tapes.

8. integrated circuit as described in claim 1 further includes a circuit, for executing following actions:

Open multiple the first transistors；And close multiple second transistors；And

Open multiple second transistors；And close multiple the first transistors.

9. a kind of method for operating multiple bit lines, these bit lines are electrically coupled to the solid NAND with multiple memory transistors Memory array, the method include:

Switchably these bit lines are electrically coupled to one of following:

(i) one first group of voltage passes through of an at least first memory operational configurations in the solid NAND memory array One group of multiple transistor is coupled, and wherein first group of multiple transistor have one first semiconducting tape laminated construction； And

(ii) one second group of voltage passes through of an at least second memory operational configurations in the solid NAND memory array Two groups of multiple transistors are coupled, and wherein second group of multiple transistor have one second semiconducting tape laminated construction； And the second memory operational configurations are different with the first memory operational configurations；

Wherein, a plurality of semiconducting tape in the first semiconducting tape laminated construction, is provided to as this first group Multiple transistor channels of these different transistors in multiple transistors；In the second semiconducting tape laminated construction A plurality of semiconducting tape is provided to lead to as multiple transistors of these transistors different in second group of multiple transistor Road；And the solid NAND memory array includes multiple semiconducting tape laminated construction, setting to store as solid NAND Multiple transistor channels of these different memory transistors in device array；And

Wherein, a plurality of semiconducting tape in the first semiconducting tape lamination, be located at the second semiconducting tape lamination A plurality of semiconducting tape in structure and a plurality of semiconducting tape in these multiple semiconducting tape laminated construction, altogether With multiple plan-positions；Wherein, the multiple plan-positions of these different correspond to different transistor channels to be arranged.

10. method as claimed in claim 9, wherein the first memory operational configurations include erasing；And the second memory Operational configurations include at least one of both write-in and reading.

11. method as claimed in claim 9, wherein the first memory operational configurations include erasing, precharge and masking；And The second memory operational configurations include write-in and read.

12. method as claimed in claim 9, wherein the not corresponding lines in these multiple bit lines is coupled to solid NAND storage These Different Plane positions in device array.

13. method as claimed in claim 9, further includes:

Generate first group of voltage for being suitable for the first memory operational configurations；And

Generate second group of voltage for being suitable for the second memory operational configurations.

14. method as claimed in claim 9, wherein being located at these semiconductor bars in the first semiconducting tape laminated construction Charging property is coupled to bit line adjacent with these semiconducting tapes in these multiple bit lines.

15. method as claimed in claim 9, wherein being located at these semiconductor bars in the first semiconducting tape laminated construction Charging property is coupled in these multiple bit lines the not bit line adjacent with these semiconducting tapes.

16. method as claimed in claim 9, further includes:

(i) first group of multiple transistor are opened；And second group of multiple transistor are closed, by by first group of voltage coupling These multiple bit lines are connected at least to carry out the first memory operational configurations；And

(ii) second group of multiple transistor are opened；And first group of multiple transistor are closed, by by second group of voltage These multiple bit lines are coupled at least to carry out the second memory operational configurations.

17. a kind of production method of integrated circuit, comprising:

A three-dimensional NAND memory array is provided, making it includes multiple memory transistors；

Multiple bit lines are provided and are electrically coupled to the solid NAND memory array；And

Multiple transistors pair are provided, make it have one it is semiconductor laminated, include in multiple and different layers during this is semiconductor laminated Multiple source/drain endpoints of these multiple and different transistors pair of these multiple pair of transistors；These multiple transistors pair Each of include a first transistor and a second transistor, and the first transistor and the second transistor have one the Source/drain electrode endpoint, one second source/drain endpoint and a third source/drain endpoint；Wherein:

The first transistor includes the first source/drain endpoint and the third source/drain endpoint；The second transistor includes The second source/drain endpoint and third source/drain endpoint；First source/drain terminal is electrically coupled to erasing electricity Crimping；Second source/drain terminal is electrically coupled in a plurality of write-in/reading pressure-wire corresponding one；And this Three source/drain terminals are electrically coupled in these multiple bit lines corresponding one；