CN106298786A - Integrated circuit and making thereof and operational approach - Google Patents

Abstract

A kind of integrated circuit includes the three-dimensional NAND memory array containing memory transistors, multiple bit lines, and different bit lines is coupled to the different parts of three-dimensional NAND memory array, and be positioned at semiconductor laminated in multiple transistors pair.Different layers in semiconductor laminated includes the different transistor pair of multiple pair of transistors.Each transistor is to comprising the first transistor and transistor seconds.Wherein, the first transistor includes first and the 3rd source/drain end points；Transistor seconds includes second and the 3rd source/drain end points.First source/drain terminal is electrically coupled to an erasing voltage line.Second source/drain terminal is electrically coupled to corresponding in a plurality of write/read voltage line one.3rd source/drain terminal is electrically coupled to corresponding in multiple bit lines one article.

Description

Integrated circuit and making thereof and operational approach

Technical field

The present invention relates to a kind of nonvolatile memory device (non-volatile memory devices), Particularly relate to a kind of system vertical gate memory array (3D vertical gate memory array).

Background technology

NAND memory array employing high voltage switching transistor is isolated and is come from array and come from The erasing voltage of sensing amplifier.Although reading and write use relatively low voltage, but erasing being grasped But the voltage of a high intensity has been coupled to array.Therefore use high voltage switching transistor by array with Sensing amplifier electrically isolated (electrically decouple), to prevent PN junction from collapsing (junction breakdown)。

It is said that in general, at plane NAND memory array (2D NAND memory array) Among erasing operation, the PWI region that in triple wells (triple-well), p-type doping content is the highest Current potential can raise.The arrangement mode of Typical Planar nand memory element is to use 4 one group High-tension switch field-effect transistor (MOSFETs) is placed in outside PWI region, thus by array and wiping Except voltage is electrically isolated.

In the arrangement of another kind of plane NAND memory array, memory array and 4 switches PWI region shared by field-effect transistor, to prevent bigger pressure reduction, and allows low-pressure designs rule to be suitable for In these 4 switch yard effect transistors.Up-to-date arrangement, is additionally to increase outside PWI region One high-voltage switch gear field-effect transistor, and by the number of high-voltage switch gear field-effect transistor by 4 minimizings It it is 1.Thus while additionally increase a transistor, but entire area is made to diminish.

Three-dimensional nand memory structure equally benefits from the configuration of high voltage switching transistor, in order to Protection sensing circuit avoids the injury of high intensity erasing voltage.But, three-dimensional nand memory can Can lack in plane nand memory structure, be used for providing high voltage switch circuit to reduce area The PWI region consumed.

Therefore, in three-dimensional nand memory structure, high voltage switching transistor circuit consumes greatly The area of amount.In a memory array embodiment with 8 bit lines, every bit lines configuration two Individual XY switch transistor, needs 16 XY switch transistors to be electrically coupled to by these bit lines Erasing voltage line or write read voltage line.

Therefore, there is a need to reduce the face consumed in switching transistor of three-dimensional NAND memory array Long-pending.

Summary of the invention

The switch that different embodiment disclosed in this invention reduces three-dimensional NAND memory array is brilliant Area consumed in body pipe.This three-dimensional NAND memory array has three-dimensional voltage switching transistor, This three-dimensional voltage switching transistor and plane voltage switching transistor (are such as formed at the crystalline substance among base material Body pipe) compare, there is relatively low stacking area (aggregate area).In certain embodiments, vertical Body NAND memory array and three-dimensional voltage switching transistor all use vertical gate memory construction.

In one aspect of the invention, this integrated circuit includes the solid with multiple memory transistor NAND memory array, multiple bit lines, the most different bit lines is coupled to three-dimensional NAND storage The different parts of device array, and it is positioned at a semiconductor laminated (stack of semiconductor Layers) the multiple transistors pair in.Different layers in semiconductor laminated includes multiple pair of transistors Different transistors pair.Each of multiple pair of transistors comprises the first transistor and the second crystal Pipe, and there is both this first, second, and third source/drain end points.Wherein, the first transistor bag Include first and the 3rd source/drain end points；Transistor seconds includes second and the 3rd source/drain end points. First source/drain terminal is electrically coupled to an erasing voltage line.The second electrical coupling of source/drain end points It is connected to corresponding in a plurality of write/read voltage line one.3rd source/drain end points electric property coupling Corresponding to multiple bit lines one.

Among some embodiments of the present invention, first grid controls all the of multiple pair of transistors One transistor；And second grid controls all transistor secondses of multiple pair of transistors.

Among some embodiments of the present invention, first grid controls whether multiple bit lines is coupled to multiple First source/drain end points of pair of transistors；And second grid controls whether multiple bit lines is coupled to many Second source/drain end points of individual pair of transistors.

Among some embodiments of the present invention, three-dimensional NAND memory array includes multiple partly leading Body band laminated construction (stacks of semiconductor strips), is arranged as three-dimensional NAND The transistor channels of different memory transistors in memory array.This is semiconductor laminated includes: the first half Conductive strap laminated construction, configuration carrys out the transistor as multiple pair of transistors difference the first transistors Passage；And the second semiconducting tape laminated construction, configuration comes as multiple pair of transistors differences the The transistor channels of two-transistor.

Among some embodiments of the present invention, be positioned in the first semiconducting tape laminated construction is a plurality of Semiconducting tape, a plurality of semiconducting tape being positioned in the second semiconducting tape laminated construction and be positioned at A plurality of semiconducting tape in multiple conductive strap laminated construction, shares multiple plan-position (plane positions)。

Among some embodiments of the present invention, the not corresponding lines in multiple bit lines is electrically coupled to solid The Different Plane position of NAND memory array.

Some embodiments of the present invention also include, are used for erasing voltage line is produced first group of voltage, with And write/read voltage line is produced the circuit of second group of voltage.

Among some embodiments of the present invention, be positioned in the first semiconducting tape laminated construction is a plurality of Semiconducting tape is electrically coupled to the bit line being adjacent in multiple bit lines.

Among some embodiments of the present invention, be positioned in the first semiconducting tape laminated construction is a plurality of Semiconducting tape is electrically coupled on the bit line that is not adjacent in multiple bit lines.

Some embodiments of the present invention also include the circuit for performing following actions:

I () opens multiple the first transistor；And close multiple transistor seconds；And

(ii) multiple transistor seconds is opened；And close multiple the first transistor.

Another aspect of the present invention is the method for operation multiple bit lines.These bit lines are electrically coupled to comprise The three-dimensional NAND memory array of multiple memory transistors, the most different bit lines is electrically coupled to The different parts of three-dimensional NAND memory array, the method includes

Switchably (switchably) bit line is electrically coupled to following one of them:

I () first group of voltage, it is by least one first storage in three-dimensional NAND memory array First group of multiple transistor of device operational configurations couple, and wherein first group of multiple transistor has One the first semiconducting tape laminated construction；And

(ii) second group of voltage, it is by least one second storage in three-dimensional NAND memory array Second group of multiple transistor of device operational configurations couple, and wherein second group of multiple transistor has One the second semiconducting tape laminated construction；And second memory operational configurations and first memory operate Kenel is different.

Among some embodiments of the present invention, it is positioned at partly leading in the first semiconducting tape laminated construction Body band, is provided to as the transistor channels of different crystal pipe in first group of multiple transistor；Position Bar semiconducting tape in the second semiconducting tape laminated construction, is provided to as second group multiple The transistor channels of different crystal pipe in transistor；And solid NAND memory array includes multiple Semiconducting tape laminated construction, is arranged as storage crystalline substances different in three-dimensional NAND memory array The transistor channels of body pipe.Among some embodiments of the present invention, it is positioned at the first semiconducting tape and folds A plurality of semiconducting tape in Ceng, a plurality of semiconductor bar being positioned in the second semiconducting tape laminated construction Carry and be positioned at a plurality of semiconducting tape in multiple conductive strap laminated construction, sharing multiple plane positions Put.Wherein, different plan-position correspondence different crystal tube passages is arranged.

Among some embodiments of the present invention, first memory operational configurations includes erasing；And second Storage operation kenel includes write and reads at least one of the two.In some embodiments of the present invention Among, first memory operational configurations includes erasing；And second memory operational configurations include write and Read.

Among some embodiments of the present invention, the not corresponding lines in multiple bit lines is coupled to solid Different Plane position in NAND memory array.

Some embodiments of the present invention, also include producing and are applicable to the first of first memory operational configurations Group voltage and be applicable to the circuit of second group of voltage of second memory operational configurations.

Among some embodiments of the present invention, be positioned in the first semiconducting tape laminated construction is a plurality of Semiconducting tape is electrically coupled in multiple bit lines be adjacent the bit line connect.

Among some embodiments of the present invention, be positioned in the first semiconducting tape laminated construction is a plurality of Semiconducting tape is electrically coupled in multiple bit lines not be adjacent the bit line connect.Such as, write and / or read storage operation, can be performed by odd number or even bitlines/whole bit lines.

Some embodiments of the present invention also include with circuit to perform following actions:

I () opens first group of multiple transistor, and close second group of multiple transistor, thus by the One group of voltage is coupled to multiple bit lines at least to carry out first memory operational configurations；And

(ii) open multiple transistor seconds, and close multiple the first transistor, thus by second Group voltage is coupled to multiple bit lines at least to carry out second memory operational configurations.

An additional aspect of the present invention is a kind of integrated circuit, including:

One three-dimensional NAND memory array, has multiple memory transistor, multiple bit lines, wherein Not corresponding lines in multiple bit lines be electrically coupled to three-dimensional NAND memory array different parts, It is positioned at the multiple the first transistors in the first semiconducting tape laminated construction, and is positioned at the second quasiconductor Multiple transistor secondses in band laminated construction.Multiple bit lines is switchably coupled to organize in voltage more Only one.These many group voltages at least include:

(i) first group of voltage, its be by three-dimensional NAND memory array at least one first First group of multiple transistor of storage operation kenel couple；And

(ii) second group of voltage, it is by three-dimensional NAND memory array, at least one second is deposited Second group of multiple transistor of reservoir operational configurations couple, and second memory operational configurations and First memory operational configurations is different.

Another aspect of the invention is the method making this integrated circuit.

For making the above embodiment of the present invention and other objects, features and advantages to become apparent, special Lift several preferred embodiment, and coordinate appended accompanying drawing, be described in detail below:

Accompanying drawing explanation

Fig. 1 illustrates the voltage switch crystalline substance having three-dimensional NAND memory array and being positioned in base material The block diagram of the integrated circuit of body pipe；

Fig. 2 illustrates another block diagram of the integrated circuit of Fig. 1, and it will be located in the electricity in base material The transistor that compresses switch is depicted as having relatively large size；

Fig. 3 illustrates the knot of a kind of system vertical gate NAND flash memory cubic memory array Structure perspective view, can be used to the embodiment of the cubic memory array as Fig. 1；

Fig. 4 illustrates one, and to be pointed in base material can be applicable to the structure of the voltage switching transistor in Fig. 1 saturating View；

The knot of voltage switching transistor that Fig. 5 illustrates in the multipair Fig. 1 of can be applicable to and is positioned in base material Structure perspective view；

Fig. 6 illustrates has three-dimensional NAND memory array and vertical gate voltage switching transistor The block diagram of integrated circuit；

Fig. 7 illustrates another block diagram of the integrated circuit of Fig. 6, and vertical gate voltage is opened by it Close transistor and be depicted as that there is relatively small size；

Fig. 8 illustrates the more detailed block diagram of the integrated circuit of Fig. 6, also demonstrates and organizes vertical gate more Pole tension switching transistor and the many groups of pads that fall (landing pads)；

Fig. 9 illustrates the structural perspective of an embodiment of the integrated circuit of Fig. 8；

The structural perspective of Figure 10 illustrates the bit line in the integrated circuit being positioned at Fig. 9 and bit line falls pad；

Figure 11 illustrates the first vertical gate voltage switching transistor in the integrated circuit being positioned at Fig. 9 Structural perspective；

Figure 12 illustrates the write of the integrated circuit being positioned in Fig. 9 and read voltage line and write and reading Power taking line ball fall pad structural perspective；

Figure 13 illustrates second group of vertical gate voltage switching transistor of the integrated circuit being positioned in Fig. 9 Structural perspective；

Figure 14 illustrates the erasing voltage line of the integrated circuit being positioned in Fig. 9 and erasing voltage line falls The structural perspective of pad；

Figure 15 illustrates another detailed block diagram of the integrated circuit of Fig. 6, demonstrates that it passes through very Number or even bitlines access, rather than are accessed by whole bit lines as shown in Figure 8；

Figure 16 illustrates the write of the integrated circuit being positioned in Figure 15 and read voltage line and write and reading Power taking line ball falls the structural perspective of pad, and it is accessed by even bitlines, rather than such as Figure 12 Shown in accessed by whole bit lines；

Figure 17 illustrates the write of the integrated circuit being positioned in Figure 15 and read voltage line and write and reading Power taking line ball falls the structural perspective of pad, and it is accessed by odd bit lines, rather than such as Figure 12 Shown in accessed by whole bit lines；

Figure 18 illustrates the erasing voltage line of the integrated circuit being positioned in Figure 15 and erasing voltage line falls The structural perspective of pad, it is accessed by even bitlines, rather than passes through complete as shown in figure 14 Bit line accesses；

Figure 19 illustrates the erasing voltage line of the integrated circuit being positioned in Figure 15 and erasing voltage line falls The structural perspective of pad, it is accessed by odd bit lines, rather than passes through complete as shown in figure 14 Bit line accesses；

Figure 20 illustrates the even number of the integrated circuit being positioned in Figure 15 and falls the structural perspective of pad, is used for Substitute the even number depicted in Figure 16 and Figure 18 to fall to padding；

Figure 21 illustrates the odd number of the integrated circuit being positioned in Figure 15 and falls the structural perspective of pad, is used for Substitute the odd number depicted in Figure 17 and Figure 19 to fall to padding；

Figure 22 illustrates and is positioned at the wiring layer that Fig. 8 carries out in the integrated circuit accessed with whole bit lines Wiring (the routing conductive lines) block diagram of (routing layer).

Figure 23 illustrates and is positioned at another wiring layer that Fig. 8 carries out in the integrated circuit accessed with whole bit lines Wiring block diagram；

Figure 24 illustrates and is positioned at Figure 15 and carries out the wiring layer of the integrated circuit accessed with even number and odd bit lines Wiring block diagram；

Figure 25 illustrates and is positioned at Figure 15 and carries out another cloth of the integrated circuit accessed with even number and odd bit lines The wiring block diagram of line layer；

Figure 26 illustrates a pair vertical gate switching transistor that can be utilized for write or read operation Simplified electrical circuit diagram；

Figure 27 illustrates and is positioned at Fig. 8 and carries out, in the integrated circuit accessed, can be utilized for whole bit lines The simplified electrical circuit diagram of the multipair vertical gate switching transistor of write or read operation；

Figure 28 illustrates and is positioned at Figure 15 and carries out in the integrated circuit accessed with even number and odd bit lines, available Carry out writing or the simplified electrical circuit diagram of multipair vertical gate switching transistor of read operation；

Figure 29 illustrates the simplification electricity of a pair vertical gate switching transistor that can be utilized for erasing operation Lu Tu；

Figure 30 illustrates and is positioned at Fig. 8 and carries out, in the integrated circuit accessed, can be utilized for whole bit lines The simplified electrical circuit diagram of the multipair vertical gate switching transistor of erasing operation；

Figure 31 illustrates and is positioned at Figure 15 and carries out in the integrated circuit accessed with even number and odd bit lines, available Carry out the simplified electrical circuit diagram of the multipair vertical gate switching transistor of erasing operation；

Figure 32 illustrates the simplified electrical circuit diagram of the integrated circuit with vertical gate switching transistor；

Figure 33 illustrates the section of structure of the different mask combinations in the Luo Zhe district that can produce different depth.

[symbol description]

20: laminated construction 22,22.0-22.7: dielectric layer

24,24.0-24.7: conductive layer 26: dielectric substrate

28: etch stop layer 30: hard mask

32,32.0-32.7: contact openings 38: opening etching district

40: close mask 52: the first photoresist mask

54: the second photoresist mask 56: the second photoresist masks

100: three-dimensional NAND memory array

112,113,114,115: semiconductor circuits

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A: bit line contact Pad

109,119: tandem selection grid structure 120: global bit line

125-1 ... 125-N: wordline 126,127: ground connection selects line

130,160-167: voltage switching transistor 132: read voltage line

134: wipe/be pre-charged/cover pressure-wire

140,146,148: conductive plunger

142: first crystal tube grid 144: transistor seconds grid

150,152,154: source/drain

230: vertical gate voltage switching transistor

232: global bit line falls and pads

234: the first groups of vertical gate voltage switching transistor

236: write and read voltage line fall to padding

238: the second groups of vertical gate voltage switching transistor

240,265: wipe/be pre-charged/cover pressure-wire and fall to padding

244: the first odd number group vertical gate voltage switching transistor

245: the first even number set vertical gate voltage switching transistor

246: odd number write and read voltage line fall to padding

247: even number write and read voltage line even number fall to padding

248: the second odd number group vertical gate voltage switching transistor

249: the second even number set vertical gate voltage switches

250: odd number falls to wiping/be pre-charged/and cover pressure-wire and pad

251: even number wipes/is pre-charged/and cover pressure-wire and fall to padding

252: odd number write and read voltage line

253,255 even numbers wipe/be pre-charged/cover pressure-wire

254: odd number wipes/is pre-charged/cover the erasing of voltage/be pre-charged/cover pressure-wire

BIAS_SEL 262、BIAS_SEL 255、BIAS_SEL 272、BIAS_SEL 273、 BIAS_SEL 274, BIAS_SEL 275, BIAS_SEL 310, BIAS_SEL 320: pressure-wire

312,314,322,324: transistor 322: transistor seconds

350,351: sensing amplifier BL_BIAS 340: pressure-wire

300,301,330,459, BL1-BL8: bit line

458: plane decoder

460: three-dimensional NAND Flash memory array

461: line decoder 462: wordline

463: page buffer 464: tandem selects line

465: bus

466: column decoder data go out/input structure

468: bias arrangement voltage 469: state machine

471: Data In-Line 474: other circuit

472: DOL Data Output Line 475: integrated circuit

BLi1, BLi3, BLi5, BLi7: read voltage line

P1-P8: semiconducting tape ML1, ML2, ML3: metal level

Detailed description of the invention

The following description content will be with reference to specific constructive embodiment and method.But must be noted that Content disclosed below, and be not used to limit the invention to specific constructive embodiment and method, The present invention still can use other features, element, method and embodiment to implement.The public affairs of preferred embodiment Open merely to the technical characteristic of the present invention is clearly described, be not limited to the appended right of the present invention Claimed scope.Persond having ordinary knowledge in the technical field of the present invention, without departing from the present invention Spirit and scope in, when making various changes and modification.Among different embodiments, identical Element will be indicated with identical component symbol.

Fig. 1 illustrates the voltage switch crystalline substance having three-dimensional NAND memory array and being positioned in base material The block diagram of the integrated circuit of body pipe.

Three-dimensional NAND memory array 100 is coupled to be positioned in base material by global bit line 120 Voltage switching transistor 130.According to the switching mode of transistor 130, global bit line 120 is coupled Extremely it is used for carrying write and the write of read voltage and read voltage line 132, or is coupled to for carrying The erasing voltage line 134 of erasing voltage.

Fig. 2 illustrates another block diagram of the integrated circuit of Fig. 1, and it will be located in the electricity in base material The transistor that compresses switch is depicted as having relatively large size.

The voltage switching transistor 130 being positioned in base material is depicted as the size with an X-direction (X-dimension), corresponding with the size of the X-direction of three-dimensional NAND memory array 100. The voltage switching transistor 130 being positioned in base material is depicted as the Y with about 150 microns (μm) Axial add overall size (aggregate Y-dimension).

Fig. 3 illustrates the knot of a kind of system vertical gate NAND flash memory cubic memory array Structure perspective view, can be used to the embodiment of the cubic memory array as Fig. 1.

This element includes laminated construction (the stacks of active being positioned at active lines in the active layers of array Lines), and with insulated circuit (insulating lines) intermesh.By insulant in accompanying drawing Removed, thus exposed other structures.Such as will be located in the semiconductor circuits of same tier structure Insulated circuit between (semiconductor lines), and it is positioned at different semiconductor circuits laminated construction Between insulated circuit removed.

In the present embodiment, multiple tier array is formed on an insulating barrier, and includes a plurality of wordline 125-1 ..., 125-N, conformal with above-mentioned multiple laminated construction.Above-mentioned multiple laminated construction includes position A plurality of semiconductor circuits 112,113,114 and 115 on multiple plane layers (multiple planes). The semiconductor circuits being positioned on same level layer passes through bit line contact pad (such as bit line contact pad 102B) Mutually electric property coupling.

It is positioned at bit line contact pad 112A, 113A, 114A and 115A of accompanying drawing near-end by semiconductor line Road, such as semiconductor circuits 112,113,114 and 115, disconnect.As it can be seen, bit line contact Pad 112A, 113A, 114A and 115A are by inter-layer connectors (interlayer connectors) electricity Property be connected to the not corresponding lines in patterned metal layer above (such as ML3), and via high electricity The transistor that compresses switch is connected to decoding circuit to select the plane layer in array.These bit line contact pads 112A, 113A, 114A and 115A can be formed on stepped matrix structure.And in definition It is patterned while multiple laminated construction.

It is positioned at bit line contact pad 102B, 103B, 104B and 105B of accompanying drawing far-end by semiconductor line Road, such as semiconductor circuits 112,113,114 and 115, disconnect.As it can be seen, bit line contact Pad 102B, 103B, 104B and 105B are electrically connected to pattern above by inter-layer connectors Change the not corresponding lines in metal level (such as ML3), and be connected to solve via high-voltage switch transistor Code circuit is to select the plane layer in array.These bit line contacts pad 102B, 103B, 104B and 105B Can be formed on stepped matrix structure.And be patterned while defining multiple laminated construction.

In the present embodiment, each semiconductor circuits laminated construction is electrically coupled to bit line contact pad 112A, 113A, 114A and 115A or bit line contact pad 102B, 103B, 104B and 105B its One of, rather than two.Semiconductor circuits (bit line) laminated construction (stack of semiconductor Lines) there is bit line end-to-source electrode line end and source electrode line end-to-two kinds of contrary trends of bit line end wherein One of.Such as, semiconductor circuits laminated construction 112,113,114 and 115 have bit line end-to- The trend of source electrode line end；And semiconductor circuits laminated construction 102,103,104 and 105 has source electrode The trend of line end-extremely-bit line end.

Semiconductor circuits laminated construction 112,113,114 and 115 one end by bit line contact pad 112A, 113A, 114A and 115A disconnect, through tandem select grid structure 119, ground connection select line 126, Wordline (by 125-1 to 125-N), ground connection select line 127, and the other end is disconnected by source electrode line 128. Semiconductor circuits laminated construction 112,113,114 and 115 do not touch bit line contact pad 102B, 103B, 104B and 105B.

Semiconductor circuits laminated construction 102,103,104 and 105 one end by bit line contact pad 102B, 103B, 104B and 105B disconnect, through tandem select grid structure 109, ground connection select line 127, Wordline (by 125-1 to 125-N), ground connection select line 126, the other end by source electrode line (by accompanying drawing Other parts are covered) disconnect.Semiconductor circuits laminated construction 102,103,104 and 105 is not Touch bit line contact pad 112A, 113A, 114A and 115A.

One storage material layer is configured at semiconductor circuits 12-115 and 102-105 with wordline 125-1 extremely On the boundary zone of the surface crosswise point of both 125-N.Ground connection selects line 126 similar with wordline with 127, All conformal with these laminated construction.

One end of each semiconductor circuits laminated construction is disconnected by bit line contact pad, and the other end is by source electrode Line disconnects.Such as one end of semiconductor circuits laminated construction 112,113,114 and 115 is connect by bit line Touch pad 112A, 113A, 114A and 115A disconnect, and the other end is disconnected by source electrode line 128.

Bit line and tandem select line to be formed on metal level ML1, ML2 and ML3.Bit line is by height Compress switch transistor couples to the plane decoder (not illustrating) being positioned at circuit surrounding zone.Tandem selects Line is coupled to be positioned at the tandem of circuit surrounding zone and selects line decoder (not illustrating).

Ground connection selection line 126 and 127 can be in the same technique of definition wordline 125-1 to 125-N Step is patterned.Ground connection selects element to be formed at multiple laminated construction and ground connection selects line 126 He On the boundary zone of the surface crosswise point both 127.Tandem selects the grid structure 119 and 109 can be The same processing step of definition wordline 125-1 to 125-N is patterned.Tandem selects element shape Become on multiple laminated construction and the boundary of the surface crosswise point of tandem selection both grid structures 119 and 109 In the district of face.These elements are coupled to decoding circuit, thus select to be positioned at specific laminated construction in array In tandem.

Fig. 4 illustrates one, and to be pointed in base material can be applicable to the structure of the voltage switching transistor in Fig. 1 saturating View.

Conductive plunger 140 couples the voltage between universe wordline and source/drain 150.

First crystal tube grid 142 switchably electric property coupling source/drain 150 and source/drain 152. When first crystal tube grid 142 receives a cut-in voltage, the first transistor electric property coupling conductive plunger 140 to conductive plunger 146.When first crystal tube grid 142 receives a closedown voltage, first is brilliant Body pipe is by electrically isolated to conductive plunger 140 and conductive plunger 146.Conductive plunger 146 is electrically coupled to It is used for carrying write and the write of read voltage and read voltage line.

Transistor seconds grid 144 switchably electric property coupling source/drain 150 and source/drain 154. When transistor seconds grid 144 receives a cut-in voltage, transistor seconds electric property coupling conductive plunger 140 to conductive plunger 148.When transistor seconds grid 144 receives a closedown voltage, second is brilliant Body pipe is by electrically isolated to conductive plunger 140 and conductive plunger 148.Conductive plunger 148 is electrically coupled to It is used for carrying the erasing voltage line of erasing voltage.

The first crystal tube grid 142 of the voltage switching transistor being positioned in base material and transistor seconds grid Pole 144 is depicted as the Y direction size with about 1.6 microns.This Y direction size and grid The size of length is corresponding.Source/drain 150, source/drain 152 and source/drain 154 are painted It is shown as the Y direction size with about 2.1 microns.

The knot of voltage switching transistor that Fig. 5 illustrates in the multipair Fig. 1 of can be applicable to and is positioned in base material Structure perspective view.

Each voltage switching transistor 160-167 being pointed in base material can be painted formula in Fig. 4 The single embodiment to voltage switching transistor, be electrically coupled to an erasing voltage line, respective bit lines, Individual other write and read voltage line.The case of these multipair voltage switching transistor, highlights base material In voltage switching transistor account for the total amount of chip area.

Fig. 6 illustrates has three-dimensional NAND memory array and vertical gate voltage switching transistor The block diagram of integrated circuit.

Three-dimensional NAND memory array 100 is coupled to vertical gate voltage by global bit line 120 Switching transistor 230.According to the switching mode of transistor 230, it is coupled to global bit line 120 use Carry write and the write of read voltage and read voltage line 132, or be coupled to for carry erasing/ It is pre-charged/covers the erasing of (erase/pre-charge/shielding) voltage/be pre-charged/cover pressure-wire 134.Wherein, be pre-charged and cover voltage be also applied for write and/or read mode.

In some other embodiments, be used for carrying wipe/be pre-charged/cover the erasing/precharge of voltage/ Cover pressure-wire and can be used to the erasing/precharge voltage line of carrying erasing/precharge, for carrying Wipe/cover the erasing of voltage/cover pressure-wire or taken for carrying the erasing voltage line of erasing voltage Generation.In some other embodiments, pre-charge pressure and/or cover voltage can be by other one or more groups Pressure-wire carries.

Erasing voltage and other circuit, such as sensing can be put by vertical gate voltage switching transistor 230 Big device, separates.

Fig. 7 illustrates another block diagram of the integrated circuit of Fig. 6, and vertical gate voltage is opened by it Close transistor 230 and be depicted as that there is relatively small size.

Vertical gate voltage switching transistor 230 is depicted as the size with an X-direction, with vertical The size of the X-direction of body NAND memory array 100 is corresponding.Vertical gate voltage switch What transistor 230 was depicted as having the Y direction of about 2 microns adds overall size, is essentially less than positioned at The Y direction of the embodiment of the voltage switching transistor 130 in base material about 150 microns adds overall size.

Semiconductor laminated structure in three-dimensional NAND memory array 100 and be positioned at vertical gate electricity Compress switch the semiconductor laminated structure in transistor 230, can share the technique steps such as formation and patterning Suddenly, therefore vertical gate voltage switching transistor 230 need not beyond making three-dimensional NAND storage Additional technical steps needed for device array 100.

Fig. 8 illustrates the more detailed block diagram of the integrated circuit of Fig. 6, more demonstrates and organizes vertical gate more Pole tension switching transistor and many groups fall to padding.

Three-dimensional NAND memory array 100 is coupled to global bit line by global bit line 120 and falls Pad 232.Global bit line falls to padding 232 and is electrically coupled to first group of vertical gate voltage switching transistor 234 and second group of vertical gate voltage switching transistor 238 both in one of source/drain end points.

First group of vertical gate voltage switching transistor 234 switchably electric property coupling global bit line falls Pad 232 and write and read voltage line fall to padding 236.When first group of vertical gate voltage switch crystal When pipe 234 is unlocked, global bit line is fallen to padding by first group of vertical gate voltage switching transistor 234 232 be electrically coupled to write and read voltage line fall to padding 236；When first group of vertical gate voltage is opened When pass transistor 234 is closed, first group of vertical gate voltage switching transistor 234 is by global bit line Fall to padding 232 and fall to padding 236 electrically isolated with write and read voltage line.Read voltage line falls and pads 236 are electrically coupled to for carrying write and the write of read voltage and read voltage line 132.

Second group of vertical gate voltage switching transistor 238 switchably electric property coupling global bit line falls Pad 232 and wipe/be pre-charged/cover pressure-wire falls to padding 240.When second group of vertical gate voltage switch When transistor 238 is unlocked, global bit line is fallen by second group of vertical gate voltage switching transistor 238 Pad 232 be electrically coupled to wipe/be pre-charged/cover pressure-wire and fall to padding 240；When second group of vertical gate When pole tension switching transistor 238 is closed, second group of vertical gate voltage switching transistor 238 will Global bit line falls to padding 232 and wipe/be pre-charged/covers pressure-wire to fall to padding 240 electrically isolated.Wipe Remove/be pre-charged/cover pressure-wire fall to padding 240 be electrically coupled to for carry wipe/be pre-charged/cover The erasing of voltage/be pre-charged/cover pressure-wire 134.

First group of vertical gate voltage switching transistor 234 and second group of vertical gate voltage switch crystal Pipe 238 by be used for carrying wipe/be pre-charged/cover the erasing of voltage/be pre-charged/cover pressure-wire 134 with Other circuit separate.Other circuit it may be that such as via write and read voltage line 132 connect Sensing amplifier.

Fig. 9 illustrates the structural perspective of an embodiment of the integrated circuit of Fig. 8.

Accumulation block (aggregated blocks) in Fig. 9 is depicted as Figure 10 to Figure 14 respectively Simplified perspective view.Three-dimensional NAND memory array (not illustrating) is by global bit line 120 coupling It is connected to global bit line fall to padding 232.Global bit line falls to padding 232 and is electrically coupled to first group of vertical gate Source in both pole tension switching transistor 234 and second group of vertical gate voltage switching transistor 238 One of pole/drain terminal.First group of vertical gate voltage switching transistor 234 switchably electric property coupling Global bit line falls to padding 232 and falls to padding 236 with write and read voltage line.Write and read voltage line Fall to padding 236 to be electrically coupled to for carrying write and the write of read voltage and read voltage line 242. Second group of vertical gate voltage switching transistor 238 switchably electric property coupling global bit line falls to padding 232 and wipe/be pre-charged/cover pressure-wire and fall to padding 240.Wipe/be pre-charged/cover pressure-wire and fall Pad 240 be electrically coupled to for carry wipe/be pre-charged/cover the erasing of voltage/be pre-charged/cover electricity Line ball 265.

In the structure of different blocks, such as, being positioned in semiconducting tape laminated construction, insulating barrier is permissible Identical or different with other layer.Adoptable representative insulant includes, Si oxide, silicon nitride, Silicon oxynitride, silicate or other materials.Can use and there is the dielectric constant less than silicon dioxide Low-k (low-k) material, such as SiCHO_x.Can also use and have higher than silicon dioxide The high dielectric constant material of dielectric constant, such as hafnium oxide (HfO_x), nitrogen hafnium oxide (HfON), Aluminium oxide (AlO_x), ru oxide (RuO_x) or titanium oxide (TiO_x)。

In the structure of different blocks, the such as semiconductor layer in semiconducting tape laminated construction, can With identical or different with other layer.The representative materials that can be used to be contained in quasiconductor includes, doping Or unadulterated polysilicon (spendable alloy, such as arsenic (As), phosphorus (P), boron (B)), (silicides, including titanium silicide (TiSi), cobalt silicide for the combination of semiconductor structure, metal silicide (CoSi)), conductor oxidate (including indium zinc oxide (InZnO), indium gallium zinc (InGaZnO)) And quasiconductor and the combination of metal silicide.

In the structure of different blocks, such as in bit line and conductive plunger, conductor layer can be metal, Conductive compound or the combination of materials described below, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), Cobalt (Co), nickel (Ni), titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride aluminium (TaAlN) Or other materials.Conductor layer can be to have electric conductivity and do not have the quasiconductor of characteristic of semiconductor after doping Layer.

The quantity of pad, semiconducting tape and pressure-wire of falling can be according to three-dimensional nand memory The capacity of array is adjusted.

The structural perspective of Figure 10 illustrates the bit line in the integrated circuit being positioned at Fig. 9 and bit line falls pad.

Three-dimensional NAND memory array (not illustrating) is coupled to by a plurality of global bit line 120 entirely Territory bit line falls and pads 232.These global bit line 120 are by one group of conductive plunger electric property coupling respectively Fall to global bit line pad 232 wire.Such as, each in bit line BL1-BL8, It is electrically coupled to be positioned at global bit line respectively fall the wherein semiconducting tape P1-P8 padding in 232. Be positioned at global bit line fall to padding semiconducting tape P1-P8 adjacent in 232 by intermediate insulation band that This is electrically insulated.

Figure 11 illustrates the first vertical gate voltage switching transistor in the integrated circuit being positioned at Fig. 9 Structural perspective.

First group of vertical gate voltage switching transistor 234 switchably electric property coupling global bit line falls Pad 232 and write and read voltage line fall to padding 236.First group of vertical gate voltage switching transistor 234 include semiconducting tape P1-P8, and it is electrically insulated from by intermediate insulation band.First group Vertical gate voltage switching transistor 234 can cover oxide, thus will be used for as channel layer Semiconducting tape P1-P8 isolates with the conductive gate material of top.This oxide can be multiple structure, Such as Si oxide/silicon nitride/Si oxide (ONO), Si oxide/low dielectric layer with high dielectric constant/ Si oxide (O/high-k/O), it is possible to provide high-k and reduce the doubt of capacity fall off.

Figure 12 illustrates the write of the integrated circuit being positioned in Fig. 9 and read voltage line and write and reading Power taking line ball fall pad structural perspective.

Write and read voltage line 242 are to be electrically coupled to one of them respectively by one group of conductive plunger Write and read voltage line fall pad 236 wire.It is positioned at write and read voltage line falls to padding 236 In adjacent semiconducting tape P1-P8 be electrically insulated from by intermediate insulation band.

When first group of vertical gate voltage switching transistor 234 receives a unlatching grid voltage, can be by It is positioned at the global bit line semiconducting tape P1-P8 padded in 232 that falls be electrically coupled to be positioned at write and read Power taking line ball falls the semiconducting tape P1-P8 padded in 236.Such as, will be located in global bit line to fall Semiconducting tape P1 in pad 232 is electrically coupled to be positioned at write and read voltage line falls to padding 236 In semiconducting tape P1.Other plane layers of semiconducting tape are also with this mode electric property coupling.

When first group of vertical gate voltage switching transistor 234 receives a closedown grid voltage, can be by It is positioned at global bit line to fall the semiconducting tape P1-P8 that pads in 232 and be positioned at write and read voltage line The semiconducting tape P1-P8 padded in 236 that falls is electrically isolated.Such as, will be located in global bit line to fall Semiconducting tape P in pad 232 and be positioned at write and read voltage line falls the quasiconductor padding in 236 Band P1 is electrically isolated.Other plane layers of semiconducting tape are also electrically isolated in this mode.

Figure 13 illustrates second group of vertical gate voltage switching transistor of the integrated circuit being positioned in Fig. 9 Structural perspective.

Second group of vertical gate voltage switching transistor 238 switchably electric property coupling global bit line falls Pad 232 and wipe/be pre-charged/cover pressure-wire falls to padding 240.In addition, second group of vertical gate The structure of voltage switching transistor 238 and first group of vertical gate voltage switching transistor 234 can be Similar.

Figure 14 illustrates the erasing of the integrated circuit being positioned in Fig. 9/be pre-charged/cover pressure-wire and erasing / be pre-charged/cover pressure-wire fall pad structural perspective.

Wipe/be pre-charged/to cover pressure-wire 265 be to be electrically coupled to it respectively by one group of conductive plunger In one wipe/be pre-charged/cover pressure-wire fall pad 240 wire.Be positioned at wipe/be pre-charged/cover Pressure-wire falls to padding semiconducting tape P1-P8 adjacent in 240 the most electrical by intermediate insulation band Insulation.

When second group of vertical gate voltage switching transistor 238 receives a unlatching grid voltage, can be by It is positioned at the global bit line semiconducting tape P1-P8 padded in 232 that falls to be electrically coupled to be positioned at erasing/preliminary filling Electricity/cover pressure-wire falls the semiconducting tape P1-P8 padded in 240.Such as, will be located in global bit line The semiconducting tape P1 padded in 232 that falls is electrically coupled to be positioned at and wipes/be pre-charged/cover pressure-wire and fall The semiconducting tape P1 in pad 240.Other plane layers of semiconducting tape are also electrical in this mode Couple.

When second group of vertical gate voltage switching transistor 238 receives a closedown grid voltage, can be by Be positioned at global bit line fall the semiconducting tape P1-P8 that pads in 232 and be positioned at wipe/be pre-charged/cover The pressure-wire semiconducting tape P1-P8 padded in 240 that falls is electrically isolated.Such as, will be located in universe position Line falls the semiconducting tape P1 that pads in 232 and be positioned at and wipe/be pre-charged/cover pressure-wire and fall to padding Semiconducting tape P1 in 240 is electrically isolated.Other plane layers of semiconducting tape are also in this mode Electrically isolated.

Figure 15 illustrates another detailed block diagram of the integrated circuit of Fig. 6, demonstrates that it passes through very Number or even bitlines access, rather than are accessed by whole bit lines as shown in Figure 8.

Three-dimensional NAND memory array 100 is coupled to global bit line by global bit line 120 and falls Pad 232.Global bit line falls to padding one of 232 source/drains being electrically coupled to following four group transistors On.This four group transistor is: the first odd number group vertical gate voltage switching transistor 244, first is even Array vertical gate voltage switching transistor the 245, second odd number group vertical gate voltage switching transistor 248 and the second even number set vertical gate voltage switching transistor 249.

First odd number group vertical gate voltage switching transistor 244 switchably electric property coupling global bit line Fall to padding 232 and odd number writes and read voltage line falls to padding 246.When the first odd number group vertical gate When voltage switching transistor 244 is opened, the first odd number group vertical gate voltage switching transistor 244 meeting Fall to padding by global bit line 232 be electrically coupled to odd number write and read voltage line fall to padding 246.When When first odd number group vertical gate voltage switching transistor 244 is closed, the first odd number group vertical gate electricity Global bit line can be fallen to padding 232 and fall with write and read voltage line odd number by the transistor 244 that compresses switch Pad 246 electrically isolated.Odd number write and read voltage line fall to padding 246 and are electrically coupled to for carrying The odd number write of write and read voltage and read voltage line 252.

First even number set vertical gate voltage switching transistor 245 switchably electric property coupling global bit line Fall to padding 232 and even number writes and read voltage line even number falls to padding 247.When the first even number set is vertical When grid voltage switching transistor 245 is opened, the first even number set vertical gate voltage switching transistor Global bit line can be fallen to pad 232 by 245 to be electrically coupled to even number and writes and read voltage line even number falls Pad 247.When the first even number set vertical gate voltage switching transistor 245 is closed, the first even number set Global bit line can fall to padding vertical gate voltage switching transistor 245 232 and even number writes and reading Pressure-wire even number falls to padding 247 electrically isolated.Even number write and read voltage line even number fall to padding 247 It is electrically coupled to the even number write for carrying write and read voltage and read voltage line 253.

Second odd number group vertical gate voltage switching transistor 248 switchably electric property coupling global bit line Fall to padding 232 and odd number wipe/be pre-charged/cover pressure-wire and fall to padding 250.When the second odd number group is vertical When grid voltage switching transistor 248 is opened, the second odd number group vertical gate voltage switching transistor Global bit line can be fallen to padding 232 by 248 to be electrically coupled to odd number and wipes/be pre-charged/cover pressure-wire and fall Pad 250.When the second odd number group vertical gate voltage switching transistor 248 is closed, the second odd number Global bit line can be fallen to padding 232 and odd number erasing/preliminary filling by group vertical gate voltage switching transistor 248 Electricity/cover pressure-wire and fall to padding 250 electrically isolated.Odd number wipes/is pre-charged/and cover pressure-wire and fall to padding 250 be electrically coupled to for carry wipe/be pre-charged/odd number that covers voltage wipes/is pre-charged/cover electricity Line ball 254.

Second even number set vertical gate voltage switching transistor 249 switchably electric property coupling global bit line Fall to padding 232 and wipe/be pre-charged/cover pressure-wire to fall to padding 251.When the second even number set vertical gate When voltage switching transistor 249 is opened, the second even number set vertical gate voltage switching transistor 249 meeting Global bit line falls to padding 232 be electrically coupled to even number and wipe/be pre-charged/cover pressure-wire and fall to padding 251.When the second even number set vertical gate voltage switching transistor 249 is closed, the second even number set is hung down Global bit line can fall to pad 232 and even number erasing by straight grid voltage switching transistor 249/be pre-charged/ Cover pressure-wire and fall to padding 251 electrically isolated.Even number wipes/is pre-charged/and cover pressure-wire and fall to padding 251 Be electrically coupled to for carry wipe/be pre-charged/even number that covers voltage wipes/is pre-charged/cover voltage Line 255.

First odd number group vertical gate voltage switching transistor the 244, first even number set vertical gate voltage Switching transistor the 245, second odd number group vertical gate voltage switching transistor 248 and the second even number set Vertical gate voltage switching transistor 249 can be with first group of vertical gate voltage depicted in Figure 11 Second group of vertical gate voltage switching transistor 238 depicted in switching transistor 234 and Figure 13 Identical.It addition, because have only to the semiconducting tape of even number or odd number, other each quasiconductor Band can replace by other materials.

First odd number group vertical gate voltage switching transistor the 244, first even number set vertical gate voltage Switching transistor the 245, second odd number group vertical gate voltage switching transistor 248 and the second even number set Odd number wiped/is pre-charged by vertical gate voltage switching transistor 249/cover pressure-wire 254 and 255 On erasing/be pre-charged/cover voltage and other circuit, such as via write and read voltage line 252 With 253 sensing amplifiers connected, separate.

Figure 16 illustrates the write of the integrated circuit being positioned in Figure 15 and read voltage line and write and reading Power taking line ball falls the structural perspective of pad, and it is accessed by even bitlines, rather than such as Figure 12 Shown in accessed by whole bit lines.

Even number write and read voltage line 253 are made by one group of conductive plunger and are electrically coupled to respectively wherein The write of one even number and read voltage line fall pad 247 wire.Even number write and read voltage line fall Pad 247 and include semiconducting tape P2, P4, P6 and P8.

In addition, even number write and read voltage line 253 are similar with write and read voltage line 242. Even number write and read voltage line fall to padding 247 can be with the write shown in Figure 12 and read voltage line Fall to padding 236 to be similar to.It addition, semiconducting tape P2, P4, P6 and P8 can take with other materials Generation.

Figure 17 illustrates the write of the integrated circuit being positioned in Figure 15 and read voltage line and write and reading Power taking line ball falls the structural perspective of pad, and it is accessed by odd bit lines, rather than such as Figure 12 Shown in accessed by whole bit lines.

Odd number write and read voltage line 252 are made by one group of conductive plunger and are electrically coupled to respectively wherein The write of one odd number and read voltage line fall pad 246 wire.Odd number write and read voltage line fall Pad 246 and include semiconducting tape P1, P3, P5 and P7.

In addition, odd number write and read voltage line 252 are similar with write and read voltage line 242. Odd number write and read voltage line fall to padding 246 can be with the write shown in Figure 12 and read voltage line Fall to padding 236 to be similar to.It addition, semiconducting tape P1, P3, P5 and P7 can take with other materials Generation.

Figure 18 illustrates the erasing of the integrated circuit being positioned in Figure 15/be pre-charged/cover pressure-wire and wiping Remove/being pre-charged/cover pressure-wire to fall the structural perspective of pad, it is accessed by even bitlines, Rather than accessed by whole bit lines as shown in figure 14.

Even number wipes/is pre-charged/and cover pressure-wire 255 and be made by one group of conductive plunger electric property coupling respectively To one of them even number wipe/be pre-charged/cover pressure-wire fall pad 251 wire.Even number erasing/pre- The pressure-wire that charges/cover falls to padding 251 and includes semiconducting tape P2, P4, P6 and P8.

In addition, even number wipe/be pre-charged/cover pressure-wire 255 and wipe/be pre-charged/cover voltage Odd number wipe/be pre-charged/cover pressure-wire 254 and be similar to.Even number wipes/is pre-charged/and cover pressure-wire and fall Pad 251 and can fall to padding 240 similar with the erasing shown in Figure 14/be pre-charged/cover pressure-wire.Separately Outward, semiconducting tape P2, P4, P6 and P8 can replace with other materials.

Figure 19 illustrates the erasing voltage line of the integrated circuit being positioned in Figure 15 and erasing voltage line falls The structural perspective of pad, it is accessed by odd bit lines, rather than passes through complete as shown in figure 14 Bit line accesses.

Odd number wipes/is pre-charged/and cover pressure-wire 254 and be made by one group of conductive plunger electric property coupling respectively To one of them odd number wipe/be pre-charged/cover pressure-wire fall pad 250 wire.Odd number erasing/pre- The pressure-wire that charges/cover falls to padding 250 and includes semiconducting tape P1, P3, P5 and P7.

In addition, odd number wipe/be pre-charged/cover pressure-wire 254 and wipe/be pre-charged/cover voltage Erasing/be pre-charged/cover pressure-wire 265 be similar to.Odd number wipes/is pre-charged/and cover pressure-wire and fall to padding 250 can fall to padding 240 similar with the erasing shown in Figure 14/be pre-charged/cover pressure-wire.It addition, Semiconducting tape P1, P3, P5 and P7 can replace with other materials.

Figure 20 illustrates the even number of the integrated circuit being positioned in Figure 15 and falls the structural perspective of pad, is used for Substitute the even number depicted in Figure 16 and Figure 18 to fall to padding.

Unlike depicted in Figure 16 and Figure 18, fallen by even number pad P2, P4, P6 and P8 are arranged in directly Line, fall pad P2, P4, P6 and P8 of the even number depicted in Figure 20 is arranged in checkerboard pattern.Remove Outside this, even number falls to padding P2, P4, P6 and P8 and falls with the even number depicted in Figure 16 and Figure 18 Pad 247 is similar with 251.It addition, even number falls, pad P2, P4, P6 and P8 can use other materials Replace.

Figure 21 illustrates the odd number of the integrated circuit being positioned in Figure 15 and falls the structural perspective of pad, is used for Substitute the odd number depicted in Figure 17 and Figure 19 to fall to padding.

Unlike depicted in Figure 16 and Figure 18, fallen by even number pad P2, P4, P6 and P8 are arranged in directly Line, fall pad P1, P3, P5 and P7 of the even number depicted in Figure 20 is arranged in checkerboard pattern.Remove Outside this, even number falls to padding P1, P3, P5 and P7 and falls with the odd number depicted in Figure 16 and Figure 18 Pad 246 is similar with 250.It addition, even number falls, pad P1, P3, P5 and P7 can use other materials Replace.

Figure 22 illustrates and is positioned on the wiring layer that Fig. 8 carries out in the integrated circuit accessed with whole bit lines Wiring block diagram.

Figure 22 illustrates a plurality of parallel digit lines BL1-BL8120 being positioned on metal level ML2, is coupled to Global bit line 232.

Figure 23 illustrates and is positioned at another wiring layer that Fig. 8 carries out in the integrated circuit accessed with whole bit lines On wiring block diagram.

Figure 23 illustrates a plurality of parallel write and read voltage line being positioned on metal level ML1 BLi1-BLi8242 is coupled to write and read voltage line falls to padding 236.Although being positioned at different metal layer On, write and the direction of routing of read voltage line BLi1-BLi8242 and bit line BL1-BL8120 phase With.BL_BIAS line 265 is coupled to wipe/be pre-charged/cover pressure-wire fall pad 240 erasing / it is pre-charged/covers pressure-wire.BIAS_SEL 262 carrying is used for controlling whether second group of vertical gate The grid voltage that voltage switching transistor 238 is turned on and off.BIAS_SEL line 264 carrying is used for Control whether the grid voltage being turned on and off by first group of vertical gate voltage switching transistor 234. Wherein BL_BIAS line 265, BIAS_SEL line 262 are all joined by parallel with BIAS_SEL line 264 Put on metal level ML1.BL_BIAS line 265, BIAS_SEL line 262 and BIAS_SEL The direction of routing of line 264 and bit line BL1-BL8120 and write and read voltage line BLi1-BLi8 242 orthogonals.

In another embodiment, the position of metal level ML1 and ML2 can change.Both such as Or one of them can be placed on metal level ML3 or higher position.In another embodiment, The direction of above-mentioned metal wire can be rotated an angle.

Figure 24 illustrates and is positioned at Figure 15 and carries out a wiring of the integrated circuit accessed with even number and odd bit lines Wiring block diagram on layer.

Figure 24 illustrates a plurality of parallel digit lines BL1-BL8120 being positioned on metal level ML2, is coupled to Global bit line 232.

Figure 25 illustrates and is positioned at Figure 15 and carries out another cloth of the integrated circuit accessed with even number and odd bit lines Wiring block diagram on line layer.

Figure 25 illustrates a plurality of parallel odd number write and read voltage line being positioned on metal level ML1 BLi1, BLi3, BLi5 and BLi7252, be coupled to odd number write and read voltage line falls to padding 246, and a plurality of parallel even number write that is positioned on metal level ML1 and read voltage line BLi2, BLi4, BLi6 and BLi8252, be coupled to write and read voltage line coupling is scolded and padded 247.No As Figure 23 is depicted, write and read voltage line herein are all distinguished into odd and even number Group.Although being positioned on different metal layer, odd number write and read voltage line BLi1, BLi3, BLi5, Even number write and read voltage line BLi2, BLi4, BLi6 and BLi8252 is also had with BLi7252 Direction of routing identical with bit line BL1-BL8120.

BL_BIAS line 254 be coupled to odd number fall to wipe/be pre-charged/cover pressure-wire and pad 250 Odd number wipes/is pre-charged/cover pressure-wire.BIAS_SEL line 255 is coupled to even number and falls erasing/pre- The pressure-wire that charges/cover pad 251 even number wipe/be pre-charged/cover pressure-wire.Unlike Figure 23 is painted As showing, these wipe/are pre-charged/and cover pressure-wire and be all distinguished into odd and even number group.

BIAS_SEL line 262 carrying is used for controlling whether the second odd number group vertical gate voltage switch The grid voltage that transistor 248 is turned on and off.BIAS_SEL line 273 carrying is used for controlling whether The grid voltage that second even number set vertical gate voltage switching transistor 249 is turned on and off.Unlike BIAS_SEL line 262 depicted in Figure 23, these BIAS_SEL lines be all distinguished into odd number and Even number group.

BIAS_SEL line 274 carrying is used for controlling whether the first odd number group vertical gate voltage switch The grid voltage that transistor 244 is turned on and off.BIAS_SEL line 275 carrying is used for controlling whether The grid voltage that first even number set vertical gate voltage switching transistor 245 is turned on and off.Unlike BIAS_SEL line 264 depicted in Figure 23, these BIAS_SEL lines be all distinguished into odd number and Even number group.

BL_BIAS line 254, BIAS_SEL line 255, BIAS_SEL line 272, BIAS_SEL Line 273, BIAS_SEL line 274 and BIAS_SEL line 275 are all arranged in parallel at metal level ML1 On.BL_BIAS line 254, BIAS_SEL line 255, BIAS_SEL line 272, BIAS_SEL Line 273, direction of routing and the bit line BL1-BL8 of BIAS_SEL line 274 and BIAS_SEL line 275 120 and odd number write and read voltage line BLi1, BLi3, BLi5 and BLi7252 even number write and Read voltage line BLi2, BLi4, BLi6 and BLi8 orthogonal.

In another embodiment, the position of metal level ML1 and ML2 can change.Both such as Or one of them can be placed on metal level ML3 or higher position.In another embodiment, The direction of above-mentioned metal wire can be rotated an angle.

Figure 26 illustrates a pair vertical gate switching transistor that can be utilized for write or read operation Simplified electrical circuit diagram.

The first transistor 312 is opened by gate voltage BL_SEL 310, makes sequentially to be electrically coupled to Bit line 300 and 330 electric property coupling each other of sensing amplifier 350.Transistor seconds 322 passes through grid Voltage BL_SEL 320 opens, and is thus electrically coupled to bit line 300 from BL_BIAS 340.With When carrying out write operation, numerical value is that the write voltage of 0V or Vdd passes through the first transistor 312 To bit line 300.When being used for being read, numerical value is about～the read voltage of 1V is brilliant through first Body pipe 312 reaches sensing amplifier 350.

Figure 27 illustrates and is positioned at Fig. 8 and carries out, in the integrated circuit accessed, can be utilized for whole bit lines The simplified electrical circuit diagram of the multipair vertical gate switching transistor of write or read operation.

Circuit depicted in Figure 27 is substantially similar with Figure 26, and difference is that switching transistor and sensing are put The quantity of big device increases along with the increase of bit line quantity.In order to control bit line 301, add first Transistor 314, transistor seconds 324, bit line 331 and sensing amplifier 351.Bit line 301, The effect of one transistor 314, transistor seconds 324, bit line 331 and sensing amplifier 351 is respectively With bit line 300, the first transistor 312, transistor seconds 322, bit line 330 and sensing amplifier 350 is similar.

Figure 28 illustrates and is positioned at Figure 15 and carries out in the integrated circuit accessed with even number and odd bit lines, available Carry out writing or the simplified electrical circuit diagram of multipair vertical gate switching transistor of read operation.

Circuit depicted in Figure 28 is substantially similar with Figure 27, and difference is that need to be spaced a bit lines is carried out Access, the most only even bitlines or odd bit lines can access.In the present embodiment, be used for into During row write operation, numerical value is that the write voltage of 0V or Vdd reaches position through the first transistor 312 Line BL 300；Or being used for when being read, numerical value is about～the read voltage of 1V is through first Transistor 312 reaches sensing amplifier 350.In the same time, when write operation or reading are just being grasped When being performed by bit line 300, do not performed by bit line 301 by any operation.The first transistor 312 is opened, Transistor seconds 324 is closed, and bit line 301 is coupled to 0V to be covered, or carries out pre-to it Charging, thus by bit line 301 and the write just carried out in adjacent bit lines 300 or read operation isolation.

Figure 29 illustrates the simplification electricity of the vertical gate switching transistor that can be utilized for erasing operation a pair Lu Tu.

The first transistor 312 is opened by gate voltage BL_SEL 310, makes sequentially to be electrically coupled to The bit line 300 and 330 of sensing amplifier 350 is electrically isolated from each other.Transistor seconds 322 passes through grid Voltage BL_SEL line 320 is opened, and thus bit line 300 is electrically coupled to BL_BIAS line 340. When being used for carrying out erasing operation, the erasing voltage of high intensity reaches bit line through transistor seconds 322 BL 300。

Figure 30 illustrates and is positioned at Fig. 8 and carries out, in the integrated circuit accessed, can be utilized for whole bit lines The simplified electrical circuit diagram of the multipair vertical gate switching transistor of erasing operation.

Circuit depicted in Figure 30 is substantially similar with Figure 29, and difference is that switching transistor and sensing are put The quantity of big device increases along with the increase of bit line quantity.In order to control bit line 301, add first Transistor 314, transistor seconds 324, bit line 331 and sensing amplifier 351.Bit line 301, The effect of one transistor 314, transistor seconds 324, bit line 331 and sensing amplifier 351 is respectively Amplify with bit line 300, the first transistor 312, transistor seconds 322, bit line BLi 330 and sensing Device 350 is similar.

Figure 31 illustrates and is positioned at Figure 15 and carries out in the integrated circuit accessed with even number and odd bit lines, available Carry out the simplified electrical circuit diagram of the multipair vertical gate switching transistor of erasing operation.

Circuit depicted in Figure 31 is substantially similar with Figure 28, and difference is only to wipe operation, and non-write Enter or read operation, it is necessary to carry out in the integrated circuit with even number or odd number bit line.Unlike Figure 28 Depicted, depicted in Figure 31 erasing operation, even number applies similar bias with odd number bit line.Cause This bit line BL 300 and BLi 330 has been applied in high intensity erasing bias.

Figure 32 illustrates the simplified electrical circuit diagram of the integrated circuit with vertical gate switching transistor.

This integrated circuit 475 includes the three-dimensional NAND Flash memory array described in above-described embodiment 460, it is positioned on the semiconductor substrate with conductor laminated construction, and has conductor laminated construction system The capacitor become.Line decoder 461 is coupled to the word of a plurality of row arrangement along memory array 460 Line 462.Column decoder in square frame 466 is coupled to a plurality of tandem and selects line 464, deposits along correspondence The row arrangement of the laminated construction in memory array 460, is used for the memory element from memory array 460 Middle reading or write data.Plane decoder 458 is coupled to memory array via multiple bit lines 459 Multiple plane layers of 460.Address then by bus 465 provide to line decoder 461, column decoder and Plane decoder 458.Page buffer 463 is coupled to the column decoder in square frame 466 and memorizer Array 460.Page buffer 463 includes the three-dimensional high voltage switching transistor described in above-described embodiment. Page buffer 463 is to pointing to the bit line of memory array 460 and pointing to the bit line of sensing amplifier Or the pressure-wire being used for carrying erasing bias carries out multiplexing (multiplexes).This multiplexing Odd and even number circuit can be distinguished into.Page buffer 463 can include for being read out and verifying The sensing amplifier of operation.Page buffer 463 can include other circuit, such as fault detect electricity Whether road (fail detection circuitry), pass through/retry/failure after being used for detecting verification operation (pass/retry/fail), the data quick memory (data of the reading/writing data of sensing write operation Cache) and caching data decoding (cache decoding)/output buffering (output buffer). Data connect end via the Data In-Line 471 input/output from integrated circuit 475, or from integrated Circuit 475 other Data Sources interiorly or exteriorly provide the data input structure to square frame 466. In the present embodiment, other circuit 474, such as general processor (general purpose processor) Or special-purpose applications circuit (special purpose application circuitry) or fast by NAND Flash memory array is supported and provides the module combination of SOC(system on a chip) (system-on-a-chip) also to comprise On this integrated circuit.Data via DOL Data Output Line 472 from integrated circuit 475 in square frame 466 Data export structure provide to the input/output on integrated circuit 475 and connect interface, or from integrated electricity Road 475 other data endpoints interiorly or exteriorly.

In the present embodiment, use bias to arrange the controller of state machine 469, control by voltage source Or the application of power supply 468 produced or provided bias arranges voltage, such as, read, write, wipe, Erasing checking and write verification；And control to be used for controlling first group and second group of vertical gate voltage The grid voltage of switching transistor.This controller can use known special purpose logic circuitry to add To realize.In another embodiment, controller includes being implemented in identical integrated circuit, is used for performing Operation program is to control the general processor of element operation.In another embodiment, can use special The combination of purposes logic circuit and general processor realizes this controller.

In certain embodiments, can by wiring and decoding change change respectively plane decoder, Column decoder and the position of line decoder.

Aforementioned used adjective, such as top (above), lower section (below), top (top), Bottom (bottom), above (over) or following (under) etc., be only for describing explanation with Help to understand, and be not used to limit the scope of the present invention.

Figure 33 illustrates the section of structure of the different mask combinations in the Luo Zhe district that can produce different depth. In order to form the described herein plot structure that falls, dielectric substrate 26 forms dielectric layer 22 and conduction The staggered laminated construction 20 of layer 24.In the present embodiment, 8 groups of dielectric layers 22 and conductive layer are included 24, respectively with 22.0 to 22.7, and 24.0 to 24.7 are indicated.Hard mask 30, etching Stop layer 28 and the first dielectric layer 22 cover on laminated construction 20.According to using the first photoresist The repeatedly etching step that mask the 52, second photoresist mask 54 and the second photoresist mask 56 are carried out Close mask regions 40 and the combination in opening etching district 38, etch the contact openings of different depth 32.0 to 32.7.

First photoresist mask 52 has an opening etching district 38 and covers the contact openings 32 of half (such as 4, in this embodiment) and between opening etching district 38 and contact openings 32 Hard mask 30.First photoresist mask 52 has a closing mask regions 40 simultaneously and covers other contacts Opening 32 and the hard mask 30 between closing mask regions 40 and contact openings 32.Second photoetching Glue mask 54 has opening etching district, interlaced with each other 2 38 and 2 closing mask regions 40, covers The contact openings 32 of 1/4th (such as 2, in this embodiment) and be positioned at these opening etchings District 38 and the hard mask 30 closed between mask regions 40 and contact openings 32.3rd photoresist mask 56 have opening etching district, interlaced with each other 4 38 and 4 closes mask regions 40, cover eight/ The contact openings 32 of one (such as 1, in this embodiment) and be positioned at these opening etching districts 38 And the hard mask 30 closed between mask regions 40 and contact openings 32.

Reactive ion can be used to etch, such as comprise tetrafluoromethane/nitrogen/difluoromethane/hydrogen bromide/ Helium-oxygen/helium (CF₄/N₂/CH₂F₂/HBr/He-O₂/ He) chemical etchant, it is suitable to stop at The top of conductive layer 24.0 to 24.7.

In the present embodiment, the pad that falls is arranged in a straight line, and corresponds to be arranged in a straight line in mask Close mask regions 40 and opening etching district 38.In other embodiments of the present invention, close mask District 40 and opening etching district 38 are arranged in checkerboard pattern adjacent to each other, thus produce and have each other Odd number or the even number of adjacent checkerboard pattern fall to padding.

More information about forming method and technology that connection conductor is connected to pad have been disclosed in Numbering US 13/049, the U.S. patent application case of 303, filing date on March 16th, 2011, mark Entitled " REDUCED NUMBER OF MASK FOR IC DEVICE WITH STACKED CONTACT LEVELS " and the U.S. patent application case of numbering US 13/114,931, the applying date It is on May 24th, 2011, entitled " MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD ", wherein the content of these application cases will be incorporated by reference into The mode of (incorporated by reference), records this full patent texts among present disclosure. These application cases and this case have co-inventor.

Although the present invention is open as above with preferred embodiment, so it is not limited to the present invention.This Processing step and structure described in place are not covered by making the complete manufacture process of over all Integration circuit.This The different production of integrated circuits technology that invention can be currently known with many or future is developed are closed And implement.Persond having ordinary knowledge in the technical field of the present invention, in the spirit without departing from the present invention With in scope, when making various changes and modification.Therefore, protection scope of the present invention is when depending on enclosing The protection domain that defined of claims be as the criterion.

Claims (20)

1. an integrated circuit, including:

One three-dimensional NAND memory array, including multiple memory transistors；

Multiple bit lines, bit lines different in these multiple bit lines is coupled to this solid nand memory Multiple different parts of array；And

Multiple transistors pair, have one semiconductor laminated (stack of semiconductor layers), Multiple different layers during this is semiconductor laminated include the multiple different crystal of these multiple pair of transistors It is right to manage；Each of these multiple pair of transistors comprises a first transistor and a transistor seconds, And this first transistor and this transistor seconds have one first source/drain end points, one second source electrode/ Drain terminal and one the 3rd source/drain end points；

Wherein, this first transistor has this first source/drain end points and the 3rd source/drain terminal Point；And this transistor seconds has this second source/drain end points and the 3rd source/drain end points； And

This first source/drain terminal is electrically coupled to an erasing voltage line；This second source/drain terminal It is electrically coupled to corresponding in a plurality of write/read voltage line one；

3rd source/drain terminal is electrically coupled to corresponding in these multiple bit lines one article.

2. integrated circuit as claimed in claim 1, also includes

One first grid, is used for controlling all these the first transistors of these multiple pair of transistors； And

One second grid, is used for controlling all these transistor secondses of these multiple pair of transistors.

3. integrated circuit as claimed in claim 2, wherein this first grid controls these a plurality of positions Whether line is coupled to these the first source/drain end points of these multiple pair of transistors；And this second gate Pole controls whether these multiple bit lines are coupled to these two source/drains of these multiple pair of transistors End points.

4. integrated circuit as claimed in claim 1, wherein this solid NAND memory array bag Include multiple semiconducting tape laminated construction (stacks of semiconductor strips), arrange as The a plurality of transistor channels of these different memory transistors in this solid NAND memory array；

And this semiconductor laminated includes:

One first semiconducting tape laminated construction, configuration is different from as these multiple pair of transistors The transistor channels of these the first transistors；And

One second semiconducting tape laminated construction, configuration is different from as these multiple pair of transistors The transistor channels of these transistor secondses.

5. integrated circuit as claimed in claim 4, is wherein positioned at this first semiconducting tape lamination A plurality of semiconducting tape in structure, a plurality of partly leading of being positioned in this second semiconducting tape laminated construction Body band and be positioned at a plurality of semiconducting tape in these multiple conductive strap laminated construction, shares many Individual plan-position (plane positions).

6. integrated circuit as claimed in claim 1, also includes a circuit, is used for this erasing electricity Line ball produces one first group of voltage, and these write/read voltage lines are produced one second group of voltage.

7. integrated circuit as claimed in claim 4, is wherein positioned at this first semiconducting tape lamination These semiconducting tape in structure are electrically coupled in these multiple bit lines and these semiconducting tape These adjacent bit lines.

8. integrated circuit as claimed in claim 4, is wherein positioned at this first semiconducting tape lamination These semiconducting tape in structure be electrically coupled in these multiple bit lines not with these quasiconductors These bit lines that band is adjacent.

9. integrated circuit as claimed in claim 2, also includes a circuit,

For performing following actions:

Open multiple the first transistor；And close multiple transistor seconds；And

Open multiple transistor seconds；And close multiple the first transistor.

10. the method operating multiple bit lines, these bit lines are electrically coupled to have multiple storage crystalline substance The three-dimensional NAND memory array of the one of body pipe, these the most different bit lines are electrically coupled to this and stand The different parts of body NAND memory array, the method includes:

Switchably (switchably) these bit lines are electrically coupled to following one of them:

I () one first group of voltage, it is by this solid NAND memory array at least one first First group of multiple transistor of storage operation kenel couple, wherein these first group of multiple crystal Pipe has one first semiconducting tape laminated construction；And

(ii) one second group of voltage, it is by this solid NAND memory array at least one second Second group of multiple transistor of storage operation kenel couple, wherein these second group of multiple crystal Pipe has one second semiconducting tape laminated construction；And this second memory operational configurations and this first deposit Reservoir operational configurations is different.

11. methods as claimed in claim 10, are wherein positioned at this first semiconducting tape lamination knot A plurality of semiconducting tape in structure, is provided to as different these in these first group of multiple transistor Multiple transistor channels of transistor；Be positioned in this second semiconducting tape laminated construction a plurality of partly leads Body band, is provided to the multiple crystalline substances as these transistors different in these second group of multiple transistor Body tube passage；And this solid NAND memory array includes multiple semiconducting tape laminated construction, Multiple crystal as these memory transistors different in this solid NAND memory array are set Tube passage.

12. methods as claimed in claim 11, are positioned in this first semiconducting tape lamination many Bar semiconducting tape, a plurality of semiconducting tape being positioned in this second semiconducting tape laminated construction and It is positioned at a plurality of semiconducting tape in these multiple semiconducting tape laminated construction, shares multiple plane positions Put；Wherein, the multiple plan-position of different these corresponds to different transistor channels and arranges.

13. methods as claimed in claim 10, wherein this first memory operational configurations includes wiping Remove；And this second memory operational configurations includes write and reads at least one of the two.

14. methods as claimed in claim 10, wherein this first memory operational configurations includes wiping Remove, be pre-charged and cover；And this second memory operational configurations includes write and reads.

15. method as claimed in claim 12, the wherein not corresponding lines couplings in these multiple bit lines These Different Plane positions being connected in this solid NAND memory array.

16. methods as claimed in claim 10, also include:

Produce the first group of voltage being applicable to this first memory operational configurations；And

Produce the second group of voltage being applicable to this second memory operational configurations.

17. methods as claimed in claim 10, are wherein positioned at this first semiconducting tape lamination knot These semiconducting tape in structure are electrically coupled in these multiple bit lines and these semiconducting tape phases Adjacent bit line.

18. methods as claimed in claim 10, are wherein positioned at this first semiconducting tape lamination knot These semiconducting tape in structure be electrically coupled in these multiple bit lines not with these semiconductor bars With adjacent bit line.

19. methods as claimed in claim 10, also include:

I () opens this first group of multiple transistor；And close this second group of multiple transistor, pass through This first group of voltage is coupled to these multiple bit lines at least to carry out this first memory operational configurations； And

(ii) this second group of multiple transistor is opened；And close this first group of multiple transistor, logical Cross and this second group of voltage is coupled to these multiple bit lines at least to carry out this second memory manipulation type State.

The manufacture method of 20. 1 kinds of integrated circuits, including:

There is provided a three-dimensional NAND memory array so that it is include multiple memory transistor；

Multiple bit lines is provided, makes these bit lines different in these multiple bit lines be coupled to this solid Multiple different parts of NAND memory array；And

Multiple transistor pair is provided so that it is have one semiconductor laminated, many during this is semiconductor laminated Individual different layers includes multiple these the different transistors pair of these multiple pair of transistors；These are multiple The each of pair of transistors comprises a first transistor and a transistor seconds, and this first transistor With this transistor seconds, there is one first source/drain end points, one second source/drain end points and 1 Three source/drain end points；

Wherein this first transistor includes this first source/drain end points and the 3rd source/drain end points； This transistor seconds includes this second source/drain end points and the 3rd source/drain end points；

This first source/drain terminal is electrically coupled to an erasing voltage line；This second source/drain terminal It is electrically coupled to corresponding in a plurality of write/read voltage line one；

3rd source/drain terminal is electrically coupled to corresponding in these multiple bit lines one article.