CN106297710A - Voltage hold circuit and driving method, GOA unit and circuit, display floater - Google Patents
Voltage hold circuit and driving method, GOA unit and circuit, display floater Download PDFInfo
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- CN106297710A CN106297710A CN201610816585.3A CN201610816585A CN106297710A CN 106297710 A CN106297710 A CN 106297710A CN 201610816585 A CN201610816585 A CN 201610816585A CN 106297710 A CN106297710 A CN 106297710A
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- 239000010409 thin film Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of voltage hold circuit and driving method, GOA unit and circuit, display floater, relates to Display Technique field, for solving the problem that prior art interior joint voltage possibly cannot keep.This voltage hold circuit includes: the first control unit, the second control unit and output unit；The voltage of primary nodal point and the first level terminal is pulled together or is pulled together by the voltage of primary nodal point with second electrical level end under the control keeping the voltage of node at voltage by the first control unit；Second control unit is for pulling together the voltage of secondary nodal point and the first level terminal or pulled together by the voltage of secondary nodal point with second electrical level end under the control of the voltage of the control signal of control signal input input and primary nodal point；Output unit is for keeping node to input the voltage of the first level terminal to voltage under the control of the voltage of secondary nodal point.The present invention is for the manufacture of display floater.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of voltage hold circuit and driving method, GOA unit and electricity
Road, display floater.
Background technology
Thin film transistor liquid crystal display screen is (English omnidistance: Thin Film Transistor Liquid Crystal
Display, is called for short: TFT-LCD) obtain in the electronic products such as display, mobile phone, digital camera, digital photo frame at present
It is widely applied.In order to further realize human-computer interaction, improve Consumer's Experience, prior art also proposed touch and show
Panel, and embedded touch (English full name: In Cell Touch) display floater integrated contact panel function and display function in
Integrally, the advantage such as the most frivolous, low cost, the mainstream development direction of embedded touch-control display panel especially.
Generally, the mode that In-cell touch display panel uses timesharing to drive is driven.Concrete, embedded touch shows
Show that a frame time is divided into display stage and touch-control stage by panel, in each grid line, input raster data model line by line in the display stage
Signal, display floater shows, does not carry out touch-control and drive the output of signal in this stage；Electricity is driven to touch-control in the touch-control stage
Pole input touch-control drives signal, and display floater carries out touch-control sensing, suspends the input of gate drive signal, under entrance in this stage
The input of gate drive signal is proceeded during one display stage.Generally, gate drive signal enter through integrated grid
Drive circuit (English: Gate Drive On Array, it is called for short: GOA) carry out.GOA circuit includes multiple GOA unit, each
GOA unit connects a grid line, for inputting gate drive signal in connected grid line.During touch-control shows, if
Enter the touch-control stage after n-th grade of GOA unit output gate drive signal, then terminate once to show the stage in entrance in the touch-control stage
Time need to ensure that (n+1)th grade of GOA unit can normally export gate drive signal.And ensure that (n+1)th grade of GOA unit can be normal
The key point of output gate drive signal is to ensure that the pull-up node in (n+1)th grade of GOA unit is still at the end of the touch-control stage
Keep high level.But, due to touch-control phases-time is longer and TFT by after still have a small amount of electric charge and flow through, therefore touch-control rank
Section terminates latter first needs the pull-up node exporting the GOA unit of gate drive signal may become low level.
Summary of the invention
Embodiments of the invention provide a kind of voltage hold circuit, GOA unit, GOA circuit and display floater, are used for solving
The problem that certainly voltage of prior art interior joint possibly cannot keep.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
First aspect, it is provided that a kind of voltage hold circuit, including: the first control unit, the second control unit and output
Unit；
Described first control unit connects the first level terminal, second electrical level end, primary nodal point and voltage and keeps node, uses
In keeping the voltage of the voltage of described primary nodal point Yu described first level terminal at described voltage under the control of voltage of node
Pull together or the voltage of the voltage of described primary nodal point with described second electrical level end is pulled together；
Described second control unit connection control signal input, secondary nodal point, described first level terminal, described second electricity
Flush end and described primary nodal point, for the control signal inputted at described control signal input and the electricity of described primary nodal point
Under the control of pressure, the voltage of the voltage of described secondary nodal point Yu described first level terminal is pulled together or by described secondary nodal point
Voltage pulls together with the voltage of described second electrical level end；
Described output unit connects described first level terminal, described secondary nodal point and described voltage and keeps node, is used for
Node is kept to input the voltage of described first level terminal to described voltage under the control of the voltage of described secondary nodal point.
Optionally, described first control unit includes: the first transistor and transistor seconds；
First pole of described the first transistor connects described first level terminal, and the second pole of described the first transistor connects institute
Stating primary nodal point, the grid of described the first transistor connects the first pole of described the first transistor；
First pole of described transistor seconds connects described primary nodal point, and the second pole of described transistor seconds connects described
Second electrical level end, the grid of described transistor seconds connects described voltage and keeps node.
Optionally, described second control unit includes: third transistor and the 4th transistor；
First pole of described third transistor connects described first level terminal, and the second pole of described third transistor connects institute
Stating secondary nodal point, the grid of described third transistor connects described control signal input；
First pole of described 4th transistor connects described secondary nodal point, and the second pole of described 4th transistor connects described
Second electrical level end, the grid of described 4th transistor connects described primary nodal point.
Optionally, described output unit includes: the 5th transistor；
First pole of described 5th transistor connects described first level terminal, and the second pole of described 5th transistor connects institute
Stating the pull-up node of GOA unit, the grid of described 5th transistor connects described secondary nodal point.
Optionally, each transistor is N-type transistor.
Second aspect, it is provided that the driving method of a kind of voltage hold circuit, for driving described in any one of first aspect
Voltage hold circuit；Described method includes:
First stage, the first control unit keeps the voltage of primary nodal point and the at voltage under the control of the voltage of node
The voltage of two level terminal pulls together；Control signal that second control unit inputs at control signal input and the voltage of primary nodal point
Control under the voltage of secondary nodal point and the voltage of the first level terminal are pulled together；
Second stage, the first control unit keeps the voltage of primary nodal point under the control of the voltage of voltage holding node；
Second section is kept under control signal that second control unit inputs at control signal input and the control of the voltage of primary nodal point
The voltage of point；Output unit keeps node to carry out by the first level portvoltage under the control of the voltage of described secondary nodal point
Charging；
Phase III, the first control unit keeps the voltage of primary nodal point and the at voltage under the control of the voltage of node
The voltage of one level terminal pulls together；Control signal that second control unit inputs at control signal input and the voltage of primary nodal point
Control under the voltage of the voltage of secondary nodal point with second electrical level end is pulled together.
The third aspect, it is provided that a kind of GOA unit, described GOA unit includes: signal input part, clock signal terminal, grid drive
Dynamic signal output part, pull-up node, reset signal end and the voltage hold circuit described in any one of first aspect；
Wherein, the voltage of voltage hold circuit described in described pull-up Node connectedness keeps node.
Fourth aspect, it is provided that a kind of GOA circuit, including the GOA unit described in the third aspect of multiple cascades；
The signal input part of the 1st grade of GOA unit connects initial signal end, and the reset signal end of described 1st grade of GOA unit is even
Connecing the signal output part of the 2nd grade of GOA unit, the signal output part of described 1st grade of GOA unit connects the signal of the 2nd grade of GOA unit
Input；
The signal input part of n-th grade of GOA unit connects the signal output part of (n-1)th grade of GOA unit, and described n-th grade of GOA is mono-
The reset signal end of unit connects the signal output part of (n+1)th grade of GOA unit, and the signal output part of described n-th grade of GOA unit connects
The signal input part of (n+1)th grade of GOA unit；
Wherein, n is the positive integer more than 1.
Optionally, the control signal input of the voltage hold circuit of n-th grade of GOA unit connects (n-1)th grade of GOA unit
Signal output part.
5th aspect, it is provided that a kind of display floater, including the GOA circuit described in any one of fourth aspect.
The voltage hold circuit that the embodiment of the present invention provides, including the first control unit, the second control unit and output
Unit, wherein the voltage of the voltage of primary nodal point and the first level terminal can be pulled together or by primary nodal point by the first control unit
The voltage of voltage and second electrical level end pull together, the second control unit can be by the voltage of secondary nodal point and the electricity of the first level terminal
Pressure pulls together or is pulled together by the voltage of the voltage of secondary nodal point with second electrical level end, and output unit can be at the voltage of secondary nodal point
Control under keep node to input the voltage of the first level terminal, i.e. above-described embodiment to voltage can keeping node by voltage
The voltage of Control of Voltage primary nodal point, then by voltage and the control signal of control signal input input of primary nodal point
Control the voltage of secondary nodal point, finally keep node to fill by the first level terminal to voltage under the Control of Voltage of secondary nodal point
Electricity is so the embodiment of the present invention can keep voltage to keep the high level of node when voltage keeps node to be high level, the most logical
Cross above-mentioned voltage hold circuit and can solve the problem that prior art interior joint voltage possibly cannot keep.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to embodiment or description of the prior art
The accompanying drawing used required in is briefly described, it should be apparent that, the accompanying drawing in describing below is only some of the present invention
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to attached according to these
Figure obtains other accompanying drawing.
The schematic diagram of the voltage hold circuit that Fig. 1 provides for embodiments of the invention；
The circuit diagram of the voltage hold circuit that Fig. 2 provides for embodiments of the invention；
The flow chart of steps of the driving method of the voltage hold circuit that Fig. 3 provides for embodiments of the invention；
The time sequence status schematic diagram of the scanning signal of the voltage hold circuit that Fig. 4 provides for embodiments of the invention；
The schematic diagram of the GOA unit that Fig. 5 provides for embodiments of the invention；
The schematic diagram of the GOA circuit that Fig. 6 provides for embodiments of the invention；
The time sequence status schematic diagram of the scanning signal of the GOA circuit that Fig. 7 provides for embodiments of the invention；
The schematic diagram of the another kind of GOA circuit that Fig. 8 provides for embodiments of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
The transistor used in all embodiments of the invention can be all thin film transistor (TFT) or field effect transistor or other characteristics
Identical device, is mainly switching transistor according to the transistor that effect embodiments of the invention in circuit are used.By
In the switching transistor used here source electrode, drain electrode be symmetrical, so its source electrode, drain electrode can exchange.At this
In bright embodiment, for distinguishing transistor the two poles of the earth in addition to grid, wherein will be referred to as the first pole in a pole, another pole is referred to as second
Pole.By the form in accompanying drawing specify the intermediate ends of transistor be grid, signal input part be source electrode, signal output part be drain electrode.
In addition the switching transistor that the embodiment of the present invention is used includes p-type switching transistor and N-type switching transistor two kinds, wherein, P
Type switching transistor turns on when grid is low level, ends when grid is high level；N-type switching transistor is at grid to be
Turn on during high level, end when grid is low level.
In addition it is also necessary to explanation, the printed words such as " first ", " second " in the application are only used to function and work
Making a distinction with essentially identical identical entry or similar item, the printed words such as " first ", " second " are not to quantity and execution time
Sequence is defined.
Embodiments of the invention provide a kind of voltage hold circuit, concrete, shown in reference Fig. 1, and this voltage hold circuit
Including: the first control unit the 11, second control unit 12 and output unit 13.
Wherein, the first control unit 11 connects the first level terminal V1, second electrical level end V2, primary nodal point a and voltage guarantor
Hold node PU1, by voltage and the first level terminal V1 of primary nodal point a under the control keeping the voltage of node PU1 at voltage
Voltage pull together or the voltage of the voltage of primary nodal point a with second electrical level end V2 pulled together.
Second control unit 12 connection control signal input Input, secondary nodal point b, the first level terminal V1, second electrical level
End V2 and primary nodal point a, at the control signal of control signal input Input input and the voltage of primary nodal point a
By the voltage of secondary nodal point b and the voltage of the first level terminal V1 pulls together or by the voltage of secondary nodal point b and the second electricity under control
The voltage of flush end V2 pulls together.
Output unit 13 connects the first level terminal V1, secondary nodal point b and voltage keeps node PU1, at second section
Node PU1 is kept to input the voltage of the first level terminal V1 to voltage under the control of the voltage of some b.
The voltage hold circuit that the embodiment of the present invention provides, including the first control unit, the second control unit and output
Unit, wherein the voltage of the voltage of primary nodal point and the first level terminal can be pulled together or by primary nodal point by the first control unit
The voltage of voltage and second electrical level end pull together, the second control unit can be by the voltage of secondary nodal point and the electricity of the first level terminal
Pressure pulls together or is pulled together by the voltage of the voltage of secondary nodal point with second electrical level end, and output unit can be at the voltage of secondary nodal point
Control under keep node to input the voltage of the first level terminal, i.e. above-described embodiment to voltage can keeping node by voltage
The voltage of Control of Voltage primary nodal point, then by voltage and the control signal of control signal input input of primary nodal point
Control the voltage of secondary nodal point, finally keep node to fill by the first level terminal to voltage under the Control of Voltage of secondary nodal point
Electricity is so the embodiment of the present invention can keep voltage to keep the high level of node when voltage keeps node to be high level, the most logical
Cross above-mentioned voltage hold circuit and can solve the problem that prior art interior joint voltage possibly cannot keep.
Further, with reference to shown in Fig. 2, the first control unit 11 includes: the first transistor T1 and transistor seconds T2；
First pole of the first transistor T1 connects the first level terminal V1, and second pole of the first transistor T1 connects primary nodal point
The grid of a, the first transistor T1 connects first pole of the first transistor T1；
First pole of transistor seconds T2 connects second pole of primary nodal point a, transistor seconds T2 and connects second electrical level end
The grid of V2, transistor seconds T2 connects voltage and keeps node PU1.
Second control unit 12 includes: third transistor T3 and the 4th transistor T4；
First pole of third transistor T3 connects the first level terminal V1, and the second pole of third transistor connects secondary nodal point b,
The grid connection control signal input Input of third transistor T3；
First pole of the 4th transistor T4 connects second pole of secondary nodal point b, the 4th transistor T4 and connects second electrical level end
The grid of V2, the 4th transistor T4 connects primary nodal point a.
Output unit 13 includes: the 5th transistor T5；
First pole of the 5th transistor T5 connects second pole of the first level terminal V1, the 5th transistor T5 and connects voltage holding
The grid of node PU1, the 5th transistor T5 connects secondary nodal point b.
Yet another embodiment of the invention provides driving of a kind of voltage hold circuit for driving any of the above-described embodiment to provide
Dynamic method, concrete, with reference to shown in Fig. 3, the method comprises the steps:
S31, first stage, the first control unit voltage keep node voltage control under by the voltage of primary nodal point
Pull together with the voltage of second electrical level end；Control signal that second control unit inputs at control signal input and primary nodal point
Under the control of voltage, the voltage of secondary nodal point and the voltage of the first level terminal are pulled together.
S32, the first control unit keep the voltage of primary nodal point under the control of the voltage of voltage holding node；Second control
The electricity of secondary nodal point is kept under control signal that unit processed inputs at control signal input and the control of the voltage of primary nodal point
Pressure；Output unit keeps node to be charged by the first level portvoltage under the control of the voltage of secondary nodal point.
S33, phase III, the first control unit voltage keep node voltage control under by the voltage of primary nodal point
Pull together with the voltage of the first level terminal；Control signal that second control unit inputs at control signal input and primary nodal point
Under the control of voltage, the voltage of the voltage of secondary nodal point with second electrical level end is pulled together.
The driving method of the voltage hold circuit that above-described embodiment provides, in first stage the first control unit by first segment
The voltage of voltage and the second electrical level end of point pulls together, and the second control unit is by the voltage of secondary nodal point and the voltage of the first level terminal
Pull together；Keep the voltage of primary nodal point, the second control unit to keep the voltage of secondary nodal point in second stage the first control unit,
Output unit keeps node to be charged, on the 3rd rank by the first level portvoltage under the control of the voltage of secondary nodal point
The voltage of primary nodal point and the voltage of the first level terminal are pulled together by section the first control unit, and the second control unit is by secondary nodal point
Voltage pulls together with the voltage of second electrical level end, i.e. voltage all can be kept node to carry out before the phase III by above-described embodiment
Charging, therefore the driving method of the voltage hold circuit that above-described embodiment provides can solve prior art interior joint voltage possibility
The problem that cannot keep.
Referring to the time-state method shown in Fig. 4, voltage shown in voltage hold circuit shown in Fig. 2 and Fig. 3 is kept electricity
The operation principle of the driving method on road illustrates.Wherein, it is grid high level with each transistor in voltage hold circuit
Time conducting N-type transistor, the first level terminal V1 and second electrical level end V2 be provided which stable DC voltage and the first level terminal V1
The high level voltage, the second electrical level end V2 that there is provided illustrate as a example by providing low level voltage.Exemplary, second electrical level end V2
Can be with ground connection.Fig. 4 shows the control signal of control signal outfan Input, the voltage of primary nodal point a, secondary nodal point b
The time sequence status of the voltage of voltage and voltage holding node PU1, and provide the time sequence status of three phases, wherein, first
Stage is t1；Second stage is t2；Phase III is t3.
In the t1 stage, voltage keeps node PU1 high level, therefore transistor seconds T2 conducting, and second electrical level end V2 is by the
It is low level that low level is inputted primary nodal point a, primary nodal point a by two-transistor T2, the 4th transistor T4 cut-off.Again because controlling
Signal input part Input is high level, therefore the conducting of third transistor T3, and the first level terminal V1 passes through third transistor T3 by height
Level input secondary nodal point b, secondary nodal point b are high level.Because secondary nodal point b high level, therefore the 5th transistor T5 conducting,
Voltage is kept node PU1 to be charged by the 5th transistor T5 by the first level terminal V1.
In the t2 stage, control signal input Input low level, third transistor T3 is ended, again because voltage keeps node
PU1 is high level, therefore transistor seconds T2 cut-off, and low level is inputted first by transistor seconds T2 by second electrical level end V2
Node a, primary nodal point a become low level, the 4th transistor T4 cut-off.Because third transistor T3 and and the 4th transistor T4 equal
Cut-off, therefore secondary nodal point b suspension joint.Due to third transistor T3 and the parasitic capacitance of the 4th transistor T4, in the t1 stage
Storing electric charge, and do not have discharge path in this stage, the electric charge therefore stored still makes secondary nodal point b keep high point to put down, because
Secondary nodal point b keeps high level, therefore the 5th transistor T5 conducting, and voltage is protected by the first level terminal V1 by the 5th transistor T5
A PU1 that serves as a diplomatic envoy is charged, and voltage keeps node PU1 to keep high level.
In the t3 stage, the grid of the first transistor T1 connects the first level terminal V1, therefore the first transistor T1 conducting；Because it is electric
Pressure keeps node PU1 to be low level, so transistor seconds T2 cut-off；First level terminal V1 is electric by height by the first transistor T1
Flat input primary nodal point a, primary nodal point a high level.Again because of control signal input Input low level, third transistor T3
Cut-off, primary nodal point a high level, the 4th transistor T4 conducting, second electrical level end V2 is defeated by low level by the 4th transistor T4
Enter secondary nodal point b, secondary nodal point b low level.
Further, after the t3 stage before the Input of voltage hold circuit input high level again, pressure keeps node
PU1 remains low level.
Because pressure is kept node PU1 to be charged, therefore when pressure keeps node PU1 to be high level by voltage hold circuit
Voltage can be avoided to keep node PU1 to become low level, so the voltage hold circuit that above-described embodiment provides can solve joint
The problem that point voltage cannot keep.
Further, the transistor in the voltage hold circuit that above-described embodiment provides can also include N-type crystal simultaneously
Pipe and P-type transistor, now need to readjust the time sequence status of each input signal of voltage hold circuit, such as: by the
Three transistor T3 are set to P-type transistor, adjust control signal input Input at t1 stage input low level and at t2, t3
Stage input high level.Other transistors can certainly be set to P-type transistor, this is all that those skilled in the art depends on
The reasonable work-around solution can made according to embodiments of the invention, the most all should be protection scope of the present invention.But consider
The making technology of transistor, owing to the active layer dopant material of different types of transistor differs, therefore voltage hold circuit
The transistor of middle employing uniform type is more beneficial for the making technology of voltage hold circuit.
Yet another embodiment of the invention provides a kind of GOA unit, concrete, and with reference to shown in Fig. 5, GOA unit includes: signal is defeated
Enter to hold Input1, clock signal terminal CLK, gate drive signal outfan Output, pull-up node PU2, reset signal end Reset
And the voltage hold circuit that any of the above-described embodiment provides；
Wherein, pull-up node PU2 connects the voltage holding node PU1 of voltage hold circuit.
Exemplary, the driving process of GOA unit can be: the first stage, signal input part Input1 input high level,
The pull-up node PU2 of GOA unit is pulled to high level, voltage hold circuit holding voltage holding node PU1 and GOA unit
Pull-up node PU2 high level；Second stage, clock signal terminal CLK exports high level, and clock signal terminal CLK is exported by GOA unit
High level signal output part Output export；Phase III, reset signal end Reset input high level, voltage keeps joint
Point PU1, the pull-up node PU2 and signal output part Output of GOA unit are all pulled to low level.
In the embodiment of the present invention, the concrete structure to GOA unit does not limits, if the GOA unit of the most any form
The voltage hold circuit provided including any of the above-described embodiment, then within belonging to the protection domain of the embodiment of the present invention.
The embodiment of the present invention provides a kind of GOA circuit, concrete, and with reference to shown in Fig. 6, this GOA circuit includes multiple cascade
Above-described embodiment provide GOA unit.
Wherein, the signal input part of the 1st grade of GOA unit connects initial signal end, the reset signal end of the 1st grade of GOA unit
Connecting the signal output part of the 2nd grade of GOA unit, the signal that the signal output part of the 1st grade of GOA unit connects the 2nd grade of GOA unit is defeated
Enter end；
The signal input part of n-th grade of GOA unit connects the signal output part of (n-1)th grade of GOA unit, n-th grade of GOA unit
Reset signal end connects the signal output part of (n+1)th grade of GOA unit, and the signal output part of n-th grade of GOA unit connects (n+1)th grade
The signal input part of GOA unit；
Wherein, n is the positive integer more than 1.
Further, with reference to shown in Fig. 6, this GOA circuit includes several GOA unit cascaded, and wherein, the 1st grade of GOA is mono-
The signal input part of unit connects frame start signal end, and the signal output part of the 1st grade of GOA unit connects the signal of the 2nd grade of GOA unit
Input and grid line G1, the signal input part of the 2nd grade of GOA unit connects the signal output part of the 1st grade of GOA unit, the 2nd grade of GOA
The signal output part of unit connects the signal input part of 3rd level GOA unit, the reset signal end of the 1st grade of GOA unit and grid line
G2, other GOA unit of this GOA circuit connect according to the mode of the 2nd grade of GOA unit.
Each GOA unit has a first clock signal terminal CLK；With reference to shown in Fig. 6, believed by the clock of two systems
Number clock1 and clock2 provide clock signal to the clock signal terminal that each GOA unit connects, wherein the 1st grade of GOA unit
CLK inputs clock1, and the CLK1 of the 2nd grade of GOA unit inputs clock2, and the CLK of the 2nd grade of GOA unit inputs clock2, for the
N level GOA unit, when n is odd number, each clock signal terminal input of n-th grade of GOA unit and the clock letter of the 1st grade of GOA unit
Number end identical clock signal of input；When n is even number, clock signal terminal input and the 2nd grade of GOA unit of n-th grade of GOA unit
Each clock signal terminal identical clock signal of input；Fig. 6 illustrates as a example by n is as odd number.The sequential of system clock
State with reference to shown in Fig. 7, the opposite in phase of clock1 Yu clock2, clock1 Yu clock2 be dutycycle be 50% time
Clock signal.
Referring to time sequence status schematic diagram shown in Fig. 7, the operation principle of above-mentioned GOA circuit is illustrated.
In the display stage, the GOA unit at different levels forming GOA circuit input successively in the grid line that GOA unit at different levels connect
Gate drive signal.This phase actuation principle is similar with existing GOA drives principle, and the present invention no longer describes in detail.
When, after (n-1)th grade of GOA unit output, the display floater belonging to GOA circuit enters touch-control stage, this demands
GOA circuit suspends input gate drive signal in grid line.First, output signal n-th grade of GOA of input of (n-1)th grade of GOA unit
The signal input part Input1 of unit, the pull-up node PU2 of n-th grade of GOA unit are pulled to high level, due to clock1 with
Clock2 does not exports, so n-th grade of GOA unit does not exports.Now the voltage of n-th grade of GOA unit keeps
Voltage is kept the pull-up node PU2 of node PU1 and n-th grade of GOA unit to be charged by the first level terminal V1 by circuit, institute
High level, GOA circuit break-off is kept with the pull-up node PU2 of n-th grade of GOA unit.Owing to voltage hold circuit can make
The pull-up node PU2 of n-th grade of GOA unit keeps high level, it is possible to avoid this stage to terminate rear n-th grade of GOA unit pull-up
Node PU2 becomes low level, and then causes the problem that n-th grade of GOA unit cannot normally export.
After this touch-control stage terminates, clock1 Yu clock2 restarts to export clock signal, and n-th grade of GOA is mono-
The clock signal of unit output clock1, the grid that GOA circuit connects to GOA unit at different levels again by n-th grade of GOA unit successively
Line inputs gate drive signal.
Optionally, with reference to shown in Fig. 8, the control signal input Input of the voltage hold circuit of n-th grade of GOA unit is even
Connect (n-1)th grade of signal output part mono-for GOA.
Mono-by making the control signal input Input of the voltage hold circuit of n-th grade of GOA unit connect (n-1)th grade of GOA
Signal output part can omit make to control signal input Input provide scanning signal power circuit, Jin Erjian
Change the manufacturing process of display floater.
One embodiment of the invention provides a kind of display floater, including any one GOA circuit in above-described embodiment.
It addition, display floater can be: Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, number
Any product with display function or the parts such as code-phase frame, navigator.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art in the technical scope that the invention discloses, the change that can readily occur in or replacement, all answer
Contain within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with scope of the claims.
Claims (10)
1. a voltage hold circuit, it is characterised in that including: the first control unit, the second control unit and output unit；
Described first control unit connects the first level terminal, second electrical level end, primary nodal point and voltage and keeps node, is used for
Under the control of the voltage of described voltage holding node, the voltage of the voltage of described primary nodal point with described first level terminal is pulled together
Or the voltage of the voltage of described primary nodal point with described second electrical level end is pulled together；
Described second control unit connection control signal input, secondary nodal point, described first level terminal, described second electrical level end
And described primary nodal point, for the voltage in the control signal of described control signal input input and described primary nodal point
The voltage of the voltage of described secondary nodal point Yu described first level terminal is pulled together or by the voltage of described secondary nodal point under control
Pull together with the voltage of described second electrical level end；
Described output unit connects described first level terminal, described secondary nodal point and described voltage and keeps node, in institute
Node is kept to input the voltage of described first level terminal to described voltage under the control of the voltage stating secondary nodal point.
Circuit the most according to claim 1, it is characterised in that described first control unit includes: the first transistor and
Two-transistor；
First pole of described the first transistor connects described first level terminal, and the second pole of described the first transistor connects described the
One node, the grid of described the first transistor connects the first pole of described the first transistor；
First pole of described transistor seconds connects described primary nodal point, and the second pole of described transistor seconds connects described second
Level terminal, the grid of described transistor seconds connects described voltage and keeps node.
Circuit the most according to claim 1, it is characterised in that described second control unit includes: third transistor and
Four transistors；
First pole of described third transistor connects described first level terminal, and the second pole of described third transistor connects described the
Two nodes, the grid of described third transistor connects described control signal input；
First pole of described 4th transistor connects described secondary nodal point, and the second pole of described 4th transistor connects described second
Level terminal, the grid of described 4th transistor connects described primary nodal point.
Circuit the most according to claim 1, it is characterised in that described output unit includes: the 5th transistor；
First pole of described 5th transistor connects described first level terminal, and the second pole of described 5th transistor connects described
The pull-up node of GOA unit, the grid of described 5th transistor connects described secondary nodal point.
5. according to the circuit described in any one of claim 2-4, it is characterised in that each transistor is N-type transistor.
6. the driving method of a voltage hold circuit, it is characterised in that for driving the electricity described in any one of claim 1-5
Pressure holding circuit；Described method includes:
First stage, the first control unit keeps under the control of the voltage of node, the voltage of primary nodal point is electric with second at voltage
The voltage of flush end pulls together；Control signal that second control unit inputs at control signal input and the control of the voltage of primary nodal point
Under system, the voltage of secondary nodal point and the voltage of the first level terminal are pulled together；
Second stage, the first control unit keeps the voltage of primary nodal point under the control of the voltage of voltage holding node；Second
Secondary nodal point is kept under control signal that control unit inputs at control signal input and the control of the voltage of primary nodal point
Voltage；Output unit keeps node to fill by the first level portvoltage under the control of the voltage of described secondary nodal point
Electricity；
Phase III, the first control unit keeps under the control of the voltage of node, the voltage of primary nodal point is electric with first at voltage
The voltage of flush end pulls together；Control signal that second control unit inputs at control signal input and the control of the voltage of primary nodal point
Under system, the voltage of the voltage of secondary nodal point with second electrical level end is pulled together.
7. a GOA unit, it is characterised in that described GOA unit includes: signal input part, clock signal terminal, raster data model are believed
Number outfan, pull-up node, reset signal end and the voltage hold circuit described in any one of claim 1-5；
Wherein, the voltage of voltage hold circuit described in described pull-up Node connectedness keeps node.
8. a GOA circuit, it is characterised in that include the GOA unit described in the claim 7 of multiple cascade；
The signal input part of the 1st grade of GOA unit connects initial signal end, and the reset signal end of described 1st grade of GOA unit connects the
The signal output part of 2 grades of GOA unit, the signal output part of described 1st grade of GOA unit connects the signal input of the 2nd grade of GOA unit
End；
The signal input part of n-th grade of GOA unit connects the signal output part of (n-1)th grade of GOA unit, described n-th grade of GOA unit
Reset signal end connects the signal output part of (n+1)th grade of GOA unit, and the signal output part of described n-th grade of GOA unit connects n-th+
The signal input part of 1 grade of GOA unit；
Wherein, n is the positive integer more than 1.
GOA circuit the most according to claim 8, it is characterised in that the control of the voltage hold circuit of n-th grade of GOA unit
Signal input part connects the signal output part of (n-1)th grade of GOA unit.
10. a display floater, it is characterised in that include the GOA circuit described in claim 8 or 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610816585.3A CN106297710B (en) | 2016-09-12 | 2016-09-12 | Voltage hold circuit and driving method, GOA unit and circuit, display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610816585.3A CN106297710B (en) | 2016-09-12 | 2016-09-12 | Voltage hold circuit and driving method, GOA unit and circuit, display panel |
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| CN106297710B CN106297710B (en) | 2018-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10497456B2 (en) | 2017-12-29 | 2019-12-03 | Nuvoton Technology Corporation | Voltage holding circuit and electronic device using the same |
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| KR20160083587A (en) * | 2014-12-31 | 2016-07-12 | 엘지디스플레이 주식회사 | Gate driver and display device including the same |
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| CN1862650A (en) * | 2005-10-18 | 2006-11-15 | 友达光电股份有限公司 | Shift register circuit and method of improving stability and grid line driving circuit |
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| CN106297710B (en) | 2018-12-21 |
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