CN106297637A - A kind of circuit - Google Patents
A kind of circuit Download PDFInfo
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- CN106297637A CN106297637A CN201610838719.1A CN201610838719A CN106297637A CN 106297637 A CN106297637 A CN 106297637A CN 201610838719 A CN201610838719 A CN 201610838719A CN 106297637 A CN106297637 A CN 106297637A
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- circuit
- film transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention, about a kind of circuit, is used for producing ramp signal, and circuit includes bleeder circuit, N level gate driver circuit and output circuit.The two ends of bleeder circuit couple common level and high level and have the incremental primary nodal point of output voltage to nth node；N level gate driver circuit comprises the first grid drive circuit mutually concatenating and can opening step by step to N gate driver circuit；Output circuit includes that output film transistor and first is opened thin film transistor (TFT) and opened thin film transistor (TFT) to N, the grid opening thin film transistor (TFT) individually couples the gate output signal of correspondence, node is respectively coupled to one of them of the corresponding source electrode opening thin film transistor (TFT) or drain electrode, and another pole opening thin film transistor (TFT) couples the source electrode of output film transistor using as outfan；Wherein, during circuit work, N level gate driver circuit is opened step by step, in turn to be exported by the output voltage of primary nodal point to nth node to output circuit to export ramp signal.
Description
Technical field
The present invention relates to a kind of circuit, particularly relate to a kind of circuit producing ramp signal.
Background technology
In prior art, allow the both sides of display floater no longer by raster data model by the technology of GOA (gate on array)
Chip takes up room, thus reaches the effect of narrow frame.But directly drive circuit is made in substrate, drive circuit can be caused
Driving force not enough, under the output load condition of large size panel, especially severe especially.Owing to driving force is not enough, letter
Number rise time (Rising time) and fall time (Falling time) are slack-off so that panel also exists asking of reliability
Topic.Along with panel resolution and size constantly rise, the promotion ability of GOA will reach the limit of, and will solve basic problem
It is necessary for changing existing type of drive.
Existing a kind of type of drive is that the mode allowing grid impulse pass through buffer is transmitted, and makes signal from gate driver circuit
Can transmit one by one in scan line, such circuit design has two functions, isolated impedance and enhancing next stage
The function of signal.Two thin film transistor (TFT)s (TFT) it addition, can connect in pixel, the grid of two TFT is coupled with scan line
(scan line) and data wire (data line), make the analogue signal of original data line into pulse width modulation (pulse
Width modulation) go ramp signal (ramp signal) is done the selection of voltage, because data wire is digital drive
Signal, if combining buffer circuit, it is possible to improve asking of data wire and scanning-line signal distortion (distortion) respectively
Topic.But still there is the problem of distorted signals, and wayward slope in ramp signal.If additionally, ramp signal will be produced
Circuit uses TFT to be made on glass substrate, owing to the gain of TFT is not as CMOS tube, it is impossible to obtain suitable ramp waveform；Institute
Must design with us and produce new ramp signal circuit in viewing area, the problem overcoming ramp signal distortion.
Summary of the invention
For solving above-mentioned ramp signal distortion and the problem of wayward slope, the present invention provides a kind of circuit.
Above-mentioned circuit includes:
Bleeder circuit, the two ends of this bleeder circuit are respectively coupled to common level and high level, and this bleeder circuit has
One node is incremented by nth node, the output voltage of this primary nodal point to this nth node；
N level gate driver circuit, comprises the first grid drive circuit mutually concatenating and can opening step by step and drives to N grid
Galvanic electricity road, this first grid drive circuit to this N gate driver circuit is respectively provided with the first grid of correspondence and outputs signal to
N gate output signal, and
Output circuit, this output circuit includes that output film transistor and first is opened thin film transistor (TFT) and opened thin to N
Film transistor, the grid of this output film transistor couples output and enables signal, and this first unlatching thin film transistor (TFT) is opened to this N
Open the grid of thin film transistor (TFT) individually to couple this first grid of correspondence and output signal to this N gate output signal, should
Primary nodal point to this nth node is respectively coupled to this first unlatching thin film transistor (TFT) of correspondence and opens thin film transistor (TFT) to this N
Source electrode or one of them of drain electrode, this first is opened thin film transistor (TFT) and opens source electrode or the drain electrode of thin film transistor (TFT) to this N
Wherein another couples the source electrode of this output film transistor using as outfan, the drain electrode of this output film transistor couples this
Common level, or, this first open thin film transistor (TFT) to this N open the source electrode of thin film transistor (TFT) or drain electrode wherein another
Coupling the drain electrode of this output film transistor using as outfan, the source electrode of this output film transistor couples this common level；
Wherein, during the work of this circuit, this first grid drive circuit of this N level gate driver circuit drives to this N grid
Galvanic electricity road is opened step by step, and in turn to export the output voltage of this primary nodal point to this nth node to this output circuit, this is defeated
Go out end output ramp signal.
As optional technical scheme, this first grid drive circuit receives the first unlatching signal, this first unlatching signal
In order to open this N level gate driver circuit step by step from this first grid drive circuit.
As optional technical scheme, this N gate driver circuit receives the second unlatching signal, and this second unlatching signal is used
To open this N level gate driver circuit step by step from this N gate driver circuit.
As optional technical scheme, this bleeder circuit by the first dividing potential drop thin film transistor (TFT) to N dividing potential drop thin film transistor (TFT)
Another the two poles of the earth of non-grid be in series, this primary nodal point to this nth node is sequentially located at this first dividing potential drop thin film transistor (TFT) extremely
Between adjacent two the dividing potential drop thin film transistor (TFT) of this N dividing potential drop thin film transistor (TFT).
As optional technical scheme, the grid of this first dividing potential drop thin film transistor (TFT) to this N dividing potential drop thin film transistor (TFT) divides
Couple the most alone this primary nodal point of correspondence to this nth node.
As optional technical scheme, the grid of this first dividing potential drop thin film transistor (TFT) to this N dividing potential drop thin film transistor (TFT) divides
Couple the most alone first be biased into N bias, this first be biased into this N bias identical or incremental.
As optional technical scheme, this circuit also includes frequency generating circuit, and this frequency generating circuit produces the first frequency
Rate signal and the first anti-phase frequency signal, this first grid drive circuit to this N gate driver circuit receive respectively this
One frequency signal and this first anti-phase frequency signal.
As optional technical scheme, this circuit also includes buffer circuit, and this buffer circuit receives this first frequency signal
And this first anti-phase frequency signal and be used for eliminate this first frequency signal and the distortion of this first anti-phase frequency signal.
As optional technical scheme, this output enables signal at this first frequency signal and this first anti-phase frequency signal
Output high level when the most not exporting high level.
As optional technical scheme, this frequency generating circuit also produces second frequency signal and the second anti-phase frequency letter
Number, the odd level gate driver circuit in this first grid drive circuit to this N gate driver circuit receive respectively this first
Frequency signal and this first anti-phase frequency signal, and even level gate driver circuit receive respectively this second frequency signal and this
Two anti-phase frequency signals.
Compared to prior art, the circuit of the present invention utilizes gate driver circuit to open successively on bleeder circuit difference node
Voltage, obtain the signal of a similar ramp signal；Further, ramp signal can be adjusted by the bias on bleeder circuit
Slope；It addition, gate driver circuit also can be become four phase frameworks from biphase framework, and can get ramp signal more true to nature.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the first embodiment of circuit of the present invention；
Fig. 2 is the first waveform figure of the first embodiment of circuit of the present invention；
Fig. 3 is the schematic diagram of the second embodiment of bleeder circuit of the present invention；
Fig. 4 is the schematic diagram of the 3rd embodiment of bleeder circuit of the present invention；
Fig. 5 is the oscillogram of the coupling output enable signal of circuit of the present invention；
Fig. 6 is the schematic diagram of the second embodiment of circuit of the present invention；
Fig. 7 is the oscillogram of the second embodiment of circuit of the present invention.
Detailed description of the invention
Fig. 1 is the schematic diagram of the first embodiment of circuit of the present invention, refer to Fig. 1.For producing the electricity of ramp signal
Road 100 includes bleeder circuit 110, N level gate driver circuit 120 and output circuit 130.
The two ends of bleeder circuit 110 are respectively coupled to common level Vcom and high level VGH, for convenience of describing, and this embodiment party
Illustrating as a example by N is equal to 4 in formula, bleeder circuit 110 has primary nodal point V1, and to nth node VN, (in the present embodiment, VN is
V4), the output voltage of primary nodal point V1 to nth node VN is incremented by, and certainly, in other embodiments, N also can be not equal to 4, N
Value meet the requirement of ramp signal.N level gate driver circuit 120 comprises first mutually concatenating and can opening step by step
Gate driver circuit G1 to N gate driver circuit G4, first grid drive circuit G1 to N gate driver circuit GN (this reality
Executing in example, GN is G4) it is respectively provided with first grid output signal Gn1 of correspondence to N gate output signal Gn4.
Output circuit 130 includes that output film transistor Q and first opens thin film transistor (TFT) P1 to N and opens film crystal
Pipe PN (in the present embodiment, PN is P4), the grid of output film transistor Q couples output and enables signal OE, and first opens thin film
Transistor P1 to N opens the grid of thin film transistor (TFT) P4 and individually couples first grid output signal Gn1 of correspondence to N
Gate output signal Gn4, the most above-mentioned grid is electrically connected with correspondingly with gate output signal, primary nodal point V1 to N
Node V4 is respectively coupled to the first unlatching thin film transistor (TFT) P1 to N of correspondence and opens the source electrode of thin film transistor (TFT) P4 or drain electrode
One of them, first open thin film transistor (TFT) P1 to N open the source electrode of thin film transistor (TFT) P4 or drain electrode wherein another couples
The source electrode of output film transistor Q is using as outfan Ramp, and the drain electrode of output film transistor Q couples common level Vcom,
Or, first open thin film transistor (TFT) P1 to N open the source electrode of thin film transistor (TFT) P4 or drain electrode wherein another couples output
The drain electrode of thin film transistor (TFT) Q is using as outfan Ramp, and the source electrode of output film transistor Q couples common level Vcom.
Wherein, when circuit 100 works, the first grid drive circuit G1 of N level gate driver circuit 120 drives to N grid
Galvanic electricity road G4 opens step by step, in turn to export respective for primary nodal point V1 to nth node V4 output voltage to output circuit
130, outfan Ramp export ramp signal.
In the present embodiment, circuit 100 also includes frequency generating circuit (not shown), and frequency generating circuit produces first
Frequency signal CK1 and the first anti-phase frequency signal XCK1, first frequency signal CK1 and the first anti-phase frequency signal XCK1 are supplied to
Every one-level gate driver circuit of N level gate driver circuit 120, such as, first grid drive circuit G1 to N raster data model electricity
First frequency signal CK1 and the first anti-phase frequency signal XCK1 is all received on the G4 of road.First frequency signal CK1 and the first anti-phase frequency
Whether rate signal XCK1 in order to control the output of every one-level gate driver circuit of N level gate driver circuit 120.Circuit 100 is also
Including buffer circuit (not shown), buffer circuit receives first frequency signal CK1 and the first anti-phase frequency signal XCK1 and eliminates
First frequency signal CK1 and the distortion of the first anti-phase frequency signal XCK1, here, the position of buffer circuit does not limit,
Only need to meet and the distortion of anti-phase to first frequency signal CK1 and first frequency signal XCK1 is eliminated.
Fig. 2 is the first waveform figure of the first embodiment of circuit of the present invention, please with reference to Fig. 1, Fig. 2.In this enforcement
In mode, first grid drive circuit G1 receives the first unlatching signal ST1, and first opens signal ST1 in order to drive from first grid
Galvanic electricity road G1 opens N level gate driver circuit 120 step by step, and i.e. first opens signal ST1 opens N level raster data model in order to forward
Circuit 120.In other embodiments, N gate driver circuit G4 also can receive the second unlatching signal ST2, second opens
Signal ST2 is in order to open N level gate driver circuit 120 step by step from N gate driver circuit G4, and i.e. second opens signal ST2
In order to reversely to open N level gate driver circuit 120.With the oscillogram of forward unlatching N level gate driver circuit 120 it is in fig. 2
Example illustrates.N level gate driver circuit 120 receives first frequency signal CK1 and the first anti-phase frequency signal XCK1 and first
After opening signal ST1, open first grid drive circuit G1 to N gate driver circuit G4, i.e. first grid output letter successively
Number Gn1 to N gate output signal Gn4 enable successively, during first grid output signal Gn1 enable, the signal of outfan Ramp
Risen to the voltage of primary nodal point V1 by common level Vcom, then second grid output signal Gn2 is to N gate output signal
Gn4 enable successively, the signal of outfan Ramp is risen to the voltage of secondary nodal point V2 again, then rises by the voltage of primary nodal point V1
To the voltage of the 3rd node V3, finally rise to the voltage i.e. high level VGH of nth node V4, the most i.e. can get ideal
The ramp signal of rising.Certainly, if it is desired to obtain the ramp signal declined, only need to reversely open N level gate driver circuit
120.
In the present embodiment, bleeder circuit 110 is by the first dividing potential drop thin film transistor (TFT) W1 to N dividing potential drop thin film transistor (TFT) WN
Another the two poles of the earth of the non-grid of (in the present embodiment, WN is W4) are in series, certainly, in other modes, it is possible to use other
Circuit composition reaches the purpose of dividing potential drop, and such as, the resistance etc. of series connection, the building form of bleeder circuit 110 only need to meet dividing potential drop
Purpose.Primary nodal point V1 is sequentially located at the first dividing potential drop thin film transistor (TFT) W1 to N dividing potential drop film crystal to nth node V4
Between adjacent two the dividing potential drop thin film transistor (TFT) of pipe W4, so arrange and can meet primary nodal point V1 to the voltage of nth node V4
It is incremented by.And the grid of the first dividing potential drop thin film transistor (TFT) W1 to N dividing potential drop thin film transistor (TFT) W4 couples the most alone the of correspondence
One node V1 is to this nth node V4.
Certainly, in other embodiments, the second embodiment of bleeder circuit of the present invention as shown in Figure 3, dividing potential drop electricity
It is inclined that the grid of first dividing potential drop thin film transistor (TFT) W1 to the N dividing potential drop thin film transistor (TFT) W4 on road 210 also can couple the most alone first
Pressure Vbias1 to N bias VbiasN (in the present embodiment, VbiasN is Vbias4), the first bias Vbias1 to N bias
Vbias4 is incremented by, and so, the first bias Vbias1 to N bias Vbias4 can be independently adjustable the ramp signal of last output
The slope of the most corresponding section.Certainly, the 3rd embodiment of bleeder circuit of the present invention as shown in Figure 4, the of bleeder circuit 310
The grid of one dividing potential drop thin film transistor (TFT) W1 to N dividing potential drop thin film transistor (TFT) W4 couples same bias Vbias, is i.e. equivalent to dividing potential drop electricity
The bias value of the first bias Vbias1 to N bias Vbias4 in road 210 is equal, and so, each bias is the most corresponding
The slope of ramp signal identical.
Fig. 5 is the oscillogram of the coupling output enable signal of circuit of the present invention, refer to Fig. 5.In some cases, first
Time period T1～T4 can be had, in time period T1, T2, T3 and T4 between frequency signal CK1 and the first anti-phase frequency signal XCK1
Time, first frequency signal CK1 and the first anti-phase frequency signal XCK1 does not the most export high level, and owing to output enables letter
Number OE exports high level, i.e. output at time period T1～T4 and enables signal OE in first frequency signal CK1 and the first anti-phase frequency
Output high level when signal XCK1 does not the most export high level, so, at time period T1-T4, output enables signal OE can be with output
The signal of end Ramp couples, and thus can not obtain preferably ramp signal.
For effectively improving above-mentioned coupling phenomenon, the present invention provides the second enforcement of circuit of the present invention as shown in Figure 6
Mode, refer to Fig. 6.Circuit 200 includes bleeder circuit 210, N level gate driver circuit 220 and output circuit 230.Circuit 200
Being with the difference of circuit 100, the control signal of the reception of N level gate driver circuit 220 is different.The first of circuit 100
All receive on gate driver circuit G1 to N gate driver circuit GN (in the present embodiment, GN is G4) first frequency signal CK1 and
First anti-phase frequency signal XCK1, and strange in the first grid drive circuit G1 of circuit 200 to this N gate driver circuit G4
Several levels gate driver circuit (such as first grid drive circuit G1, the 3rd gate driver circuit G3) receives first frequency letter respectively
Number CK1 and the first anti-phase frequency signal XCK1, and even level gate driver circuit (such as second grid drive circuit G2, N grid
Pole drive circuit G4) respectively receive second frequency signal CK2 and the second anti-phase frequency signal XCK2, second frequency signal CK2 and
Second anti-phase frequency signal XCK2 is produced by frequency generating circuit (not shown), and because N level gate driver circuit 220 is divided into
Odd level gate driver circuit and even level gate driver circuit, so the unlatching signal each received changes the most therewith, odd number
The first and last two-stage gate driver circuit of level gate driver circuit meets the first unlatching signal ST1 and second respectively and opens signal ST2, and
The first and last two-stage gate driver circuit of even level gate driver circuit meets the 3rd unlatching signal ST1 ' respectively and opens signal with the 4th
ST2’。
Refer again to the oscillogram of the second embodiment that Fig. 7, Fig. 7 are circuit of the present invention.First frequency signal CK1 and first
Still there is between anti-phase frequency signal XCK1 both of which and do not export the time period of high level, but due to second frequency signal CK2
And second anti-phase frequency signal XCK2 output high level in the above-mentioned time period, so, output enables signal OE can't be
The above-mentioned time period couples with the signal of outfan Ramp, and so, circuit 200 (can be received by biphase framework by this
First frequency signal CK1 and the first anti-phase frequency signal XCK1) become four phase frameworks (be further added by receive second frequency signal CK2
And the second anti-phase frequency signal XCK2) mode, thus preferable ramp signal can be obtained at outfan Ramp.
Above-mentioned circuit 100 or circuit 200 can directly be made in panel, in order to provide ramp signal, because circuit
100 or circuit 200 can make of undersized thin film transistor (TFT), and the not same district that available in parallel mode is made in panel
Territory, so can be used on large-sized panel, without the problem having distorted signals.
In sum, the circuit of the present invention utilizes gate driver circuit to open the electricity on bleeder circuit difference node successively
Pressure, obtains the signal of a similar ramp signal；Further, the oblique of ramp signal can be adjusted by the bias on bleeder circuit
Rate；It addition, gate driver circuit also can be become four phase frameworks from biphase framework, and can get ramp signal more true to nature.
Certainly, the present invention also can have other various embodiments, in the case of without departing substantially from present invention spirit and essence thereof, ripe
Know those skilled in the art and can make various corresponding change and deformation according to the present invention, but these change and deformation accordingly
All should belong to the protection domain of appended claims of the invention.
Claims (10)
1. a circuit, is used for producing ramp signal, it is characterised in that this circuit includes:
Bleeder circuit, the two ends of this bleeder circuit are respectively coupled to common level and high level, and this bleeder circuit has first segment
Point is incremented by nth node, the output voltage of this primary nodal point to this nth node；
N level gate driver circuit, comprises the first grid drive circuit mutually concatenating and can opening step by step to N raster data model electricity
Road, this first grid drive circuit to this N gate driver circuit is respectively provided with the first grid of correspondence and outputs signal to N grid
Pole output signal；And
Output circuit, this output circuit includes that output film transistor and first is opened thin film transistor (TFT) and opened thin film crystalline substance to N
Body pipe, the grid of this output film transistor couples output and enables signal, and this first unlatching thin film transistor (TFT) is opened thin to this N
The grid of film transistor individually couples this first grid of correspondence and outputs signal to this N gate output signal, and this is first years old
Node to this nth node is respectively coupled to this first unlatching thin film transistor (TFT) source to this N unlatching thin film transistor (TFT) of correspondence
One of them of pole or drain electrode, this first is opened thin film transistor (TFT) and opens its of the source electrode of thin film transistor (TFT) or drain electrode to this N
In another couples the source electrode of this output film transistor using as outfan, it is common that the drain electrode of this output film transistor couples this
Level, or, this first open thin film transistor (TFT) to this N open the source electrode of thin film transistor (TFT) or drain electrode wherein another couples
The drain electrode of this output film transistor is using as outfan, and the source electrode of this output film transistor couples this common level；
Wherein, during the work of this circuit, this first grid drive circuit of this N level gate driver circuit is to this N raster data model electricity
Road is opened step by step, so that the output voltage of this primary nodal point to this nth node is in turn exported to this output circuit, and this outfan
Output ramp signal.
2. circuit as claimed in claim 1, it is characterised in that this first grid drive circuit receives the first unlatching signal, should
First opens signal in order to open this N level gate driver circuit step by step from this first grid drive circuit.
3. circuit as claimed in claim 1, it is characterised in that this N gate driver circuit receives the second unlatching signal, this is the years old
Two open signal in order to open this N level gate driver circuit step by step from this N gate driver circuit.
4. circuit as claimed in claim 1, it is characterised in that this bleeder circuit is divided to N by the first dividing potential drop thin film transistor (TFT)
Another the two poles of the earth of the non-grid of ironed film transistor are in series, and this primary nodal point to this nth node is sequentially located at this first dividing potential drop
Thin film transistor (TFT) is between adjacent two the dividing potential drop thin film transistor (TFT) of this N dividing potential drop thin film transistor (TFT).
5. circuit as claimed in claim 4, it is characterised in that this first dividing potential drop thin film transistor (TFT) is brilliant to this N dividing potential drop thin film
The grid of body pipe couples the most alone this primary nodal point of correspondence to this nth node.
6. circuit as claimed in claim 4, it is characterised in that this first dividing potential drop thin film transistor (TFT) is brilliant to this N dividing potential drop thin film
The grid of body pipe couple the most alone first be biased into N bias, this first be biased into this N bias identical or incremental.
7. circuit as claimed in claim 1, it is characterised in that this circuit also includes frequency generating circuit, and this frequency produces electricity
Road produces first frequency signal and the first anti-phase frequency signal, and this first grid drive circuit is equal to this N gate driver circuit
Receive this first frequency signal and this first anti-phase frequency signal respectively.
8. circuit as claimed in claim 7, it is characterised in that this circuit also includes buffer circuit, this buffer circuit receives should
First frequency signal and this first anti-phase frequency signal also are used for eliminating this first frequency signal and this first anti-phase frequency signal
Distortion.
9. circuit as claimed in claim 7, it is characterised in that this output enable signal this first frequency signal and this first
Output high level when anti-phase frequency signal does not the most export high level.
10. circuit as claimed in claim 9, it is characterised in that this frequency generating circuit also produces second frequency signal and the
Two anti-phase frequency signals, the odd level gate driver circuit in this first grid drive circuit to this N gate driver circuit divides
Do not receive this first frequency signal and this first anti-phase frequency signal, and even level gate driver circuit receives this second frequency respectively
Rate signal and this second anti-phase frequency signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610838719.1A CN106297637A (en) | 2016-09-21 | 2016-09-21 | A kind of circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610838719.1A CN106297637A (en) | 2016-09-21 | 2016-09-21 | A kind of circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106297637A true CN106297637A (en) | 2017-01-04 |
Family
ID=57712953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610838719.1A Pending CN106297637A (en) | 2016-09-21 | 2016-09-21 | A kind of circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN106297637A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022193708A1 (en) * | 2021-03-15 | 2022-09-22 | 京东方科技集团股份有限公司 | Display panel, detection method therefor, and compensation method therefor, and display device |
-
2016
- 2016-09-21 CN CN201610838719.1A patent/CN106297637A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022193708A1 (en) * | 2021-03-15 | 2022-09-22 | 京东方科技集团股份有限公司 | Display panel, detection method therefor, and compensation method therefor, and display device |
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Application publication date: 20170104 |