WO2022193708A1

WO2022193708A1 - Display panel, detection method therefor, and compensation method therefor, and display device

Info

Publication number: WO2022193708A1
Application number: PCT/CN2021/131702
Authority: WO
Inventors: 李威; 黄建邦; 吴章敏; 何林昌
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2021-03-15
Filing date: 2021-11-19
Publication date: 2022-09-22
Also published as: CN113053275A; CN113053275B; US20240046829A1

Abstract

A display panel, a detection method therefor, and a compensation method therefor, and a display device. The display panel comprises a first voltage end (V1), a gate drive circuit (7), and a detection circuit (8). The gate drive circuit (7) comprises multiple stages of first output ends (Vout11, Vout12, Vout13, Vout14, ..., and Vout1n); and the detection circuit (8) comprises a voltage division circuit (81), a plurality of first switch units, and a plurality of second switch units. The voltage division circuit (81) comprises multiple stages of voltage output ends (N1, N2, N3, N4, ..., and Nn), and the voltage output ends (N1, N2, N3, N4, ..., and Nn) and the first output ends (Vout11, Vout12, Vout13, Vout14, ..., and Vout1n) are arranged in a one-to-one correspondence mode; the first switch units and the voltage output ends (N1, N2, N3, N4, ..., and Nn) are arranged in a one-to-one correspondence mode; the first switch units have control ends connected to the voltage output ends (N1, N2, N3, N4, ..., and Nn) corresponding thereto, and first ends connected to a first power supply end (VDD); the second switch units and the first switch units are arranged in a one-to-one correspondence mode; and the second switch units have control ends connected to the first output ends (Vout11, Vout12, Vout13, Vout14, ..., and Vout1n) corresponding thereto, first ends connected to second ends of the first switch units corresponding thereto, and second ends connected to a second output end (Vout2). The display panel can simultaneously detect whether the voltage of the first voltage end (V1) and the gate drive circuit (7) are normal or not.

Description

Display panel and its detection method, compensation method, and display device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Chinese Patent Application No. 202110277532.X filed on March 15, 2021 and entitled "Display Panel and Its Detection Method, Compensation Method, Display Device", and the above Chinese patent application is hereby cited in its entirety. The disclosure is made a part of this application.

technical field

The present disclosure relates to the field of display technology, and in particular, to a display panel, a detection method, a compensation method, and a display device thereof.

Background technique

In the related art, the light emitting unit in the display panel usually needs to be driven by a low-level terminal and a high-level terminal. The low-level terminal and the high-level terminal are easily affected by various factors and cause abnormal voltage values, so that the display panel cannot work normally.

It should be noted that the information disclosed in the above Background section is only for enhancement of understanding of the background of the present disclosure, and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

public content

According to one aspect of the present disclosure, a display panel is provided, the display panel includes: a first voltage terminal, a gate driving circuit, and a detection circuit, the gate driving circuit includes a multi-stage first output terminal, and the multi-stage The first output terminal outputs shift signals at intervals in sequence. The detection circuit includes: a voltage divider circuit, a plurality of first switch units, and a plurality of second switch units. The voltage divider circuit is connected between the first voltage terminal and the reference voltage terminal, and the voltage divider circuit includes a multi-stage voltage output terminal, the voltage output terminal is set in a one-to-one correspondence with the first output terminal; a plurality of first switch units are set in a one-to-one correspondence with the multi-stage voltage output terminal, and the control terminal of the first switch unit is connected to its corresponding The voltage output terminal of the first switch unit is connected to the first power supply terminal; a plurality of second switch units are arranged in a one-to-one correspondence with a plurality of the first switch units, and the second switch units are in a one-to-one correspondence. The control terminal is connected to the corresponding first output terminal, the first terminal is connected to the corresponding second terminal of the first switch unit, and the second terminal is connected to the second output terminal. Wherein, the first switch unit may turn on the first end and the second end in response to the signal of the control end, and the second switch unit may turn on the first end and the second end in response to the signal of the control end.

In an exemplary embodiment of the present disclosure, the display panel further includes: a driver chip, a third switch unit, and a fourth switch unit, and the driver chip is connected to the first power supply terminal, a second voltage terminal, and a start signal terminal , for respectively providing corresponding signals to the first power supply terminal, the second voltage terminal and the start signal terminal; wherein, the gate driving circuit is connected to the start signal terminal, and in one frame driving period , the gate drive circuit is configured to start outputting the shift signal to the first output terminal in response to an effective level signal at the start signal terminal, and the effective level signal at the start signal terminal is earlier in time sequence for all of the shift signals. The control terminal of the third switch unit is connected to the second power terminal, and the first terminal is connected to the first power terminal; the control terminal of the fourth switch unit is connected to the start signal terminal, and the first terminal is connected to the third switch The second end of the unit is connected to the second output end. Wherein, the third switch unit may turn on the first end and the second end in response to the signal of the control end, and the fourth switch unit may turn on the first end and the second end in response to the signal of the control end.

In an exemplary embodiment of the present disclosure, the voltage divider circuit includes a plurality of resistors, and the plurality of resistors are connected in series between the first voltage terminal and the reference voltage terminal; the voltage output of the voltage divider circuit The terminals are connected between the adjacent resistors.

In an exemplary embodiment of the present disclosure, one resistor is connected between the voltage output terminals of two adjacent stages, and the resistance values of a plurality of the resistors are the same.

In an exemplary embodiment of the present disclosure, the first switch unit includes a first transistor, a gate of the first transistor is connected to the corresponding voltage output terminal, and a first stage of the first transistor is connected to the first power supply end. The second switch unit includes: a second transistor, the gate of the second transistor is connected to the corresponding first output terminal, the first stage of the second transistor is connected to the second pole of the first transistor corresponding to the second transistor, The second pole of the second transistor is connected to the second output terminal.

In an exemplary embodiment of the present disclosure, the third switch unit includes a third transistor, a gate of the third transistor is connected to the second power supply terminal, and a first electrode of the third transistor is connected to the first power supply terminal. The fourth switch unit includes: a fourth transistor, the gate of the fourth transistor is connected to the start signal terminal, the first pole of the fourth transistor is connected to the second pole of the third transistor, and the second pole of the fourth transistor is connected the second output.

In an exemplary embodiment of the present disclosure, the first transistor is an N-type transistor or a P-type transistor, the second transistor is an N-type transistor or a P-type transistor, and the third transistor is an N-type transistor or a P-type transistor transistor, the fourth transistor is an N-type transistor or a P-type transistor.

In an exemplary embodiment of the present disclosure, the display panel further includes: a display screen, the display screen includes a plurality of light-emitting units, the first voltage terminal is located on the display screen, and is connected to the light-emitting unit. cathode.

In an exemplary embodiment of the present disclosure, the display panel further includes a display screen, the display screen includes a plurality of pixel driving circuits, the pixel driving circuits include driving transistors, and the first voltage terminal is located on the display screen is connected to the first pole of the driving transistor, and the driving transistor is used for outputting a driving current to the second pole of the driving transistor according to the gate voltage thereof.

In an exemplary embodiment of the present disclosure, the display panel further includes a plurality of pixel driving circuits;

The gate driving circuit is used for providing a gate driving signal to the pixel driving circuit.

In an exemplary embodiment of the present disclosure, the multi-stage voltage output terminals include n-stage power supply output terminals, wherein the voltage of the m-th stage voltage output terminal is smaller than the voltage of the m+1-th stage voltage output terminal; the m-th stage first output The terminals are set correspondingly to the m-th stage voltage output terminals, wherein the first output terminal outputs the shift signal at intervals according to the increasing order of the number of stages, or the first output terminal outputs the shift signals at intervals according to the decreasing order of the number of stages. the shift signal.

In an exemplary embodiment of the present disclosure, the gate driving circuit includes a plurality of cascaded shift register units, and at least part of the output ends of the shift register units are used to form the first output end.

In an exemplary embodiment of the present disclosure, the multi-stage shift register units sequentially output shift signals according to the increasing order of their stages; the multi-stage first output terminals sequentially output shift signals according to their stages increasing order; The output terminal of the M+(X-1) Nth stage shift register unit is used to form the Xth stage first output terminal, wherein M, N, X are positive integers greater than or equal to 1, and N is not equal to M.

In an exemplary embodiment of the present disclosure, the display screen includes a non-display area, and the detection circuit is integrated in the non-display area of the display screen.

In an exemplary embodiment of the present disclosure, the detection circuit further includes: an RC filter circuit, where the RC filter circuit is connected to the second output terminal.

According to one aspect of the present disclosure, there is provided a display panel detection method for detecting the above-mentioned display panel, including:

Obtaining the number of pulse signals output by the second output terminal in one frame of driving period;

Determine whether the voltage of the first voltage terminal in the display panel and the gate driving circuit are normal according to the number of pulse signals output by the second output terminal in one frame driving period;

Wherein, when the number of pulse signals output by the second output terminal in one frame driving period is equal to a preset value, the voltage of the first voltage terminal and the gate driving circuit are normal;

Otherwise, the voltage of the first voltage terminal or the gate driving circuit is abnormal.

According to an aspect of the present disclosure, there is provided a display panel compensation method for compensating the above-mentioned display panel, including:

The voltage of the first voltage terminal is compensated according to the number of pulse signals output by the second output terminal in one frame driving period.

According to an aspect of the present disclosure, there is provided a display device, wherein the display device includes: the above-mentioned display panel and a processor, wherein the processor is connected to the second output end of the display panel, and is used for recording a driving period of one frame , the second output terminal outputs the number of pulse signals.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a display panel in the related art;

2 is a structural diagram of a pixel driving circuit in the related art;

FIG. 3 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure;

Fig. 4 is the sequence diagram of each node in Fig. 3;

Fig. 5 is another timing diagram of a plurality of first output terminals in Fig. 3;

Fig. 6 is another timing diagram of a plurality of first output terminals in Fig. 3;

FIG. 7 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure;

FIG. 8 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure;

FIG. 9 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure;

Fig. 10 is a kind of sequence diagram of each node in Fig. 9;

11 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure;

FIG. 12 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure;

FIG. 13 is a schematic structural diagram of an exemplary embodiment of a display device of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, such as according to the direction of the example described. It will be appreciated that if the device of the icon is turned upside down, the components described as "on" will become the components on "bottom". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a certain structure is "on" other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is "directly" arranged on other structures, or that a certain structure is "indirectly" arranged on another structure through another structure. other structures.

The terms "a", "an", "the" are used to indicate the presence of one or more elements/components/etc; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and refer to Additional elements/components/etc may be present in addition to the listed elements/components/etc.

As shown in FIG. 1 , it is a schematic structural diagram of a display panel in the related art. The display panel may include a display screen 01, a flexible circuit board 02, a driver chip 04 (Driver IC), and a power management chip 03 (Power IC). The flexible circuit board 02 can be connected to the display screen 01 by binding a PIN corner, and connected to the power management chip 03 through a connector. As shown in FIG. 2 , it is a structural diagram of a pixel driving circuit in the related art. In the related art, the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first pole of the second transistor T2 is connected to the second pole of the driving transistor T3, and the second pole The gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N, and the first electrode is connected to the first power supply signal terminal VDD; the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, and the first The diode is connected to the first pole of the driving transistor T3, the gate is connected to the gate driving signal terminal Gate; the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the first pole of the driving transistor T3, and the gate The pole is connected to the enable signal terminal EM; the first pole of the sixth transistor T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, and the second pole The second pole of the sixth transistor T6 is connected. The capacitor C is connected between the gate of the driving transistor T3 and the first power signal terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, the anode of the light-emitting unit OLED can be connected to the second pole of the sixth transistor T6, and the cathode of the light-emitting unit can be connected to the second power signal terminal VSS. Wherein, the transistors T1-T7 may all be P-type transistors. The power management chip 03 can provide a high-level signal to the first power supply signal terminal VDD in the pixel driving circuit, and a low-level signal to the second power supply signal terminal VSS. Usually the voltage of the high-level signal can be +4.6V, and the voltage of the low-level signal can be -2.4V. The high-level signals and low-level signals output by the power management chip 03 usually need to be finally transmitted to the pixel driving circuit and the light-emitting unit located in the display screen 01 through connecting devices such as connectors, flexible circuit boards 02, and binding PIN corners. If any of the above-mentioned connection devices are faulty, the high-level signal and the low-level signal transmitted to the position of the display screen will be abnormal in voltage, which will cause the display panel to fail to work properly.

Based on this, the present exemplary embodiment provides a display panel. As shown in FIGS. 3 and 4 , FIG. 3 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure, and FIG. 4 is a timing diagram of each node in FIG. 3 . . Wherein, Vout11 is the timing diagram of the first output terminal Vout11 in FIG. 3 , Vout12 is the timing diagram of the first output terminal Vout12 in FIG. 3 , Vout13 is the timing diagram of the first output terminal Vout13 in FIG. 3 , and Vout14 is the timing diagram of the first output terminal Vout13 in FIG. 3 . A timing diagram of the output terminal Vout14, Vout1n is the timing diagram of the first output terminal Vout1n in FIG. 3, and Vout2 is the timing diagram of the second output terminal Vout2. The display panel may include: a first voltage terminal V1, a gate driving circuit 7, and a detection circuit 8. The gate driving circuit 7 may include n-stage first output terminals Vout11, Vout12, Vout13, Vout14... Vout1n. As shown in FIG. 4 , the multi-stage first output terminals Vout11 , Vout12 , Vout13 , Vout14 . . . Vout1n can output shift signals at intervals in sequence. The detection circuit 8 may include: a voltage divider circuit 81, n first transistors T11, T12, T13, T14...T1n, and n second transistors T21, T22, T23, T24...T2n. The voltage dividing circuit 81 may be connected between the first voltage terminal V1 and the reference voltage terminal Vref. The voltage dividing circuit 81 may include n-stage voltage output terminals N1, N2, N3, N4...Nn, and the voltage output terminals N1, N2, N3, N4...Nn may be connected with the first output terminals Vout11, Vout12 , Vout13, Vout14… Corresponding settings; a plurality of first transistors T11, T12, T13, T14...T1n can be set in one-to-one correspondence with the multi-stage voltage output terminals N1, N2, N3, N4...Nn, for example, the first transistor T11 and the voltage The output terminal N1 is set correspondingly, the first transistor T12 is set correspondingly with the voltage output terminal N2, and the first transistor T1n is set correspondingly with the voltage output terminal Nn. The gate of the first transistor can be connected to the corresponding voltage output terminal, and the first electrode of each first transistor is connected to the first power supply terminal VDD; a plurality of second transistors and a plurality of the first transistors One-to-one correspondence, for example, the second transistor T21 is arranged corresponding to the first transistor T11, the second transistor T22 is arranged corresponding to the first transistor T12, and the second transistor T2n is arranged corresponding to the first transistor T1n. The first transistor corresponding to the same voltage output terminal and the first output terminal are set correspondingly, and the second transistor corresponding to the first transistor and the first output terminal are set correspondingly, for example, the second transistor T21 and the first output terminal are set correspondingly. Vout11 is set correspondingly, the second transistor T22 is set corresponding to the first output terminal Vout12, the second transistor T2n is set corresponding to the first output terminal Vout1n, and the gate of the second transistor can be connected to the corresponding first output terminal, The first electrode is connected to the corresponding second electrode of the first transistor, and the second electrode is connected to the second output terminal Vout2. Wherein, n can be a positive integer greater than 1.

In this exemplary embodiment, as shown in FIG. 3 , the first transistor and the second transistor may be P-type transistors. The first power supply terminal VDD may be at a high level, and the voltage of the first power supply terminal VDD may generally be 1.8V or 3.3V. The voltage of the first voltage terminal V1 may be a low-level voltage, the voltage of the reference voltage terminal Vref may be greater than the voltage of the first voltage terminal V1, and the voltage difference between the reference voltage terminal Vref and the first power supply terminal VDD is greater than the threshold of the first transistor Voltage. Under the action of the voltage divider circuit 81, the voltages of the multi-stage voltage output terminals N1, N2, N3, N4, . . . For example, the voltage of the voltage output terminal N2 is greater than the voltage of the voltage output terminal N1. When the voltage difference between the voltage output terminal and the first power terminal VDD is smaller than the threshold voltage of the first transistor, the first transistor is turned on. For example, when the voltage difference between the voltage output terminal N1 and the first power terminal VDD is smaller than the threshold voltage of the first transistor T11, the first transistor T11 is turned on, the first power terminal VDD charges the first pole of the second transistor T21, and the second transistor T21 is charged. The transistor T21 can be turned on under the action of the shift signal of the first output terminal Vout11. The effective low level of the shift signal may be -7V, the inactive level of the first output terminal may be +7V, the second transistor is only turned on under the action of the effective low level of the shift signal, and the It is turned off under the action of invalid level. Thus, a high-level pulse signal is formed at the second output terminal Vout2. When the voltage of the voltage output terminal increases to a certain value, the voltage difference between the voltage output terminal and the first power terminal VDD is greater than the threshold voltage of the first transistor, for example, the voltage output terminal Nm-1 of the m-1 stage and the first power terminal The voltage difference of VDD is less than the threshold voltage of the first transistor T1 (m-1), and the voltage difference between the m-th level voltage output terminal Nm and the first power supply terminal VDD is greater than the threshold voltage of the first transistor T1m, then the m-th level voltage The first transistor Tm corresponding to the output terminal Nm will not be able to be turned on, so in one driving cycle of the gate driving circuit (that is, the time period during which each first output terminal in the gate driving circuit outputs a valid level in sequence), The second output terminal can output m-1 high-level pulses. The display panel can judge whether the voltage of the first voltage terminal V1 is abnormal through the number of high-level pulses of the second output terminal Vout2 in one driving cycle of the gate driving circuit. For example, the display panel can set the number of high-level pulses output by the second output terminal Vout2 to 8 under the normal range of the first voltage terminal V1, and when the number of high-level pulses output by the second output terminal Vout2 is greater than 8 , it means that the voltage of the first voltage terminal V1 is too small, and when the number of high-level pulses output by the second output terminal Vout2 is less than 8, it means that the voltage of the first voltage terminal V1 is too large.

It should be noted that due to process errors, the threshold voltages of the first transistors and the resistance values of the resistors in different display panels cannot be completely consistent. Therefore, when the display panels leave the factory, the voltage of the reference voltage terminal Vref can be adjusted to make each display panel When the panel outputs the first voltage terminal V1 normally, the number of pulses at the second output terminal Vout2 is the same.

In this exemplary embodiment, as shown in FIGS. 3 and 4 , the multi-level voltage output terminals may include n-level power supply output terminals, wherein the voltage of the m-th voltage output terminal is lower than the voltage of the m+1-th voltage output terminal, For example, the voltage of the second-stage voltage output terminal N2 is lower than the voltage of the third-stage voltage output terminal N3. The first output terminal of the mth stage is set corresponding to the voltage output terminal of the mth stage. For example, the first output terminal Vout3 of the third stage is set corresponding to the voltage output terminal N3 of the third stage. Wherein, as shown in FIG. 4 , the first output terminal may output the shift signals at intervals according to the order of increasing the number of stages.

It should be understood that, in other exemplary embodiments, the multi-stage first output terminals may also have other timing forms. For example, as shown in FIG. 5 , it is another timing diagram of the plurality of first output terminals in FIG. 3 . The multi-stage first output terminals may also output the shift signals at intervals according to the decreasing order of the stages. For another example, as shown in FIG. 6 , which is another timing diagram of the plurality of first output terminals in FIG. 3 , the multi-stage first output terminals may also output the shift signals at intervals in any order. As long as the gate driving circuit is in a driving cycle, each first output terminal only outputs a shift signal once, the display panel can judge whether the first power terminal is normal by measuring the number of pulse signals of the second output terminal. .

As shown in FIG. 3 , both the first transistor and the second transistor may be P-type transistors. It should be understood that, in other exemplary embodiments, the first transistor may be an N-type transistor, and the second transistor may also be an N-type transistor. transistor. In addition, the first transistor and the second transistor may also be switch units of other structures. As shown in FIG. 3 , in this exemplary embodiment, the voltage dividing circuit 81 may include n resistors R1 , R2 , R3 , R4 . . . Rn, and a plurality of the resistors are connected in series with the first voltage terminals V1 and Between the reference voltage terminals Vref; the voltage output terminals N1 , N2 , N3 . . . Nn of the voltage dividing circuit 81 can be connected between the adjacent resistors. In addition, as shown in FIG. 3 , one voltage output terminal of the voltage dividing circuit 81 may also be connected to the reference voltage terminal Vref. Wherein, one of the resistors may be connected between the voltage output terminals of two adjacent stages, and the resistance values of a plurality of the resistors may be the same. The resistance can be designed to be a resistance of more than 100 ohms by adjusting the line width and line length, so as to be separated from the normal wiring resistance by a certain number of stages, so as to avoid the normal wiring causing the voltage division characteristics of the voltage divider circuit to be relatively large. Impact.

It can be seen from the above analysis that when the second output terminal Vout2 has x pulses:

VNx-VDD≤Vth<VNx+1-VDD, wherein, VNx is the voltage of the X-level voltage output terminal Nx, VNx+1 is the voltage of the first X+1-level voltage output terminal Nx+1, and VDD is the first power supply voltage of terminal VDD.

VNx-VDD≤Vth<VNx+1-VDD can be written as:

VDD+Vth=[VNx+(VNx+1-VNx)/2]±(VNx+1-VNx)/2;

The control accuracy of the detection circuit can be defined as (VNx+1-VNx)/2;

And because the voltage of the voltage output terminal Nx is (Vref-V1)/(R total)*Rx total +V1, where Vref is the voltage of the reference voltage terminal, V1 is the voltage of the first voltage terminal, R total = R1+R2+...+ Rn, Rx total=R1+R2...Rx, so the control precision of the detection circuit is (Vref-V1)/2n, and the precision of the detection circuit can be controlled by controlling the number of resistors.

In this exemplary embodiment, as shown in FIG. 7 , it is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure. The display panel may further include: a display screen 1, the display screen 1 may include a plurality of light-emitting units, and the first voltage terminal V1 may be located on the display screen and connected to the cathodes of the light-emitting units. That is, the display panel can detect the voltage of the cathode of the light-emitting unit on the display screen through the detection circuit. The first voltage terminal V1 may be located at any position on the display screen, for example, the first voltage terminal V1 may be located at the centroid of the display screen, and for example, the first voltage terminal may be located at the edge of the display screen. In addition, as shown in FIG. 7 , the display panel may further include a flexible circuit board 2 and a power management chip 3 . The flexible circuit board 2 can be connected to the display screen 1 by binding a PIN corner, and connected to the power management chip 3 by a connector. The power management chip 3 can provide power to the first voltage terminal V1 located on the display screen through connecting devices such as a connector, a flexible circuit board 02, and a binding PIN corner.

In this exemplary embodiment, as shown in FIG. 7 , the display screen 1 may include a display area 11 and a non-display area 12 . The display screen may also include a plurality of pixel driving circuits 6 located in the display area. The above-mentioned gate driving circuit 7 can be integrated in the non-display area 12 of the display screen. The gate driving circuit 7 can be used to provide gate driving signals to the pixel driving circuit 6 . For example, the structure of the pixel driving circuit 6 may be as shown in FIG. 2 , and the gate driving signal provided by the gate driving circuit 7 may include one of the signal of the gate driving signal terminal, the signal of the reset signal terminal, the signal of the enable signal terminal, or variety. Correspondingly, one driving period of the gate driving circuit 7 may refer to one frame driving period of the display panel. Therefore, the display panel can also judge whether the gate driving circuit in the display screen 1 normally outputs the shift signal through the number of high-level pulses of the second output terminal Vout2 in one driving cycle of the gate driving circuit. In this exemplary embodiment, as shown in FIG. 7 , the detection circuit 8 may also be integrated in the non-display area 12 of the display screen.

As shown in FIG. 8 , it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure. The gate driving circuit 7 may include a plurality of cascaded shift register units 71 , and the plurality of shift register units 71 may sequentially output shift signals according to the increasing order of their stages. For example, the shift register unit 71 in FIG. 8 sequentially outputs shift signals from top to bottom. Wherein, at least part of the output end of the shift register unit 71 may be used to form the first output end. For example, as shown in FIG. 8 , a shift register unit may be arranged at intervals between the first output ends of two adjacent poles, that is, the first output end of the first stage may be connected to the shift register unit of the first stage, and the first output end of the second stage may be connected to the shift register unit of the second stage. The output terminal can be connected to the third-stage shift register unit. It should be understood that, in other exemplary embodiments, other numbers of shift register units may be arranged at intervals between the first output terminals of adjacent two poles, or shift register units may be arranged without intervals between the first output terminals of adjacent two poles register unit. By adjusting the number of shift register units between the first output ends of two adjacent poles, the interval between two adjacent pulse signals of the second output end can be adjusted. In addition, the number of shift register units spaced between the first output terminals of different adjacent two poles may be the same or different.

In this exemplary embodiment, as shown in FIG. 9 , it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure. As shown in FIGS. 7 and 9 , the display panel may further include: a driving chip 4 , the driving chip 4 may be connected to the first power supply terminal VDD, the second voltage terminal VGL, and the start signal terminal STV, and the driving chip 4 may It is used to provide corresponding signals to the first power supply terminal VDD, the second voltage terminal VGL and the start signal terminal STV respectively. The first power supply terminal VDD can provide a high-level voltage to the gate driving circuit, and the second voltage terminal VGL can provide a low-level voltage to the gate driving circuit. In one frame driving period, the start signal terminal STV A start signal can be provided to the input signal terminal of the first pole shift register unit in the above gate driving circuit, and the gate driving circuit can start to send the signal to the first pole in response to an active level signal of the start signal terminal STV. An output terminal outputs the shift signal, and the active level signal of the start signal terminal STV may be earlier than all the shift signals in timing. The detection circuit 8 may further include a third transistor T3 and a fourth transistor T4, the gate of the third transistor T3 is connected to the second power supply terminal VGL, and the first electrode is connected to the first power supply terminal VDD; the gate of the fourth transistor T4 The pole is connected to the start signal terminal STV, the first pole is connected to the second pole of the third transistor T3, and the second pole is connected to the second output terminal Vout2. Wherein, the multi-stage shift register unit sequentially outputs the shift signals according to the increasing order of the stages, and the multi-stage first output terminals sequentially output the shift signals according to the increasing order of the stages. The output terminal of the M+(X-1) Nth stage shift register unit is used to form the Xth stage first output terminal, wherein M, N, X are positive integers greater than or equal to 1, and M is not equal to N. For example, as shown in Figure 9, M is equal to 4 and N is equal to 2. As shown in FIG. 10, it is a timing diagram of each node in FIG. 9, wherein STV is the timing diagram of the start signal terminal STV, Vout11 is the timing diagram of the first output terminal Vout11 in FIG. 9, and Vout12 is the first output terminal in FIG. 9. The timing diagram of the output terminal Vout12, Vout13 is the timing diagram of the first output terminal Vout13 in FIG. 9, Vout1n is the timing diagram of the first output terminal Vout1n in FIG. 9, and Vout2 is the timing diagram of the second output terminal in FIG. 9. As shown in FIG. 10 , when the driving chip operates normally, that is, the first power supply terminal VDD outputs a high-level voltage, the second voltage terminal VGL outputs a low-level voltage, and the start signal terminal STV inputs a start signal to the gate driving circuit , the second output terminal Vout2 can output a high-level pulse signal. And since M is greater than N, the distance between the first pulse signal and the second pulse signal in the second output terminal Vout2 is greater than the distance between other adjacent pulse signals. Therefore, it can be judged whether the display panel outputs the pulse signal corresponding to the start signal terminal according to the output pulse signal form of the second output terminal Vout2. When the display panel outputs the pulse signal corresponding to the start signal terminal, it can be considered that the driver chip is working normally. .

As shown in FIG. 9 , both the third transistor and the fourth transistor may be P-type transistors. It should be understood that, in other exemplary embodiments, the third transistor may be an N-type transistor, and the fourth transistor may also be an N-type transistor. Correspondingly, the gate of the third transistor may be connected to the VDD of the first cell, and the first electrode may be connected to the second power supply terminal VGL. In addition, the third transistor and the fourth transistor may also be switch units of other structures.

As shown in FIG. 11 , it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure. The detection circuit may further include an RC filter circuit, the RC filter circuit may include a resistor R and a capacitor C, and the resistor R and the capacitor C may be connected in parallel between the second output terminal Vout2 and the ground terminal GND. The RC filter circuit may filter the waveform of the second output terminal so that the second output terminal outputs a smooth waveform.

As shown in FIG. 3 , the power management circuit 3 can also be used to provide a high-level signal to the pixel driving circuit, and the power management circuit 3 can provide a high-level signal to the first power signal terminal VDD in FIG. 2 . As shown in FIG. 12 , it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure. The first voltage terminal V1 may be located on the display screen, and the first voltage terminal V1 may be connected to the first pole of the driving transistor T3 in FIG. 2 . In this exemplary embodiment, the voltage of the reference voltage terminal Vref may be smaller than the voltage of the first voltage terminal V1. Similarly, the display panel can also judge whether the voltage of the first voltage terminal V1 is normal through the number of pulse signals output by the second output terminal Vout2.

In this exemplary embodiment, the display panel may be provided with two inspection circuits 8 shown in FIG. 3 , and the two detection circuits 8 may be respectively used to detect the cathode voltage of the light-emitting unit and the high-level voltage in the pixel driving circuit.

The present exemplary embodiment also provides a display panel detection method for detecting the above-mentioned display panel, wherein the detection method may include:

The detection method has been described in detail in the above content, and will not be repeated here.

Under different brightness of the display panel, the current passing through the first voltage terminal is different, so that the voltage drop of the trace used to transmit the power signal to the first voltage terminal is also different, which causes the voltage of the first voltage terminal to fluctuate under different brightness. , the brightness of the display panel will be abnormal, and even the color shift will occur.

The present exemplary embodiment also provides a compensation method for a display panel for compensating the above-mentioned display panel, wherein the compensation method may include:

According to the above content, when the number of resistors in the voltage divider circuit is large, the voltage of the first voltage terminal can be limited to a smaller range value by the number of pulse signals at the second output terminal. Therefore, the voltage value of the first voltage terminal can be approximately obtained, and the display panel can compensate the first voltage terminal in the display screen by the voltage value of the first voltage terminal.

The present exemplary embodiment also provides a display device, as shown in FIG. 13 , which is a schematic structural diagram of an exemplary embodiment of the display device of the present disclosure. The display device may include: the above-mentioned display panel 9 and the processor 10, and the processor 9 may be connected to the second output end of the display panel 10 for recording in one frame of driving cycle, the second output The number of output pulse signals at the terminal. Therefore, the display device can judge whether the first voltage terminal in the display panel is at a normal voltage value according to the number of pulses obtained by the processor 9 .

Other embodiments of the present disclosure will readily suggest themselves to those skilled in the art upon consideration of the specification and practice of what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or techniques in the technical field not disclosed by the present disclosure . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the claims.

It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

A display panel, wherein the display panel comprises:

the first voltage terminal;

a gate drive circuit, the gate drive circuit includes a multi-stage first output terminal, and the multi-stage first output terminal outputs shift signals at intervals in sequence;

Detection circuit, including:

a voltage divider circuit, connected between the first voltage terminal and the reference voltage terminal, the voltage divider circuit includes a multi-stage voltage output terminal, and the voltage output terminal and the first output terminal are arranged in a one-to-one correspondence;

A plurality of first switch units are arranged in a one-to-one correspondence with the multi-stage voltage output terminals, the control terminals of the first switch units are connected to the corresponding voltage output terminals, and the first terminals of the first switch units are connected to the first power terminal;

A plurality of second switch units are arranged in a one-to-one correspondence with a plurality of the first switch units, the control end of the second switch unit is connected to the corresponding first output end, and the first end is connected to the corresponding first output end The second end of the first switch unit is connected to the second output end.
The display panel of claim 1, wherein the display panel further comprises:

a driving chip, connected to the first power supply terminal, the second voltage terminal and the starting signal terminal, and used to provide corresponding signals to the first power supply terminal, the second voltage terminal and the starting signal terminal respectively;

Wherein, the gate driving circuit is connected to the start signal terminal, and in a frame driving period, the gate driving circuit is configured to start outputting to the first in response to an active level signal of the start signal terminal The terminal outputs the shift signal, and the effective level signal of the start signal terminal is earlier than all the shift signals in timing;

a third switch unit, the control terminal is connected to the second power terminal, and the first terminal is connected to the first power terminal;

In the fourth switch unit, the control terminal is connected to the start signal terminal, the first terminal is connected to the second terminal of the third switch unit, and the second terminal is connected to the second output terminal.
The display panel of claim 1, wherein the voltage dividing circuit comprises:

a plurality of resistors, wherein a plurality of the resistors are connected in series between the first voltage terminal and the reference voltage terminal;

The voltage output terminal of the voltage dividing circuit is connected between the adjacent resistors.
The display panel according to claim 3, wherein one of the resistors is connected between the voltage output terminals of two adjacent stages, and the resistance values of a plurality of the resistors are the same.
The display panel of claim 1, wherein,

The first switch unit includes:

a first transistor, the gate of which is connected to the corresponding voltage output terminal, and the first stage is connected to the first power supply terminal;

The second switch unit includes:

The gate of the second transistor is connected to the corresponding first output terminal, the first stage is connected to the second pole of the corresponding first transistor, and the second pole is connected to the second output terminal.
The display panel of claim 2, wherein the third switch unit comprises:

a third transistor, the gate is connected to the second power supply terminal, and the first pole is connected to the first power supply terminal;

The fourth switch unit includes:

The gate of the fourth transistor is connected to the start signal terminal, the first electrode is connected to the second electrode of the third transistor, and the second electrode is connected to the second output end.
The display panel of claim 5, wherein the first transistor is an N-type transistor or a P-type transistor, and the second transistor is an N-type transistor or a P-type transistor.
The display panel of claim 1, wherein the display panel further comprises:

The display screen includes a plurality of light-emitting units, and the first voltage terminal is located on the display screen and is connected to the cathode of the light-emitting units.
The display panel of claim 1, wherein the display panel further comprises:

A display screen, the display screen includes a plurality of pixel driving circuits, the pixel driving circuits include driving transistors, the first voltage terminal is located on the display screen, and is connected to the first pole of the driving transistors, the driving The transistor is used to output a drive current to its second pole according to its gate voltage.
The display panel of claim 1, wherein the display panel further comprises a plurality of pixel driving circuits;

The gate driving circuit is used for providing a gate driving signal to the pixel driving circuit.
The display panel according to claim 10, wherein the multi-level voltage output terminals include n-level power output terminals, wherein the voltage of the m-th level voltage output terminal is smaller than the voltage of the m+1-th level voltage output terminal;

The first output terminal of the m-th stage is set corresponding to the voltage output terminal of the m-th stage, wherein the first output terminal outputs the shift signal at intervals according to the increasing order of the number of stages, or the first output terminal outputs the shift signal according to the order of its stages. The shift signals are sequentially output at intervals in decreasing order of numbers.
The display panel of claim 11 , wherein the gate driving circuit comprises a plurality of cascaded shift register units, and at least part of the output ends of the shift register units are used to form the first output end.
The display panel according to claim 12 , wherein the shift register units of multiple stages sequentially output shift signals according to the increasing order of the number of stages;

The multi-stage described first output terminals sequentially output shift signals according to the increasing order of their stages;

The output terminal of the M+(X-1) Nth stage shift register unit is used to form the Xth stage first output terminal, wherein M, N, X are positive integers greater than or equal to 1, and N is not equal to M.
The display panel according to claim 8, wherein the display screen includes a non-display area, and the detection circuit is integrated in the non-display area of the display screen.
The display panel of claim 1, wherein the detection circuit further comprises:

An RC filter circuit is connected to the second output end.
A method for detecting a display panel, used for detecting the display panel according to any one of claims 1-15, comprising:

Obtaining the number of pulse signals output by the second output terminal in one frame of driving period;

Determine whether the voltage of the first voltage terminal in the display panel and the gate driving circuit are normal according to the number of pulse signals output by the second output terminal in one frame driving period;

Wherein, when the number of pulse signals output by the second output terminal in one frame driving period is equal to a preset value, the voltage of the first voltage terminal and the gate driving circuit are normal;

Otherwise, the voltage of the first voltage terminal or the gate driving circuit is abnormal.
A display panel compensation method for compensating the display panel according to any one of claims 1-15, comprising:

Obtaining the number of pulse signals output by the second output terminal in one frame of driving period;

The voltage of the first voltage terminal is compensated according to the number of pulse signals output by the second output terminal in one frame driving period.
A display device, wherein the display device comprises:

The display panel of any one of claims 1-15;

The processor is connected to the second output terminal of the display panel, and is used for recording the number of pulse signals output by the second output terminal in one frame of driving period.