CN106255346A - A kind of interlayer interconnection process - Google Patents
A kind of interlayer interconnection process Download PDFInfo
- Publication number
- CN106255346A CN106255346A CN201610713111.6A CN201610713111A CN106255346A CN 106255346 A CN106255346 A CN 106255346A CN 201610713111 A CN201610713111 A CN 201610713111A CN 106255346 A CN106255346 A CN 106255346A
- Authority
- CN
- China
- Prior art keywords
- interconnection
- present
- carried out
- interlayer interconnection
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Medicines Containing Plant Substances (AREA)
Abstract
The present invention relates to circuit board manufacturing area, particularly to a kind of interlayer interconnection process.Its technical scheme is to use following steps: one is that copper face is carried out roughening treatment；Two is by wire bonding equipment, and the copper face needing interconnection is carried out golden convex making, golden convex height 50 ~ 70um；Three is covering glue layer, glue thickness 25um；Four is by another side copper and its para-position hot pressing, temperature 140 degree, continuous pressing 4 hours, completes interlayer interconnection.The invention has the beneficial effects as follows: solving flow process present in prior art complicated, wet process has considerable influence problem to product harmomegathus, and the present invention uses dry process scheme, and step is simple, it is to avoid the problem that product is produced harmomegathus.
Description
Technical field
The present invention relates to circuit board manufacturing area, particularly to a kind of interlayer interconnection process.
Background technology
Along with the development of science and technology, it is the most convenient that various electronic products have brought for daily life, and
These product great majority all possess light weight, and the features such as thickness is thin, therefore, the circuit board of multilayer interconnection becomes each big electronic product
The development priority of manufacturing enterprise.Chinese patent literature Patent No. CN200710039305.3 discloses a kind of printed circuit board
Manufacture method, employed technical scheme comprise that a kind of based on plating filling perforation and semi-additive process formed circuit and realize interlayer interconnection
Method, the technique of its interlayer interconnection or traditional approach realize: hole-> electroplate.
Chinese patent 201310270208.0 discloses a kind of printed circuit board interconnected manufacture method, and description is with copper post+plating
The mode of copper filling perforation realizes interlayer interconnection, and its inventive point is to improve the defect of tradition interlayer conduction technique by making copper post,
Its flow process can be sketched into: makes copper post-> lamination-> boring-> plating.
Said method is all the interconnection being realized interlayer by electric plating method in hole, and its processing step is various, produces difficulty
Degree is big, easily causes the decline of product fine rate and increases the production cost of product to a certain extent.
Chinese patent literature Patent No. CN201410775664.5, discloses " a kind of interlayer interconnection process ", and it is concrete
Processing step can be sketched and be: 1.. select base material；2.. the attaching of sensitive material；3.. expose, develop；4.. plating；5.. remove sense
Luminescent material；6.. glue-line attaches；7.. interlayer alignment is fitted；8.. pressing also completes interlayer interconnection.
Technology there is the problem that flow process is complicated now, and wet process has considerable influence to product harmomegathus.
Summary of the invention
The purpose of the present invention is aiming at the drawbacks described above that prior art exists, it is provided that a kind of interlayer interconnection process, it is adopted
Using dry process scheme, step is simple.
Its technical scheme is to use following steps:
One is that copper face is carried out roughening treatment；
Two is by wire bonding equipment, and the copper face needing interconnection is carried out golden convex making, golden convex height 50 ~ 70um；
Three is covering glue layer, glue thickness 25um；
Four is by another side copper and its para-position hot pressing, temperature 140 degree, continuous pressing 4 hours, completes interlayer interconnection.
The invention has the beneficial effects as follows: solving flow process complexity present in prior art, product harmomegathus is had by wet process
Considerable influence problem, the present invention uses dry process scheme, step is simple, it is to avoid the problem that product is produced harmomegathus.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of the present invention.
Detailed description of the invention
In conjunction with accompanying drawing 1, the invention will be further described:
A kind of interlayer interconnection process that the present invention mentions, employing following steps:
A, it is that copper face is carried out roughening treatment；
B, it is by wire bonding equipment, the copper face needing interconnection is carried out golden convex making, golden convex height 50 ~ 70um；
C, it is covering glue layer, glue thickness 25um；The optional epoxide-resin glue of glue line used, acrylic glue or liquid crystal polymer
Any one in glue.
D, it is by another side copper and its para-position hot pressing, temperature 140 degree, continuous pressing 4 hours, completes interlayer interconnection.
The invention have the advantage that and solve flow process complexity present in prior art, product harmomegathus is had bigger by wet process
Affecting problem, the present invention uses dry process scheme, step is simple, it is to avoid the problem that product is produced harmomegathus.
The above, be only the part preferred embodiment of the present invention, and any those of ordinary skill in the art all may profit
Revised or be revised as the technical scheme of equivalent by the technical scheme of above-mentioned elaboration.Therefore, according to the technology of the present invention
Any simple modification that scheme is carried out or substitute equivalents, belong to the greatest extent the scope of protection of present invention.
Claims (1)
1. an interlayer interconnection process, it is characterized in that use following steps:
One is that copper face is carried out roughening treatment；
Two is by wire bonding equipment, and the copper face needing interconnection is carried out golden convex making, golden convex height 50 ~ 70um；
Three is covering glue layer, glue thickness 25um；
Four is by another side copper and its para-position hot pressing, temperature 140 degree, continuous pressing 4 hours, completes interlayer interconnection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610713111.6A CN106255346A (en) | 2016-08-24 | 2016-08-24 | A kind of interlayer interconnection process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610713111.6A CN106255346A (en) | 2016-08-24 | 2016-08-24 | A kind of interlayer interconnection process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106255346A true CN106255346A (en) | 2016-12-21 |
Family
ID=57595137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610713111.6A Pending CN106255346A (en) | 2016-08-24 | 2016-08-24 | A kind of interlayer interconnection process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106255346A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1104404A (en) * | 1993-04-16 | 1995-06-28 | 株式会社东芝 | Circuit elements and manufacture of same |
| CN1599048A (en) * | 2003-09-19 | 2005-03-23 | 株式会社村田制作所 | Method for manufacturing an electronic circuit device and electronic circuit device |
| US20100221909A1 (en) * | 2007-12-17 | 2010-09-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for making an electric interconnection between two conducting layers |
| CN104768336A (en) * | 2014-12-17 | 2015-07-08 | 安捷利电子科技（苏州）有限公司 | Interlayer interconnection process |
-
2016
- 2016-08-24 CN CN201610713111.6A patent/CN106255346A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1104404A (en) * | 1993-04-16 | 1995-06-28 | 株式会社东芝 | Circuit elements and manufacture of same |
| CN1599048A (en) * | 2003-09-19 | 2005-03-23 | 株式会社村田制作所 | Method for manufacturing an electronic circuit device and electronic circuit device |
| US20100221909A1 (en) * | 2007-12-17 | 2010-09-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for making an electric interconnection between two conducting layers |
| CN104768336A (en) * | 2014-12-17 | 2015-07-08 | 安捷利电子科技（苏州）有限公司 | Interlayer interconnection process |
Non-Patent Citations (1)
| Title |
|---|
| 王天曦: "《现代电子工艺》", 30 November 2009 * |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161221 |
|
| WD01 | Invention patent application deemed withdrawn after publication |