CN106160725B - The method whether output circuit and detecting load are connected to the connectivity port corresponding to output circuit - Google Patents
The method whether output circuit and detecting load are connected to the connectivity port corresponding to output circuit Download PDFInfo
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- CN106160725B CN106160725B CN201510168700.6A CN201510168700A CN106160725B CN 106160725 B CN106160725 B CN 106160725B CN 201510168700 A CN201510168700 A CN 201510168700A CN 106160725 B CN106160725 B CN 106160725B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
- H04N17/045—Self-contained testing apparatus
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
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Abstract
A kind of output circuit includes: a level regulation circuit and a decision circuitry.An output end of the output circuit to generate an output to the output circuit, the output end are coupled to a connectivity port.The level regulation circuit is coupled to the output end, and to according to, in the second voltage signal on the first voltage signal of one first period and the output end in one second period, generating signal after at least one adjustment on the output end.The decision circuitry is coupled to the level regulation circuit, and judges signal to generate one according to signal after at least one adjustment, and wherein this judges that signal points out whether the connectivity port is connected to a load.
Description
Technical field
The present disclosure generally relates to output circuit, whether espespecially a kind of detecting load is connected to the connecting pin corresponding to output circuit
The output circuit of mouth, related method for detecting and image output circuit.
Background technique
In general, multimedia playing apparatus (such as set-top box) is usually defeated by video-audio signal through connectivity port and transmission line
Out to display equipment.In order in response to the different images signal specification supported in different display equipment, on multimedia playing apparatus
It is commonly configured with the connectivity port for being compatible to different size, for example, composite video signal specification (Composite video), S are regarded
Frequency signal specification (S-Video), color difference video signal specification (Component Video), digital video interface specification
(Digital Visual Interface, DVI) and high-definition multimedia interface specification (High Definition
Multimedia Interface, HDMI) etc..However, only the configuration of pipe multimedia playing apparatus is compatible to the connection of different size
Port, but in actual use, often there is the connectivity port of part to be not connected to any display equipment, and it is relevant to these companies
The output circuit or signal processing circuit for connecing port because that can not know whether need output image signal, and must maintain normal
Running, in turn results in meaningless energy dissipation.In order to avoid meaningless energy consumption, there are several detecting videos in known techniques
The technology whether transmission line is connected with connectivity port.Through such detection techniques, multimedia playing apparatus can be further by letter
Power down mode is closed or switched to number processing circuit or output circuit, reduces power consumption.
Common detection techniques are the middle setting mechanical braking arrangements in connectivity port.When the connection terminal of transmission line is inserted
When entering connectivity port, the spring leaf in mechanical braking arrangement is bounced so that it is subsidiary in the circuit on spring leaf thus open a way or short
Road generates current or voltage signal.Also, this signal will be fed back to signal processing circuit or output circuit, control its running
State.In this way, signal processing circuit or output circuit can when not receiving the signal generated by mechanical braking arrangement pass
It closes, and when transmission line is inserted into connectivity port, starting when receiving the signal of mechanical braking arrangement generation.However, this mode
Cause the promotion of hardware cost, that is, the hardware cost of mechanical braking arrangement and its additional circuits.Also, in this framework
In, signal processing circuit or output circuit need to provide additional signal pin to receive signal.Thus increase output
The complexity of circuit or the circuit layout of signal processing circuit.Also, mechanical braking arrangement may be due to plugging transmission line repeatedly
Abrasion is even destroyed.
Fig. 1 and Fig. 2 depict a kind of known detection techniques, and have been explained in detail in this detection techniques and may face
The problem of.Referring to FIG. 1, the output stage in output circuit 10 can produce an output electric current I_OUT to output end E_OUT, provide
To load 50, and output end E_OUT concatenates a build-out resistor R1, and equivalent resistance R2 of the resistance value of build-out resistor R1 and load 50
Match, in this detection techniques, the voltage V_OUT on output end E_OUT is compared by comparator with critical voltage value VTH,
To judge whether output circuit 10 connect with load 50, but the accuracy of this detection techniques but will receive output circuit
10 are influenced with the coupled modes for loading 50.(a) of Fig. 2 is partially depicted under dc-couple (coupled capacitor C is not present), defeated
When the output stage of circuit 10 exports a fixed current I_OUT out, the variation of voltage V_OUT.Wherein, when load 50 and output circuit
10 it is connected when, build-out resistor R1 that output end E_OUT is concatenated forms in parallel with the equivalent resistance R2 of load 50, makes output end E_
Lower voltage V_OUT is generated on OUT (there is voltage value Vt1)；Conversely, if load 50 when not being connected with output circuit 10, it is defeated
Higher voltage V_OUT is then generated on outlet E_OUT (there is voltage value Vt2).Therefore, the comparator of output circuit 10 is available
One critical value between voltage value Vt1 and Vt2 is as the critical electricity for judging that whether output circuit 10 is connected with load
Pressure value VTH.Part (b) of Fig. 2 then depicts under AC coupled the variation of (coupled capacitor C presence) voltage V_OUT.Wherein,
The situation of variation and the dc-couple of voltage V_OUT have the tendency that it is the same, load 50 be not connected with output circuit 10 when, voltage
V_OUT can be increased.However, be in situation about not being connected with load 50 or in the case where be connected with load 50, voltage V_OUT's
Value is all than dc-couple Shi Weigao.When load 50 is connected with output circuit 10, the voltage value Vt3 of voltage V_OUT is higher than direct current
Voltage value Vt1 when coupling, and when load is not connected with output circuit 10, the voltage value Vt4 of voltage V_OUT is higher than direct current coupling
Voltage value Vt2 when conjunction.In other words, the presence of coupled capacitor C will cause the offset (V_offset) of voltage V_OUT forward direction.Such as
This one, in AC coupled, since Vt3 and Vt4 are all higher than critical voltage value VTH, based on voltage value Vt1 and Vt2 institute
The critical voltage value VTH that selects simultaneously can not allow the comparator of output circuit 10 to correctly judge the connection state of load 50.
It therefore, otherwise and can not be according to fixed critical unless designing the critical voltage value that can change with the presence of coupled capacitor C
Voltage is simultaneously in response to the situation of dc-couple and AC coupled.However, output circuit can directly be increased by designing variable critical voltage
10 circuit complexity.It follows that there are still the defects to need to be improved for known detection techniques.
Summary of the invention
From the foregoing, it will be observed that due to the coupled capacitor between output circuit and load will cause it is defeated on the output end of output circuit
Variation out, thus cause comparator can not correctly judge load whether connect with output circuit.Therefore, the present invention mentions
A kind of mode for eliminating the offset in output voltage out, no matter offset presence or absence, Rule of judgment set by this mode is (i.e.
The critical voltage of comparator) connection status that can correctly judge and load.Furthermore, it is understood that the present invention is in output circuit
In joined the level regulation circuit for the offset that can eliminate output voltage to solve this problem.Furthermore, it is understood that the present invention in
In different periods, different voltage signals is generated on the output using output circuit, level regulation circuit is recycled to sample this
A little voltage signals, and generate signal adjusted.Finally, decision circuitry can judge to load according to this signal adjusted
Whether connect and output circuit.The offset due to caused by coupled capacitor is fixed to the voltage influence on output end, so
The two is then subtracted each other, can be offset using the voltage signal on output end in level regulation circuit sampling different periods by the present invention
Offset therein.Therefore, the connection shape that subsequent decision circuitry will not can not be judged and load by the interference deviated
Condition.
One embodiment of the invention provides a kind of output circuit, which includes: a level regulation circuit and one
Decision circuitry.An output end of the output circuit to generate an output to the output circuit, the output end are coupled to a connection
Port.The level regulation circuit is coupled to the output end, and to according on the output end in the one first of one first period
In the second voltage signal of one second period on voltage signal and the output end, signal after at least one adjustment is generated.This is sentenced
Deenergizing is coupled to the level regulation circuit, and judges signal to generate one according to signal after at least one adjustment, wherein
This judges that signal points out whether the connectivity port is connected to a load.
Another embodiment of the present invention provides a kind of detect corresponding to whether a connectivity port of an output circuit is connected to
The method of one load, wherein the connectivity port is connected to an output end, and this method includes: in the output end in the first period of Yu Yi
One first voltage signal of upper generation, and in generating a second voltage signal in one second period on the output end；According to this
First voltage signal and the second voltage signal generate signal after at least one adjustment；And according to this at least one adjustment after believe
It number generates and one to judge signal, wherein this judges that signal points out whether the connectivity port is connected to the load.
Detailed description of the invention
Fig. 1 is the configuration diagram of known output circuit.
Fig. 2 explains the reason of known output circuit can not correctly judge load connection.
Fig. 3 is the configuration diagram of an embodiment of output circuit of the present invention.
Fig. 4 is the configuration diagram of an embodiment of the level regulation circuit of output circuit of the present invention.
Fig. 5 is the level regulation circuit of Fig. 4 in the operation chart in different operating stages.
Fig. 6 is the configuration diagram of another embodiment of the level regulation circuit of output circuit of the present invention.
Fig. 7 is the level regulation circuit of Fig. 6 in the operation chart in different operating stages.
Fig. 8 is the time diagram of the control signal in the level regulation circuit of Fig. 6.
Fig. 9 is the configuration diagram of another embodiment of output circuit of the present invention.
Figure 10 is the operational flowchart of output circuit of the present invention.
Description of symbols
10,100 output circuit
210 output stages
50 loads
R1, R2, R_Gnd resistance
C, C_sample, capacitor
C_sample1~C_sample4
120,220 level regulation circuit
130 decision circuitries
140 signal processing circuits
200 circuit boards
300 Ports
400 connecting lines
500 external device (ED)s
S1~S3, SW1, SW2 controllable switch
E_OUT output end
150 current sources
Specific embodiment
Fig. 3 is the configuration diagram of an embodiment of output circuit of the present invention.As shown, output circuit of the invention
100 include level regulation circuit 120 and decision circuitry 130.Output circuit 100 includes an output end E_OUT, and thoroughly
Cabling on oversampling circuit plate 200 is connected to a connectivity port 300 on circuit board 200.In connectivity port 300 and output end E_
Between OUT, build-out resistor R1 is provided on circuit board 200, to the equivalent electricity with external device (ED) 500 (can be a display equipment)
Resistance R2 is matched (the resistance value R of resistance R1 and R2 are indicated respectively with R1 and R2), thereby increases and it is possible to which there are a coupled capacitor C.
External device (ED) 500 is connected to one end of transmission line 400, and the other end of transmission line 400 can be inserted into connectivity port 300.Work as transmission
It also include a signal processing circuit 140 in output circuit 100 when connectivity port 300 is inserted at 400 end of line.Signal processing circuit 140
In include a circuit output stage, to by signal (such as vision signal) export to external device (ED) 500.In the following description, will
It is formed completely with the narration of " being connected with load " to represent output circuit 100, transmission line 400 and 500 three of external device (ED)
Connection, and with the narration of " not with load be connected " come represent output circuit 100 not with 500 shape of transmission line 400 and external device (ED)
At complete connection, e.g., transmission line 400 is not inserted into connectivity port 300 or transmission line 400 is inserted into connectivity port
300, but do not connect with external device (ED) 500.
In one embodiment, signal processing circuit 140 includes a digital to analog converter of an electric current output form
(DAC), also, digital to analog converter is according to the first digital signal S_code1 and the second digital signal S_code2, generates
Output controls internal circuit output stage, in the first operational phase Phase 1 of output circuit 100 and the second operational phase
In Phase 2, the first electric current for corresponding to the first digital signal S_code1 and the second digital signal S_code2 is generated respectively
I1 and the second electric current I2, to form voltage signal V1 and V2 on output end E_OUT respectively.Level regulation circuit 120 then can
Sampling voltage signal V1 and V2 generate signal S_Adj1 after at least one adjustment, in this adjustment signal, coupled capacitor accordingly
The offset of possibility caused by C will be offseted.It will be described below the working principle of level regulation circuit 120.
Firstly, consider not to be connected with load when output circuit 100, and in the absence of coupled capacitor C, signal processing circuit
The first electric current I1 that circuit output stage in 140 generates in the first operational phase Phase 1 can be formed on output end E_OUT
Voltage value is the first voltage signal V1 of I1*R1.If there are when coupled capacitor C (at signal between right output circuit 100 and load
Circuit output stage in reason circuit 140 equally generates the first electric current I1), then coupled capacitor C can bring additional potential difference Δ 1,
So that the voltage value of first voltage signal V1 is I1*R1+ Δ 1 at this time.Likewise, output circuit 100 not with load be connected and
In the case of coupled capacitor C is not present, the circuit output stage in signal processing circuit 140 is in the second operational phase Phase 2
The the second electric current I2 generated can form the second voltage signal V2 that voltage value is I2*R1 on output end E_OUT.And when output electricity
There are (circuit output stage in signal processing circuit 140 is same to generate the second electric current when coupled capacitor C between road 100 and load
I2), then coupled capacitor C brings additional potential difference Δ 1, will make the voltage value I2*R1+ Δ 1 of second voltage signal V2.It is worth
No matter it is noted that coupled capacitor C presence or absence, if by different operating stages on output end E_OUT caused by the first electricity
Pressure signal V1 and second voltage signal V2 subtracts each other, and finally can all obtain the result of V2-V1=(I2-I1) * R1.It obviously, will be different
The mode subtracted each other again after voltage sampling in period on output end E_OUT can exclude shifted by delta 1 caused by coupled capacitor C.
Then, in the case of considering that work as output circuit 100 is connected with load, and coupled capacitor C is not present, signal processing electricity
The first electric current I1 that circuit output stage in road 140 generates in the first operational phase Phase 1 can on output end E_OUT shape
It is the first voltage signal V1 of I1* (R1//R2) at voltage value；Coupled capacitor C there are in the case of, then on output end E_OUT
First voltage signal V1 voltage value be I1* (R1//R2)+Δ 2.Likewise, being connected and coupling in output circuit 100 with load
In the case of conjunction capacitor C is not present, the circuit output stage in signal processing circuit 140 produces in the second operational phase Phase 2
The second raw electric current I2 can form the second voltage signal V2 that voltage value is I2* (R1//R2) on output end E_OUT；If coupling
In the presence of capacitor C, then the voltage value of the second voltage signal V2 on output end E_OUT is made to become I2* (R1//R2)+Δ 2.If will
First voltage signal V1 and second voltage signal V2 in different operating stages on output end E_OUT is subtracted each other, then can be obtained
V2-V1=(I2-I1) * (R1//R2).Likewise, in the case where output circuit 100 is connected with load, it will be defeated in different periods
The mode subtracted each other again after voltage sampling on outlet E_OUT can also exclude shifted by delta 2 caused by coupled capacitor C.
As seen from the above description, in the case where being connected with load, by different operating stages on output end E_OUT the
One voltage signal V1 is subtracted each other with second voltage signal V2, available voltage signal difference V2-V1=(I2-I1) * (R1//
R2)；And in the case where not being connected with load, then available voltage signal difference V2-V1=(I2-I1) * (R1), therefore, voltage
Signal difference V2-V1 will not be as first voltage signal V1 and second voltage signal V2, by the interference deviated.For another aspect,
Due to load be connected in the case where obtained poor (I2-I1) * (R1//R2) of voltage signal effectively less than not with load phase
Voltage differential signal V2-V1=(I2-I1) * R1 in the case where even with load (in impedance exact matching, in the case where being connected
Voltage signal difference is only the half of the voltage differential signal in the case where not being connected with load), therefore, voltage signal difference V2-V1
The variation with load connection status is certainly reflected.
As long as available as described above, to subtracting each other again after the voltage sampling in different periods on output end E_OUT
It is not shifted by interference, and can reflect the signal of load connection state really.Therefore, the present invention utilizes level regulation circuit 120
Above-mentioned theory is put into effect.Level regulation circuit 120 is on output end E_OUT in the first operational phase Phase_1
First voltage signal V1 is sampled and keeps, and in the second operational phase Phase_2, according to the first voltage kept
Second voltage signal V2 on signal V1, with output end E_OUT at this time generates signal S_Adj1 after at least one adjustment.Come in
One step is with reference to the explanation operated in Fig. 4 about the specific framework of level regulation circuit 120 and in detail.
Fig. 4 depicts the framework of one embodiment of level regulation circuit 120, and wherein level regulation circuit 120 includes
The sample-and-hold circuit as composed by sampling capacitor C_sample and controllable switch S1 and S2, wherein controllable switch
S1 and S2 can be controlled by the control signal that external circuit generates, or be controlled by internal control circuit, both be belonged to
Scope of the invention.
(a) of Fig. 5 partially depicts level regulation circuit 120 in 1 first half of the first operational phase Phase respectively with the portion (b)
Portion and latter half of running.In first half, controllable switch S1 is switched on, so that sampling capacitor C_sample is connected to output
It holds between E_OUT and ground, in this way, the first voltage signal V1 quilt in the first operational phase Phase 1 on output end E_OUT
Sampling capacitor C_sample is sampled.Then, (b) part represent first operational phase Phase_1 it is latter half of in, controllably
System switch S2 is switched on and controllable switch S1 is disconnected, so that sampling capacitor C_sample is connected to output end E_OUT and sentences
Between one input terminal of deenergizing 130, so that first voltage signal V1 be enabled to be maintained in sampling capacitor C_sample, and make
The potential difference at the both ends sampling capacitor C_sample is equal to first voltage signal V1.(c) of Fig. 5 partially depicts level regulation circuit
120 the second operational phase Phase 2 running.At this point, controllable switch S2 is still switched on and controllable switch S1 maintenance
It disconnects, maintains the connection of sampling capacitor C_sample and output end E_OUT and decision circuitry 130.Due in the second operational phase
In Phase 2, voltage on output end E_OUT is V2, and the potential difference at sampling capacitor both ends is V1, therefore level regulation circuit
120 in the second operation time period Phase 2 by provide be equal to V2-V1 adjustment after signal S_Adj1 to decision circuitry 130.
In the second operational phase Phase_2, decision circuitry 130 is activated, and the tune that will be equal to voltage signal difference V2-V1
Signal S_Adj1 is compared with reference signal VTH after whole, so that generating can indicate what whether output circuit 100 was connected with load
Judge signal S_DET.When load is not connected with output circuit 100, judge that signal S_DET can be further utilized at shutdown signal
Manage circuit 140.
In different embodiments of the invention, decision circuitry 130 can by comparison circuit either other with same effect
Circuit is realized, is compared to the signal on its input terminal, realize for voltage differential signal V2-V1 and reference signal VTH it
Between size judgement.No matter and by previous explanation it is found that coupled capacitor C presence or absence, the result one of voltage signal difference V2-V1
It causes, so voltage signal difference V2-V1 can exclude offset caused by coupled capacitor C.Therefore, the reference signal VTH of decision circuitry 130
As long as selection consider variation of the voltage signal difference V2-V1 between different loads connection state.Also that is, being connected according to load
When poor (I2-I1) * (R1//R2) of voltage signal, and poor (I2-I1) the * R1 of voltage signal when load is not connected will refer to
Signal VTH is set between the two different levels.So, decision circuitry 130 can correctly pick out output electricity
The connection status on road 100 and load.It should be noted that the framework for the level regulation circuit 120 that Fig. 4 is painted, is not invented
Limitation.In different embodiments of the invention, level regulation circuit may have the sampling capacitor of different number, controllable switch, with
And different connection type.
Fig. 6 depicts the architecture diagram of another embodiment of level regulation circuit of the present invention.As shown, level regulation circuit
220 include by multiple sampling capacitor C_sample1, C_sample2, C_sample3 and C_sample4, and it is multiple controllable
Make switch S1, S2 and S3 composed by sample-and-hold circuit, and be connected to signal processing circuit 140 output end E_OUT, with
And between two input terminals E_IP and E_IN of decision circuitry 130.Detailed operation about this framework please also refer to Fig. 7.
(a) of Fig. 7 has partially corresponded to the operation of controllable switch in the first operational phase Phase_1, at this point, shown in Figure 6 is controllable
It makes switch S1 to be switched on, sampling capacitor C_sample1 and C_sample2 can be sampled in the first operational phase Phase_1, be exported
Hold the first voltage signal V1 and the first reference signal VREFP on E_OUT.Wherein, it in the first operational phase Phase_1, takes
The stored quantity of electric charge is (V1-VCM) * c1 (capacitance that c1 is sampling capacitor C_sample1) in sample capacitor C_sample1,
And the quantity of electric charge stored in sampling capacitor C_sample2 is that (c2 is the electricity of sampling capacitor C_sample2 to (VREFP-VCM) * c2
Capacitance).Then, in the second operational phase Phase_2, controllable switch S2 be switched on, at this time sampling capacitor C_sample3 with
Second voltage signal V2 and second reference of the C_sample4 by sampling in the second operational phase Phase_2 on output end E_OUT
Signal VREFN (part Fig. 7 (b)).Wherein, stored in sampling capacitor C_sample3 in the second operational phase Phase_2
The quantity of electric charge be (V2-VCM) * c3 (capacitance that c3 is sampling capacitor C_sample3), and institute in sampling capacitor C_sample4
The quantity of electric charge of storage is (VREFN-VCM) * c4 (capacitance that c4 is sampling capacitor C_sample4).Part (c) of Fig. 7 is corresponding
In the third operational phase Phase_3 operation of controllable switch.Controllable switch S3 is switched at this time, by sampling capacitor C_
One end of sample1~C_sample4 is connected to common-mode voltage VCM, and the other end is respectively connected to the defeated of decision circuitry 130
Enter to hold E_IP or E_IN, wherein one end of sampling capacitor C_sample1~C_sample2 is connected to common-mode voltage VCM, and another
One end is then connected to the input terminal E_IP of decision circuitry 130, and one end of sampling capacitor C_sample3~C_sample4 connects
The input terminal E_IN of decision circuitry 130 is then connected to common-mode voltage VCM and the other end.Such connection type will cause
Stored charge in C_sample1~C_sample4 is redistributed.Since total amount of electric charge is constant, therefore can further obtain
Relationship below:
(VCM-VIN) * c1+ (VCM-S_Adj1) * c2=(V1-VCM) * c1+ (VREFP-VCM) * c2；
(VCM-VIP) * c3+ (VCM-S_Adj2) * c4=(V2-VCM) * c3+ (VREFN-VCM) * c4
Wherein, S_Adj1 and S_Adj2 is respectively input terminal E_IP of the output of level regulation circuit 220 to decision circuitry 130
With signal after the adjustment of E_IN)
It is assumed that sampling capacitor C_sample1 is consistent with the capacitance of C_sample2, then can be with from the equation of top first
Obtain following relationship:
S_Adj1=(4*VCM-V1-VREFP))/2
Further, it is assumed that sampling capacitor C_sample3 is consistent with the capacitance of C_sample4, then from top second etc.
The available following relationship of formula:
S_Adj2=(4*VCM-V2-VREFN))/2
The two further equatioies subtract each other, and obtain:
S_Adj1-S_Adj2=((VREFP-VREFN)-(V2-V1))/2
It assumes again that VREFP-VREFN=VTH, can further obtain:
S_Adj1-S_Adj2=((VTH)-(V2-V1))/2.
It follows that as long as decision circuitry 130 compares by the output of level regulation circuit 220 to input terminal E_IP and E_IN
Signal S_Adj1 and S_Adj2 after adjustment, so that it may judge whether the result of V2-V1 is greater than reference signal VTH.Wherein, level
Adjustment circuit 220 subtracts each other the first voltage signal V1 and second voltage signal V2 in different periods on output end E_OUT,
Offset that may be present is eliminated, and further samples reference signal VREFP and VREFN, and after being reflected in exported adjustment
In signal S_Adj1 and S_Adj2, to enable the output result S_DET of decision circuitry 130 that can directly reflect output circuit 100
Whether it is connected with load.
Fig. 8 is further depicted in different operating stages, voltage V_OUT, level adjustment electricity on output end E_OUT
The enable signal S_EN for controlling signal Sctrl1~Sctrl3, decision circuitry 130 of the controllable switch S1~S3 on road 220 respectively
Between sequential relationship.When in a period of the voltage V_OUT on output end E_OUT being equal to V1, control signal Sctrl1 is risen
It rises, controllable switch S1 is connected, level regulation circuit 220 sampling voltage signal V1 and reference signal VREFP.And it is exporting
When in a period of holding the voltage V_OUT on E_OUT to be equal to V2, control signal Sctrl2 is first raised, and leads controllable switch S2
Logical, level regulation circuit 220 sampling voltage signal V2 and reference signal VREFN, then, control signal Sctrl3 are raised,
Controllable switch S3 is connected, redistributes the charge in sampling capacitor C_sample1~C_sample4, finally, enable is believed
Number S_EN rises, and decision circuitry 130 starts to compare S_Adj1 and S_Adj2, generates judging result S_DET.
In the foregoing embodiments, signal processing circuit 140 may turn comprising a number to the simulation of electric current output form
Parallel operation (DAC) forms voltage signal V1 and V1 using electric current I1 and I2 as output in the operational phase on output end E_OUT.
However, in another embodiment, signal processing circuit 140 may include the digital to analog converter of voltage output form
(DAC), and Fig. 9 then depict when signal processing circuit 140 include voltage output form digital to analog converter (DAC)
When, the design variation inside output circuit 100.Wherein, signal processing circuit 140 includes that a voltage output grade 210 is used to produce
Raw output signal, and be connected with output end E_OUT.In this embodiment, current source 150 is respectively in the first operational phase
In Phase_1 and the second operational phase Phase_2, the first reference current and the second reference current are provided, thus in output end E_
First voltage signal V1 and second voltage signal V2 are formed on OUT.In the first operational phase Phase_1 and the second operational phase
In Phase_2, switch SW1 and SW2 are switched on, and current source 150 can provide electric current appropriate and flow through resistance R_Gnd, to export
First voltage signal V1 and second voltage signal V2 are formed on the E_OUT of end.Level regulation circuit 120/220 and decision circuitry
130 operation is then identical to aforementioned.
Figure 10 show the operation workflow figure of output circuit 100 according to an embodiment of the invention, includes following steps:
Step 610: in generating a first voltage signal in the first period on the output end, and in one second period
A second voltage signal is generated on the output end.
Step 620: according to the first voltage signal and the second voltage signal, generating signal after at least one adjustment.
Step 630: generating one according to signal after at least one adjustment and judge signal, wherein the judgement signal points out that load is
It is no to be connected to connectivity port.
Since the concrete operations principle of the above process and implementation variation are described in detail in previous paragraph, therefore do not do separately herein
It repeats.
Above-described output circuit and method for detecting actually can operate in any signal processing system, include image
Processing system.In general, image processing system may carry out solution modulation, decoding, image tune to image data by front stage circuits
Whole equal operation.After, the image frame that front stage circuits generate can penetrate the processing of late-class circuit, and output to display equipment is (such as: outer
Portion's equipment 500).And output circuit 100 of the invention can be used as the late-class circuit of image processing system, receive by prime electricity
Video signal caused by road, and exported after being carried out signal conversion and amplification.Therefore, even if front stage circuits are according to image number
According to generate image frame, if but late-class circuit detect connectivity port not with display equipment be connected when, internal circuit can be closed
The running of element enters power down mode with it is enabled, and avoids unnecessary power consumption.Signal processing circuit 140 in output circuit 100
Analog image signal may be converted into for the digital image signal for generating front stage circuits comprising digital to analog converter.
Then, the current or voltage output stage in signal processing circuit 140 amplifies analog image signal, then penetrates connectivity port 300
On the transmission line 400 that is connected, amplified analog image signal is input to display equipment.Detection techniques of the invention are available
In 140 non-reality output video content of signal processing circuit, such as during hiding from view (blanking), the first behaviour above-mentioned is carried out
Make stage Phase_1, the second operational phase Phase_2 and third operational phase Phase_3 with detect display equipment whether with
Output circuit connection.Wherein, signal processing circuit 140 may will receive specific digital code, to issue specific analog signal,
The current or voltage output stage in signal processing circuit 140 is allowed to generate the first electric current I1 and the second electric current I2 during hiding from view, or
Person is that current source 150 is allowed to generate electric current appropriate, to form first voltage signal V1 and second voltage signal V2 on the output,
Judged for decision circuitry 130.
It, can will be in output circuit 100 when detecting display equipment and not penetrating transmission line 400 and access connectivity port 300
Partial circuit closes (such as: signal processing circuit 140), or even (such as: solution by the prime signal processing circuit in image processing system
Modulation circuit, decoding circuit either image adjustment circuit etc.) it closes or makes it into battery saving mode, because having no output at this time
Necessity of video signal, to reach energy-efficient effect.
In summary, idea of the invention is, carries out two sub-samplings to the output voltage on the output end of output circuit,
And subtract each other the voltage that sampling obtains, eliminate variation caused by coupled capacitor.In simple terms, given coupled capacitor is deposited
, and cause that there is offset in the output voltage on output end, then the sampling result repeatedly sampled to output voltage is all
It can include identical offset, so the two is subtracted each other, one can be obtained there is no offset and can reflect load connection status
The difference (V1-V2) of sampling result.In this way, which the running of decision circuitry/comparator would not can not be just because of variation
Really judge the connection state with load.
Special characteristic, structure described in the embodiment are directed to either with " embodiment " representative mentioned in above
Characteristic system is contained in an at least embodiment of the invention.Furthermore " embodiment " appeared in different paragraphs simultaneously in text
It is non-to represent identical embodiment.Therefore, although describe above for different embodiments, it is referred to different structure features respectively
Or deemed-to-satisfy4 movement, but it should be noted that these different characteristics can pass through modification appropriate and be implemented in simultaneously same
In particular implementation.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification, is all covered by the present invention.
Claims (21)
1. a kind of output circuit generates an output to the output end for being coupled to a connectivity port, includes:
One level regulation circuit is coupled to the output end, to according on the output end in the first voltage of one first period
In the second voltage signal of one second period on signal and the output end, signal after at least one adjustment is generated；Wherein, the position
Quasi- adjustment circuit includes:
One sample-and-hold circuit is coupled to the output end, in the first voltage signal is sampled and kept in first period,
And in, according to the second voltage signal and the first voltage signal that is kept, believing after generating the adjustment in second period
Number；And
One decision circuitry is coupled to the level regulation circuit, judges signal to generate one according to signal after at least one adjustment,
Wherein this judges that signal points out whether the connectivity port is connected to a load.
2. output circuit as described in claim 1, which is characterized in that additionally comprise:
One signal processing circuit is coupled to the decision circuitry, wherein when the judgement signal points out that the load is not attached to the connection
When port, which enters a power down mode.
3. output circuit as claimed in claim 2, which is characterized in that the signal processing circuit includes an electric current output form
A digital to analog converter, the digital to analog converter is respectively in first period and second period, according to one
First digital signal and one second digital signal control the signal processing circuit and generate one first output electric current and one second output
Electric current is to the output end, to generate the first voltage signal and the second voltage signal on the output end.
4. output circuit as claimed in claim 2, which is characterized in that the signal processing circuit includes a voltage output form
A digital to analog converter, wherein the signal processing circuit includes that a current source is coupled to the output end, the current source point
Not in first period and second period, providing one first reference current and one second reference current to the output end, with
The first voltage signal and the second voltage signal are generated on the output end.
5. output circuit as described in claim 1, which is characterized in that the decision circuitry includes:
One comparison circuit is coupled to the sample-and-hold circuit, and there is a first input end to be coupled to a reference signal and one the
Two input terminals are coupled to the sample-and-hold circuit, and the comparison circuit, in second period, receiving from second input terminal should
Signal after adjustment, signal is after comparing the reference signal and the adjustment to generate the judgement signal.
6. output circuit as claimed in claim 5, which is characterized in that the sample-and-hold circuit include a sampling capacitor and
Multiple controllable switch, for those controllable switch in first period, the Schilling sampling capacitor is coupled to the output end and one
Between ground, sample the first voltage signal, and then enable the sampling capacitor be coupled to second input terminal of the comparison circuit with
Between output end, to keep the first voltage signal；Those controllable switch in second period, enable the sampling capacitor couple
Between the output end and second input terminal of the comparison circuit, it is based on the first voltage signal and the second voltage signal
Signal is generated after the adjustment to the comparison circuit.
7. output circuit as described in claim 1, which is characterized in that the level regulation circuit includes:
One sample-and-hold circuit is coupled to the output end, in sampling the first voltage signal and one in first period
First reference signal, and in second period, sampling the second voltage signal and one second reference signal and Yu Yi
Three periods believed according to the first voltage signal, the second voltage signal, first reference signal and second reference for being sampled
Number, generate after a first adjustment signal after signal and a second adjustment.
8. output circuit as claimed in claim 7, which is characterized in that decision circuitry includes:
One comparison circuit is coupled to the sample-and-hold circuit, and there is a first input end to receive signal after the first adjustment, and
One second input terminal receives signal after the second adjustment, to compare after the first adjustment in the third period signal and this second
Signal after adjustment, to generate the judgement signal.
9. output circuit as claimed in claim 8, which is characterized in that the sample-and-hold circuit include multiple sampling capacitors with
And multiple controllable switch, wherein those controllable switch are in first period:
Enable one first sampling capacitor in those sampling capacitors couple the output end and the comparison circuit the first input end it
Between；And
One second sampling capacitor in multiple sampling capacitor is enabled to be coupled between first reference signal and the first input end；
And those controllable switch are in second period:
The third sampling capacitor in multiple sampling capacitor is enabled to be coupled to the output end and one second input of the comparison circuit
Between end；And
One the 4th sampling capacitor in multiple sampling capacitor is enabled to be coupled between second reference signal and second input terminal.
10. output circuit as claimed in claim 9, which is characterized in that those controllable switch are in the third period:
First sampling capacitor is enabled to be coupled between a common mode voltage signal and the first input end of the comparison circuit；
Second sampling capacitor is enabled to be coupled between the common mode voltage signal and the first input end of the comparison circuit；
The third sampling capacitor is enabled to be coupled between the common mode voltage signal and second input terminal of the comparison circuit；And
The 4th sampling capacitor is enabled to be coupled between the common mode voltage signal and second input terminal of the comparison circuit.
11. output circuit as claimed in claim 8, which is characterized in that the comparison circuit is substantially by first reference signal
And the difference of second reference signal, and the difference of the first voltage signal and the second voltage signal is compared.
12. a kind of method whether one load of detecting is connected to the connectivity port corresponding to an output circuit, the wherein connection
Port is connected to an output end, and this method includes:
In generating a first voltage signal in one first period on the output end, and in one second period in the output end
One second voltage signal of upper generation；
According to the first voltage signal and the second voltage signal, signal after at least one adjustment is generated；And
One is generated according to signal after at least one adjustment and judges signal, and wherein this judges that signal points out whether the connectivity port connects
In the load；
Wherein, generate this at least one adjustment after signal the step of include:
In being sampled in first period and keep the first voltage signal；And
In, according to the second voltage signal and the first voltage signal that is kept, believing after generating the adjustment in second period
Number.
13. method as claimed in claim 12, which is characterized in that additionally comprise:
When the judgement signal points out that the load is not attached to the connectivity port, the signal processing circuit in the output circuit is enabled
Into a power down mode.
14. method as claimed in claim 12, which is characterized in that the step of generating the judgement signal includes:
Signal is believed after in second period, comparing a reference signal and the adjustment using a comparison circuit to generate the judgement
Number.
15. method as claimed in claim 14, which is characterized in that generate this at least one adjustment after signal the step of include:
In in first period, one sampling capacitor of Schilling is coupled between the output end and a ground, samples the first voltage signal,
And the sampling capacitor is then enabled to be coupled between an input terminal of the comparison circuit and the output end, to keep the first voltage to believe
Number；And
In in second period, enables the sampling capacitor be coupled between the output end and the input terminal of the comparison circuit, be based on
The first voltage signal and the second voltage signal generate after the adjustment signal to the comparison circuit.
16. method as claimed in claim 12, which is characterized in that generate this at least one adjustment after signal the step of include:
In sampling the first voltage signal and one first reference signal in first period, and in second period, sampling
The second voltage signal and one second reference signal；And
In in a third period, according to the first voltage signal, the second voltage signal, first reference signal sampled with
Second reference signal generates after a first adjustment signal after signal and a second adjustment.
17. the method described in claim 16, which is characterized in that the step of generating the judgement signal includes:
In in the third period, compare after the first adjustment signal after signal and the second adjustment using a comparison circuit, to produce
The raw judgement signal.
18. method as claimed in claim 17, which is characterized in that generate this at least one adjustment after signal the step of include:
One first sampling capacitor is enabled to be coupled between the output end and a first input end of the comparison circuit；And
One second sampling capacitor is enabled to be coupled between first reference signal and the first input end；
And in second period:
A third sampling capacitor is enabled to be coupled between the output end and one second input terminal of the comparison circuit；And
One the 4th sampling capacitor is enabled to be coupled between second reference signal and second input terminal.
19. method as claimed in claim 18, which is characterized in that generate this at least one adjustment after signal the step of include:
In the third period:
First sampling capacitor is enabled to be coupled between a common mode voltage signal and the first input end of the comparison circuit；
Second sampling capacitor is enabled to be coupled between the common mode voltage signal and the first input end of the comparison circuit；
The third sampling capacitor is enabled to be coupled between the common mode voltage signal and second input terminal of the comparison circuit；And
The 4th sampling capacitor is enabled to be coupled between the common mode voltage signal and second input terminal of the comparison circuit.
20. method as claimed in claim 12, which is characterized in that generate the first voltage signal and the second voltage signal
Step includes:
Using a digital to analog converter in first period and second period, causing different size of one first output
Electric current and one second output electric current flow to the output end, to generate the first voltage signal and second electricity on the output end
Press signal.
21. method as claimed in claim 12, which is characterized in that generate the first voltage signal and the second voltage signal
Step includes:
Using an electric current within first period and second period, different size of first reference current and one are provided respectively
Second reference current is to the output end, to generate the first voltage signal and the second voltage signal on the output end.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510168700.6A CN106160725B (en) | 2015-04-10 | 2015-04-10 | The method whether output circuit and detecting load are connected to the connectivity port corresponding to output circuit |
| US14/930,671 US9832459B2 (en) | 2015-04-10 | 2015-11-03 | Output circuit and method for detecting whether load connected to connection port corresponding to output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510168700.6A CN106160725B (en) | 2015-04-10 | 2015-04-10 | The method whether output circuit and detecting load are connected to the connectivity port corresponding to output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106160725A CN106160725A (en) | 2016-11-23 |
| CN106160725B true CN106160725B (en) | 2019-08-23 |
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| CN201510168700.6A Active CN106160725B (en) | 2015-04-10 | 2015-04-10 | The method whether output circuit and detecting load are connected to the connectivity port corresponding to output circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9832459B2 (en) |
| CN (1) | CN106160725B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR3047378B1 (en) * | 2016-01-29 | 2018-05-18 | STMicroelectronics (Alps) SAS | CIRCUIT FOR PROVIDING AN ANALOGUE VIDEO SIGNAL |
| KR102656425B1 (en) * | 2016-12-07 | 2024-04-12 | 삼성전자주식회사 | Electronic apparatus and method for displaying an image |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US1738710A (en) * | 1925-02-21 | 1929-12-10 | Howard B Jones | Method for identifying cabled wires |
| JP3159392B2 (en) * | 1991-04-16 | 2001-04-23 | 富士写真フイルム株式会社 | Image memory device and operation method thereof |
| US5539632A (en) * | 1991-06-28 | 1996-07-23 | Marsh; John K. | Multi-phase and shifted phase power distribution systems |
| EP0543037B1 (en) * | 1991-11-19 | 1995-09-13 | Siemens Aktiengesellschaft | Output circuit with adjustable parameters in an integrated circuit |
| US5479570A (en) * | 1992-10-06 | 1995-12-26 | Matsushita Electric Industrial Co., Ltd. | Learning and recognition machine |
| US5457704A (en) * | 1993-05-21 | 1995-10-10 | At&T Ipm Corp. | Post processing method and apparatus for symbol reliability generation |
| US5491457A (en) * | 1995-01-09 | 1996-02-13 | Feher; Kamilo | F-modulation amplification |
| US5847557A (en) * | 1997-06-06 | 1998-12-08 | Fincher; William C. | Wire pair identification method |
| US6750643B2 (en) * | 2002-08-05 | 2004-06-15 | Richard Hwang | Group wiring patching system and method for wire pair identification |
| CN100410672C (en) * | 2004-06-16 | 2008-08-13 | 瑞昱半导体股份有限公司 | Signal output device and operation method |
| US8284087B2 (en) | 2008-03-04 | 2012-10-09 | Ati Technologies Ulc | System and method for detecting accessory connection and accessory class |
| WO2011048103A1 (en) * | 2009-10-22 | 2011-04-28 | St-Ericsson (Grenoble) Sas | Detection of display device connection |
| CN103378842B (en) * | 2012-04-19 | 2016-01-06 | 扬智科技股份有限公司 | Whether output circuit is connected to the method for transmission line with detecting connectivity port |
| TWI495294B (en) * | 2012-10-30 | 2015-08-01 | Realtek Semiconductor Corp | Method for detecting on-line state of a computer network |
| CN104426524A (en) * | 2013-09-06 | 2015-03-18 | 扬智科技股份有限公司 | Output circuit, method for detecting whether connecting port is connected to load or not and image output circuit |
-
2015
- 2015-04-10 CN CN201510168700.6A patent/CN106160725B/en active Active
- 2015-11-03 US US14/930,671 patent/US9832459B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106160725A (en) | 2016-11-23 |
| US20160301927A1 (en) | 2016-10-13 |
| US9832459B2 (en) | 2017-11-28 |
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