CN106158741B

CN106158741B - Method for realizing degradation of stacked IC defective products by cutting broken wires of packaging body

Info

Publication number: CN106158741B
Application number: CN201510191778.XA
Authority: CN
Inventors: 凡会建; 李文化; 彭志文
Original assignee: Tekism Co ltd
Current assignee: Tekism Co ltd
Priority date: 2015-04-21
Filing date: 2015-04-21
Publication date: 2020-05-15
Anticipated expiration: 2035-04-21
Also published as: CN106158741A

Abstract

The invention discloses a method for realizing degradation of stacked IC defective products by cutting and breaking a packaging body, which comprises a packaging appearance drawing and an internal welding wire drawing, wherein the IC, die, a metal wire, a blade and a dicing saw are arranged, the IC has a multilayer structure, and a problem layer die in the multilayer structure in the tested IC is judged through testing; determining the lower cutter position of a cutter and setting parameters, and in order to meet the cutting precision control requirement, using a dicing saw for cutting a wafer, and placing an IC (integrated circuit) to be cut on a cutting disc with vacuum adsorption of the dicing saw; the cut IC particles can be cleaned and dried in a dicing saw, the rest die is tested after the cleaning and drying, and the IC without the problem in the rest die is used as a degradation product; according to the technical scheme, the scrapped IC is degraded and used through a physical damage isolation method, so that the benefit is increased, and the waste is reduced.

Description

Method for realizing degradation of stacked IC defective products by cutting broken wires of packaging body

Technical Field

The invention belongs to the technical field of integrated circuit packaging, and discloses a method for realizing degradation of stacked IC defective products by cutting and cutting wires of a packaging body.

Background

In order to improve the capacity and increase the functions of IC packages, a multi-die (wafer chip) package manner is commonly used, which includes a manner of placing a plurality of die packages in parallel and a manner of stacking die packages, wherein the number of die stacked layers is different from 2 to 16, and of course, there are also die stacked packages of the same kind and die stacked packages of different kinds, so that the higher the integration level is, the more convenient the IC application is; the advantages of the multiple die packages are obvious, but the package yield is lower than that of a single die package, the defective product ratio is increased by multiple times according to the number of the stacked dice, in a simple manner, the whole IC is scrapped because one wire on one die has a problem, for example, each die of an IC stacked and packaged in two layers needs to be scrapped by 30 wires on a substrate, the two dice share 60 wires, if one wire has a problem, the product is unqualified, but each of the two dice has an independent function, 1 die without broken wires is scrapped, and the whole IC is scrapped because one die has a damage or a defective function; at present, the two layers of stacked die of the packaged good product rate are 99%, while the 4 layers and 8 layers are lower, wherein 1% of the packaged good products cause problems mostly because of a certain line in the packaged good products or 1 die in the packaged good products, about 2% of the packaged good products can also generate defective products in the electrical test, and a large rate of the packaged good products also causes the whole waste because one die has a problem; by isolating problematic Die in a plurality of Die packages and enabling an IC to retain functions of other Die, the IC can play functions of other Die, the problem of waste product processing is solved, a small-sized packaging factory can produce 15 ten thousand 32GB flash memory particles (two wafers of 16GB are overlapped inside the flash memory particles) in one day, 4.5 ten thousand defective products are about to be contained in the flash memory particles, 80% of the defective products are caused by one Die, the IC can be graded into 16GB for use by isolating the Die, 4.5x 80% is about to be recycled as 3.6 ten thousand products, even if 5% of defective products caused by improper operation are 3.4 ten thousand 16GB products, 13.6 ten thousand dollars are saved by calculation according to the current market price of 16GBIC unit price of 4 dollars, the cost of the rework is lower than 0.1 dollars, 12.24 dollars can be saved in one day, and a Die isolation scheme is developed for the problem. The problem of the layer of die in the IC is judged through analysis modes such as IC test or X-ray irradiation, the position of a connecting line between the layer and the substrate is judged according to the packaging structure diagram, and the connecting line between the layer of die and the substrate is cut off by using a scribing knife or laser, so that the functions of other dies of the product can be completely reserved without interference, and the effect of degrading and using the waste products of the produced wire newspaper is achieved.

Disclosure of Invention

In order to solve the problem that one die in a plurality of dice is damaged or the whole IC is scrapped due to poor function in the prior art, the invention discloses a method for determining the cutting position of the die by accurately calculating, so that the cutting position of the die is accurate, and the waste of the die is avoided; the discarded IC is degraded and used by a physical damage isolation method, and the method for degrading the defective stacked IC is realized by increasing the operation and reducing the waste of the cutting and wire breaking mode of the packaging body.

The invention provides a method for realizing degradation of stacked IC defective products by cutting and breaking a packaging body, which comprises a packaging outline drawing, an internal bonding wire drawing, an IC, a wafer chip, a metal wire, a blade and a dicing saw, wherein the IC has a multilayer structure and is realized by the following method:

determining wafer chips of the layers with problems in the tested IC internal multilayer structure through testing;

secondly, determining the lower cutter position of the cutter and setting parameters, wherein the method comprises the following steps:

determining the position of a leading-out metal wire of an upper wafer chip according to a packaging outline drawing and an internal bonding wire drawing, wherein the leading-out metal wire is used for positioning the position of a lower cutter, and the minimum distance from the arc top of the leading-out metal wire to the surface of the upper wafer chip is equal to 40 um;

determining a distance position b from the surface of an upper-layer packaging body to a first-layer wafer chip and a distance position c from the surface of a second-layer wafer chip according to a packaging outline drawing and an internal bonding wire drawing, and determining a cut-in depth; the formula used for the cutting depth e is (b-40+ c)/2;

thirdly, using a dicing saw for cutting the wafer for the purpose of controlling the cutting precision, wherein the dicing saw comprises a mechanical dicing saw and a laser dicing saw; the blade of the mechanical scribing machine is a wafer cutting knife with diamond particles larger than or equal to 2000 and with the blade thickness smaller than 40um, and the cutting speed is smaller than 10 mm/s; the laser scribing machine cuts, and the cutting depth precision of the laser scribing machine is less than 10 um;

fourthly, the IC to be cut is placed on a cutting disc with vacuum adsorption of a dicing saw, different cutting discs can be manufactured according to different materials, and different cutting discs are prepared according to different packaged ICs;

fifthly, the cut wafer chips can be dried through cleaning in the dicing saw, the functions of the remaining wafer chips are tested after the wafer chips are dried through cleaning, and ICs (integrated circuits) which are not problematic in the remaining wafer chips are used as degradation products.

As a further limitation of the present invention, the cutting parameters may be set based on the ability to cut the wire of the upper wafer chip, or may be set based on the ability to cut the upper wafer chip without cutting the lower wafer chip.

Compared with the prior art, the invention has the beneficial effects that: the method for realizing degradation of the stacked IC defective products by cutting the broken wires of the packaging body can accurately determine the cutting position by calculation, so that the cutting position of die is accurate, and waste of die is avoided; the scrapped IC is degraded and used by a physical damage isolation method, so that the business income is increased, and the waste is reduced; the whole design is simple to operate, accurate in cutting, and capable of improving product quality and achieving the effect of degrading and using the waste products of the production line.

Drawings

FIG. 1 is a schematic diagram of a two-layer stacked die LGA package structure for implementing the method of degrading the defective stacked IC by cutting the package body.

FIG. 2 is a diagram showing the calculation of the IC cutting position in the present invention.

FIG. 3 is a schematic view of the cutting position of the diamond cutting blade of the present invention.

Fig. 4 is a schematic view of a structure embodying a trench in the present invention.

Fig. 5 and 6 are schematic views showing the structure of the present invention in which the cutting position is located on the second layer die.

FIG. 7 is a schematic illustration of the cutting of various laminated structures in accordance with the present invention.

Fig. 8 is a schematic diagram of two die packaged ICs according to the present invention.

In the figure: die1, first layer die11, second layer die12, metal line 2, IC platform 3, IC section 4, blade 5, trench 6.

Detailed Description

The present invention will be further described with reference to the accompanying drawings, wherein it is to be understood that the specific embodiments described herein are merely illustrative of the invention and not restrictive thereof.

As shown in fig. 1 to 6, the present invention provides a method for degrading defective products of stacked ICs by cutting and breaking package bodies, including package outline drawings and inner wire bonding drawings, ICs, die, metal wires 2, a blade 5 and a dicing saw, wherein the ICs have a multi-layer structure, and the method is implemented by:

firstly, determining die of a layer with problems in a tested IC internal multilayer structure through testing;

determining the position of an upper die leading-out metal wire 2, marked as a in the drawing, for positioning the position of a lower cutter according to a packaging outline drawing and an internal welding wire drawing; by the arrangement, the specific position of the lower cutter can be determined, and die scrapping caused by wrong cutting positions is avoided.

Determining the distance position from the surface of the upper layer package to the first layer die11, which is marked as b, and the distance position from the surface of the second layer die12, which is marked as c, according to the package outline drawing and the inner bonding wire drawing, thereby determining the cutting-in depth;

thirdly, using a dicing saw for cutting the wafer for the purpose of controlling the cutting precision, wherein the dicing saw comprises a mechanical dicing saw and a laser dicing saw; the blade of the mechanical scribing machine is a wafer cutting knife with diamond particles larger than or equal to 2000 and with the blade thickness smaller than 40um, and the cutting speed is smaller than 10 mm/s; the laser scribing machine cuts, and the cutting depth precision of the laser scribing machine is less than 10 um; so arranged, the cut is of a certain accuracy.

Fourthly, the IC to be cut is placed on a cutting disc with vacuum adsorption of a dicing saw, namely an IC table 3, and a packaging factory can manufacture different cutting discs according to different materials and prepare different cutting discs according to different packaged ICs; thus, the cutting is accurate.

Fifthly, the cut particles can be cleaned and dried by a dicing saw, the residual die functions are tested after cleaning and drying, and the particles which do not have problems are used as degraded products;

the line arc vertex to die surface distance is at least equal to 40 um.

The cutting parameters are set based on the ability to cut the wire 2 of the first layer die11, or may cut into the first layer die11 and not into the second layer die 12.

The cutting depth e of the cutting blade 5 is calculated by using the formula of (b-40+ c)/2, so that the cutting depth can be accurately calculated, and the second layer die12 is not easy to cut.

As shown in fig. 5 and 6, the specific implementation steps are as follows:

step one, calculating a cutting position, which is marked as a and a position cut into the package body by depth, which is marked as e, according to an IC design drawing, and obtaining that e is (b-40+ c)/2 (shown in the figure I);

step two, placing the IC on a vacuum fixed IC platform 3 of a dicing saw, cutting according to the position and the position cut-in depth calculated in the step one (as shown in the figure three), wherein a diamond cutting blade is used for cutting in mechanical cutting, and a blade is not needed for laser cutting, so that the metal wire of the upper die connecting substrate is cut off (as shown in the figures three and four), and the second die12 is not influenced;

and step three, cleaning after cutting, and cutting the groove 6 on the IC resin surface (as shown in the figure four).

Assuming that the second layer die12 needs to be isolated, the cutting-in position and depth are also based on the principle of not affecting other dice or substrates, i.e. cutting lines, and the cutting-in die may also be configured such that the depth position e (as indicated in fig. five and fig. six) is calculated by the calculation formula of (b-40+ c)/2 to obtain a specific value of the depth position, and thus, the calculation is accurate.

As shown in fig. 7, the four-layer die package may have multiple cutting modes, where the cutting modes are stacked from bottom to top in the order of 1, 2, 3, and 4, and include several cutting combinations, which are respectively a fourth layer, a second layer and a fourth layer, a third layer and a fourth layer, and a second layer, a third layer and a fourth layer; a second layer, a first layer and a second layer, the first layer, the second layer and the fourth layer; thus, the combination is convenient.

As shown in fig. 8, 2 die packaged ICs placed in parallel, were used according to the method described above.

According to the method for realizing degradation of the stacked IC defective products by cutting the broken wires of the packaging body, 1, the lower cutter position can be accurately determined through calculation, so that the cutting position of die is accurate, and waste of die is avoided; 2. the scrapped IC is degraded and used by a physical damage isolation method, so that the business income is increased, and the waste is reduced; 3. it should be noted that the above preferred embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and implement the same, and not to limit the scope of the present invention. Any effective variations or modifications made according to the spirit of the present invention should be covered within the scope of the present invention.

Claims

1. A method for realizing degradation of stacked IC defective products by cutting and breaking a packaging body comprises a packaging outline drawing and an internal bonding wire drawing, an IC, a wafer chip, a metal wire, a blade and a dicing saw, wherein the IC has a multilayer structure and is characterized in that: the method is realized by the following steps:

firstly, judging wafer chips of a layer with problems in a multi-layer structure in an IC to be tested through testing;

2. The method for realizing degradation of the defective stacked ICs by cutting and cutting the wire of the package body according to claim 1, wherein: the cutting parameters are set based on the wire capable of cutting the first layer of wafer chips, and the first layer of wafer chips can be cut into and not cut into the second layer of wafer chips.