CN113921500A - Packaging method of silicon wafer level scribing groove - Google Patents
Packaging method of silicon wafer level scribing groove Download PDFInfo
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- CN113921500A CN113921500A CN202010660270.0A CN202010660270A CN113921500A CN 113921500 A CN113921500 A CN 113921500A CN 202010660270 A CN202010660270 A CN 202010660270A CN 113921500 A CN113921500 A CN 113921500A
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- 238000000034 method Methods 0.000 title claims abstract description 125
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 33
- 239000010703 silicon Substances 0.000 title claims abstract description 33
- 238000012544 monitoring process Methods 0.000 claims abstract description 63
- 238000012545 processing Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 15
- 238000013461 design Methods 0.000 claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 238000005336 cracking Methods 0.000 abstract description 25
- 238000012360 testing method Methods 0.000 abstract description 12
- 238000013100 final test Methods 0.000 abstract description 5
- 238000003754 machining Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
Abstract
The invention discloses a packaging method of a silicon wafer level scribing groove, which comprises the following steps: dividing the process monitoring graph in the array of the chips of the wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove by a scribing machine, so that the cracks are easy to find, the failure probability of a terminal is reduced, and a scribing groove is formed between two adjacent chips in the process of processing the silicon wafer level packaging product. The invention solves the problems that chip cracking is easily caused in the final packaging scribing process, a silicon wafer level packaging product is subjected to scribing after testing, and the existing scribing groove structure is not subjected to final testing, so that the existing scribing groove structure is often cracked in the scribing process due to the existence of a graph for process monitoring, the cracked chips are difficult to find, and the existing scribing groove structure has certain probability of failure in the terminal use process.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a packaging method of a silicon wafer level scribing groove.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a function requirement to obtain an independent chip, and the packaging process is as follows: the wafer from the previous process of the wafer is cut into small chips through a scribing process, then the cut chips are pasted on the corresponding small islands of the substrate frame through glue, and then the bonding pads of the chips are connected to the corresponding pins of the substrate through superfine metal wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out the processes of inspection, testing, packaging and the like, and finally warehousing and shipping.
In the traditional processing process of a silicon wafer level packaging product of an 8-inch wafer, a scribing groove is formed between two chips, the width of the scribing groove is different from 25-80um so as to facilitate scribing, the spacing structures are called as cutting channels and sometimes called saw channels or channels, a wafer factory can place a process monitoring graph in the scribing groove, the process monitoring refers to a process flow of finding any line width or overlay error fluctuation by monitoring photoetching graphs on the wafer in real time, the graph of the part of process monitoring has a metal wiring layer and a metal via hole, but the existing chip cracking is easily caused in the final packaging scribing process, the silicon wafer level packaging product is scribed after testing, and the existing scribing groove structure is not finally tested, due to the existence of the graph for process monitoring, the cracking in the scribing process is often caused and difficult to find, there is a certain probability of failure when the terminal is used.
Disclosure of Invention
The invention aims to provide a packaging method of a silicon wafer level scribing groove, which has the advantages of placing process monitoring graphs on two sides of the scribing groove, ensuring the cleanness of the scribing groove and reducing the risk of cracking, and solves the problems that chip cracking is easily caused in the final packaging scribing process in the prior art, a silicon wafer level packaging product is subjected to scribing after testing, and because the final testing is not carried out after scribing, cracking in the scribing process is often caused due to the existence of the graphs for process monitoring in the prior scribing groove structure, the cracking is difficult to find, and failure occurs at a certain probability in the terminal use process.
In order to achieve the purpose, the invention provides the following technical scheme: a packaging method of a silicon wafer level scribing groove comprises the following steps: the method comprises the steps of dividing a process monitoring graph in an array of chips of a wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove through a scribing machine, so that the cracks are easy to find, and the failure probability of a terminal during use is reduced.
Preferably, a scribing groove is formed between two adjacent chips in the process of processing the silicon wafer level packaging product.
Preferably, the design method further includes: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to be provided with any data with a metal wiring layer and metal through holes, respectively placing the two parts of the process monitoring graph on two sides of the scribing groove, and placing the process monitoring graph originally placed in the scribing groove in a pre-vacant area between the chip and the scribing groove.
Preferably, finally, packaging and scribing the wafer by any scribing of diamond, laser and grinding wheel to obtain each corresponding chip product and a chip area with a process monitoring graph, and discarding the chip area.
Preferably, the width of the scribing groove is between 40 and 75 micrometers, and the wafer is 8 inches or 12 inches.
Compared with the prior art, the invention has the following beneficial effects:
the invention has the advantages of placing the process monitoring patterns on the two sides of the scribing groove, ensuring the cleanness of the scribing groove and reducing the risk of the wafer cracking, and solves the problems that the chip cracking is easily caused in the final packaging scribing process in the prior art, the wafer level packaging product is subjected to the scribing after the test, and the final test is not carried out after the scribing, the wafer cracking in the scribing process is often caused due to the existence of the patterns for process monitoring in the prior scribing groove structure, the wafer cracking is difficult to find, and the wafer cracking is invalid at a certain probability in the terminal use process.
Drawings
FIG. 1 is a prior art scribe line and process monitor pattern placement method;
FIG. 2 is a flow chart of a method for packaging a silicon wafer level scribe line according to the present invention;
FIG. 3 is a drawing showing a layout of a scribe line and a process monitor pattern according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", "both ends", "one end", "the other end", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly, such as "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1-3, a method for packaging a silicon wafer level scribe line includes: dividing the process monitoring graph in the array of the chips of the wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove by a scribing machine, so that the cracks are easy to find, the failure probability of a terminal is reduced, a scribing groove is formed between two adjacent chips in the process of processing a silicon wafer level packaging product, and the design method further comprises the following steps: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to place any data with a metal wiring layer and a metal via hole, respectively placing the process monitoring graph divided into two parts on two sides of the scribing groove, placing the process monitoring graph originally placed in the scribing groove in a pre-empty area between the chip and the scribing groove, finally carrying out packaging scribing on the wafer through any scribing of diamond, laser and a grinding wheel, obtaining corresponding chip products and chip areas with the process monitoring graph, discarding the chip areas, enabling the width of the scribing groove to be between 40 and 75 micrometers and enabling the wafer to be 8 inches or 12 inches, and the invention has the advantages of placing the process monitoring graph on two sides of the scribing groove, ensuring the cleanness of the scribing groove and reducing the risk of the scribing groove, the problems that chip cracking is easily caused in the process of finally packaging scribing in the prior art, a silicon wafer level packaging product is subjected to scribing after testing, and due to the fact that final testing is not carried out after scribing, cracking in the scribing process is often caused due to the fact that a graph for process monitoring exists in the existing scribing groove structure, the cracking is difficult to find, and failure occurs at a certain probability in the process of terminal use are solved.
Example 1:
a packaging method of a silicon wafer level scribing groove comprises the following steps: dividing the process monitoring graph in the array of the chips of the wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove by a scribing machine, so that the cracks are easy to find, the failure probability of a terminal is reduced, a scribing groove is formed between two adjacent chips in the process of processing a silicon wafer level packaging product, and the design method further comprises the following steps: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to place any data with a metal wiring layer and a metal via hole, respectively placing the process monitoring graph divided into two parts on two sides of the scribing groove, placing the process monitoring graph originally placed in the scribing groove in a region which is pre-vacant between the chip and the scribing groove, finally packaging and scribing the wafer through diamond scribing to obtain each corresponding chip product and a chip region with the process monitoring graph, discarding the chip region, enabling the width of the scribing groove to be between 40 and 75 micrometers and the wafer to be 8 inches or 12 inches, and having the advantages of placing the process monitoring graph on two sides of the scribing groove, ensuring the cleanness of the scribing groove and reducing the risk of the scribing groove, solving the problem that the existing chip is easy to cause chip scribing when the final packaging and scribing is carried out, the silicon chip level packaging product is subjected to scribing after testing, and because the scribing is not finished, the current scribing groove structure often causes the problem of cracking in the scribing process due to the existence of a pattern for process monitoring, the cracking is difficult to find, and the problem of failure with a certain probability exists in the terminal use process.
Example 2:
a packaging method of a silicon wafer level scribing groove comprises the following steps: dividing the process monitoring graph in the array of the chips of the wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove by a scribing machine, so that the cracks are easy to find, the failure probability of a terminal is reduced, a scribing groove is formed between two adjacent chips in the process of processing a silicon wafer level packaging product, and the design method further comprises the following steps: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to place any data with a metal wiring layer and a metal through hole, respectively placing the process monitoring graph divided into two parts on two sides of the scribing groove, placing the process monitoring graph originally placed in the scribing groove in a pre-vacant area between the chip and the scribing groove, finally packaging and scribing the wafer through laser scribing to obtain each corresponding chip product and a chip area with the process monitoring graph, discarding the chip area, wherein the width of the scribing groove is between 40 and 75 micrometers, and the wafer is 8 inches or 12 inches. The silicon chip level packaging product is subjected to scribing after testing, and because the scribing is not finished, the current scribing groove structure often causes the problem of cracking in the scribing process due to the existence of a pattern for process monitoring, the cracking is difficult to find, and the problem of failure with a certain probability exists in the terminal use process.
Example 3:
a packaging method of a silicon wafer level scribing groove comprises the following steps: dividing the process monitoring graph in the array of the chips of the wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove by a scribing machine, so that the cracks are easy to find, the failure probability of a terminal is reduced, a scribing groove is formed between two adjacent chips in the process of processing a silicon wafer level packaging product, and the design method further comprises the following steps: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to place any data with a metal wiring layer and a metal through hole, respectively placing the process monitoring graph divided into two parts on two sides of the scribing groove, placing the process monitoring graph originally placed in the scribing groove in a pre-empty area between the chip and the scribing groove, finally carrying out packaging scribing on the wafer through a grinding wheel scribing to obtain each corresponding chip product and a chip area with the process monitoring graph, discarding the chip area, enabling the width of the scribing groove to be between 40 and 75 micrometers and the wafer to be 8 or 12 inches, and having the advantages of placing the process monitoring graph on two sides of the scribing groove, ensuring the cleanness of the scribing groove and reducing the risk of the scribing groove, solving the problem that the existing chip is easy to cause chip scribing when the final packaging scribing is carried out, the silicon chip level packaging product is subjected to scribing after testing, and because the scribing is not finished, the current scribing groove structure often causes the problem of cracking in the scribing process due to the existence of a pattern for process monitoring, the cracking is difficult to find, and the problem of failure with a certain probability exists in the terminal use process.
Comparison of three types of dicing in example 1, example 2 and example 3
| Classification | Diamond scribing | Laser scribing | Grinding wheel scribing |
| Speed of processing | 46㎜/s | 150㎜/s | 300㎜/s |
| Depth of machining | 3～10μm | ～100μm | ～100μm |
| Width of machining | 3～10μm | 20～25μm | Less than or equal to the thickness of the blade and less than or equal to 10 mu m |
| Scribing effect | Big crack | With heat loss | With only micro-cracks |
| Yield of finished products | 60～70％ | 70～80％ | 98％ |
| Noise (F) | Small | Big (a) | Is smaller |
In summary, the following steps: the packaging method of the silicon wafer level scribing groove has the advantages that process monitoring graphs are placed on two sides of the scribing groove, the cleanness of the scribing groove is guaranteed, and the risk of cracking is reduced, so that the problem that chip cracking is easily caused in the process of finally packaging scribing in the prior art, a silicon wafer level packaging product is subjected to scribing after testing, and due to the fact that final testing is not carried out after scribing, cracking in the scribing process is often caused due to the fact that the graphs used for process monitoring exist in the structure of the conventional scribing groove, the cracking is difficult to find, and certain probability failure exists in the process of terminal use is solved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A packaging method of a silicon wafer level scribing groove is characterized by comprising the following steps: the method comprises the steps of dividing a process monitoring graph in an array of chips of a wafer into two parts, respectively placing the two parts of the process monitoring graph on two sides of a scribing groove, and then packaging and scribing in the scribing groove through a scribing machine, so that the cracks are easy to find, and the failure probability of a terminal during use is reduced.
2. The method for packaging a silicon wafer level scribe line as claimed in claim 1, wherein: during the processing of the silicon wafer level packaging product, a scribing groove is formed between two adjacent chips.
3. The method for packaging a silicon wafer level scribe line as claimed in claim 1, wherein: the design method further comprises the following steps: dividing the process monitoring graph in the array of the chip of the wafer into two parts, removing the process monitoring graph placed in the scribing groove, enabling the scribing groove not to be provided with any data with a metal wiring layer and metal through holes, respectively placing the two parts of the process monitoring graph on two sides of the scribing groove, and placing the process monitoring graph originally placed in the scribing groove in a pre-vacant area between the chip and the scribing groove.
4. The method for packaging a silicon wafer level scribe line as claimed in claim 1, wherein: finally, packaging and scribing the wafer by any scribing of diamond, laser and grinding wheel to obtain corresponding chip products and chip areas with process monitoring graphs, and discarding the chip areas.
5. The method for packaging a silicon wafer level scribe line as claimed in claim 1, wherein: the width of the scribing groove is between 40 micrometers and 75 micrometers, and the wafer is 8 inches or 12 inches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010660270.0A CN113921500A (en) | 2020-07-10 | 2020-07-10 | Packaging method of silicon wafer level scribing groove |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010660270.0A CN113921500A (en) | 2020-07-10 | 2020-07-10 | Packaging method of silicon wafer level scribing groove |
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| CN113921500A true CN113921500A (en) | 2022-01-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066218A1 (en) * | 2022-09-28 | 2024-04-04 | 长鑫存储技术有限公司 | Mask and layout method therefor, and typesetting pattern of chip |
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2020
- 2020-07-10 CN CN202010660270.0A patent/CN113921500A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066218A1 (en) * | 2022-09-28 | 2024-04-04 | 长鑫存储技术有限公司 | Mask and layout method therefor, and typesetting pattern of chip |
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