200929396 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之製造技術’在半導體 晶圓切割後之晶片接合過程，特別係有關於一種即取即 測之晶片接合方法。 【先前技術】 在半導體之前段製程中，主要可分成ic(積體電路） ❹ ❹ 設計、晶圓製程（wafer fabrication，簡稱 wafer fab)、 晶圓測試（wafer probe )以及晶圓切割，在將一晶圓切 割成小塊之積體電路晶片並經適當分類之後，方可進行 各式封裝（packaging)製程。 曰曰圓測试是利用測試機台與探針卡（pr〇be card)來測 試晶圓上每一個晶粒（die)或稱晶片，以確保晶粒的電氣 特性與效能是依照設計規格製造出來的。測試機台之檢 測頭裝上細如毛髮之探針（pr〇be )，與晶粒上的電極端 (pad )接觸，以便測試其電氣特性，不合格的晶粒會 被標上記號，而後當晶圓依晶粒為單位切割成獨立的晶 粒時，標有記號的不合格晶粒會被淘汰，不再進行下一 個製程，以免徒增製造成本。在進行系統單晶片設計 (system on chip，S〇c)、多晶片模組封裝（muiti。叫 咖―，MCM)或是系統封裝（system in a package，SIP) 時，為避免造成整組模組的報廢而浪費成本，在封裝之 前進行晶圓測試，並確保晶粒係為良品方可進行封裝。 因此，多道的測試與分類是必要的。 5 200929396 一般而言’半導體封裝製程第一道步驟便 合（die bonding)或稱黏晶步驟，其係與晶片測 進行。積體電路完成之晶圆經由晶圓切割步驟 成晶片之後’應作晶片分類，依不同功能等級 同之晶片盒或晶片收納捲帶，接下來方可進— 驟。黏晶之目的乃將一顆顆分離之晶片分別玫 於一晶片載體上，然後利用一晶片吸嘴將已分 ◎之晶片取出，並且放置於該晶片載體上，其已 之工作時間，故降低了工作效率。如果在晶圓 直接進行黏晶步驟，很容易將優質晶片與劣等 在同—晶片載體，特別是運用在多晶片封裝領 不同等級之晶片組裝在同一封装構造内，在運 以劣等晶片之較低工作頻率為基準。如此一來 響封裝產品之工作效能，使得具備優等功能等 體封艘產品的產出值大幅降低。 ❹ 【發明内容】 本發明之主要目的係在於提供一種即取即 方法’在晶片取放同時完成晶片測試與分 要額外的分類收藏’可減少流程時間。並且， 質與劣等晶片混雜在同一封裝產品之情況，以 望的優等功能等級的封裝產品的產出值β 發明之次一目的係在於提供一種即取即 接合方法’可在晶片測試時，減少探觸晶片電 的微检污染，以維持晶片之清潔度。 疋晶片接 試是分開 予以分離 收藏在不 庁黏晶步 置並固定 離與分類 花費較多 切割之後 晶片混雜 域中，將 算時將是 ，便會影 級的半導 測之晶片 類，不需 不會有優 達到所希 測之晶片 極端造成 6 200929396 本發明之另一目的係在於提供一種即取即測之晶片接 合方法，能根據測試結果，預先將不良之晶片在進行黏 晶步驟中加以淘汰’排除誤測誤分類之潛在可能性，以 避免封裝製程的錯誤執行。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明之一種即取即測之晶片接合方 法’首先’提供至少一晶片，係具有複數個電極端，該 ❹晶片係裝載於一來源區。接著，提供複數個晶片載體， 分別裝載於複數個黏晶區，該些黏晶區係依據晶片之功 能等級加以區隔。之後，以一取放吸嘴吸取該晶片，該 取放吸嘴係具有複數個探針，用以探觸該些電極端，在 吸取之後隨即測試該晶片之功能等級，並且該取放吸嘴 係活動於複數個移動路徑，其係由該來源區分別連接至 該些黏晶區。之後’依據該晶片之功能等級，選擇對應 之移動路徑，以移動該取放吸嘴至對應之該些黏晶區之 Ο 其中之一。最後，放置被該取放吸嘴吸附之晶片至對應 黏晶區内之晶片載體。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的晶片接合方法中，該取放吸嘴係可更活動於 一共用路徑’其係連接該來源區與該些移動路徑，當該 取放吸嘴移動於該共用路徑之際，同步完成該晶片之測 試0 在前述的晶片接合方法中，該晶片載體係可為一基板。 7 200929396 在前述的晶片接合方法中，該晶片載體 ί馬另一晶 在前述的晶片接合方法中，該取放吸嘴係可吸附該晶片BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer bonding process after semiconductor wafer dicing, and in particular to a wafer bonding method. [Prior Art] In the pre-semiconductor process, it can be mainly divided into ic (integrated circuit) ❹ ❹ design, wafer fabrication (wafer fabrication, wafer fab), wafer probe (wafer probe) and wafer dicing. After a wafer is cut into small pieces of integrated circuit chips and appropriately classified, various packaging processes can be performed. The round test uses a test machine and a pr〇be card to test each die or wafer on the wafer to ensure that the electrical characteristics and performance of the die are manufactured according to design specifications. of. The test head of the test machine is equipped with a hair-like probe (pr〇be) that is in contact with the electrode terminal (pad) on the die to test its electrical characteristics, and the unqualified die is marked with a mark, and then When the wafer is cut into individual dies according to the die, the unqualified dies marked with marks will be eliminated, and the next process will not be performed, so as not to increase the manufacturing cost. In order to avoid the whole set of modules when performing system on chip (S〇c), multi-chip module package (muiti, called MCM) or system in a package (SIP) The group is scrapped and wastes costs, wafer testing is performed prior to packaging, and the die is guaranteed to be packaged. Therefore, multiple tests and classifications are necessary. 5 200929396 In general, the first step of the semiconductor packaging process is the die bonding or die bonding step, which is performed with the wafer. After the wafers completed by the integrated circuit are processed into wafers by the wafer dicing step, the wafers should be classified, and the tape cassettes or wafers can be taped according to different functional levels, and then the next step can be taken. The purpose of the die-bonding is to separate a separate wafer on a wafer carrier, and then use a wafer nozzle to take out the wafer that has been dispensed, and place it on the wafer carrier, which has been operated for a long time. Work efficiency. If the die bonding step is performed directly on the wafer, it is easy to assemble the high-quality wafer and the inferior wafer carrier, especially the wafers of different grades in the multi-chip package, in the same package structure, which is lower in the inferior wafer. The operating frequency is the benchmark. As a result, the performance of the packaged product is greatly reduced, so that the output value of the product with superior function is greatly reduced. SUMMARY OF THE INVENTION The main object of the present invention is to provide an instant method of performing wafer testing while performing wafer testing and dispensing additional classified collections. Moreover, the quality and the inferior wafers are mixed in the same packaged product, and the output value of the packaged product of the superior functional level is expected to be β. The second objective of the invention is to provide a ready-to-join method that can be reduced during wafer testing. The micro-test contamination of the wafer is probed to maintain the cleanliness of the wafer.疋When the wafer is tested separately, it is separated and stored in the wafer miscellaneous field after the 庁 庁 并 并 并 并 并 并 并 并 并 并 并 并 并 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片There is no need to achieve the desired extremes of the wafer. 6 200929396 Another object of the present invention is to provide a ready-to-measure wafer bonding method in which a defective wafer can be preliminarily subjected to a die bonding step according to the test result. Eliminate 'to eliminate the potential for misclassification of misclassifications to avoid incorrect execution of the packaging process. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A ready-to-measure wafer bonding method in accordance with the present invention 'first' provides at least one wafer having a plurality of electrode ends loaded in a source region. Next, a plurality of wafer carriers are provided which are respectively loaded in a plurality of die-bonding regions which are separated according to the functional level of the wafer. Thereafter, the wafer is sucked by a pick-and-place nozzle, the pick-and-place nozzle has a plurality of probes for detecting the electrode ends, and then testing the functional level of the wafer after the suction, and the pick-and-place nozzle The system is active in a plurality of moving paths, which are respectively connected to the sticky regions by the source regions. Then, according to the functional level of the wafer, a corresponding moving path is selected to move the pick and place nozzle to one of the corresponding dies. Finally, the wafer adsorbed by the pick and place nozzle is placed to the wafer carrier in the corresponding die region. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing wafer bonding method, the pick-and-place nozzle can be more active in a common path 'connecting the source area and the moving paths, and when the pick-and-place nozzle moves on the shared path, the synchronization is completed. Test 0 of the wafer In the aforementioned wafer bonding method, the wafer carrier can be a substrate. 7 200929396 In the foregoing wafer bonding method, the wafer carrier is another crystal. In the foregoing wafer bonding method, the pick and place nozzle can adsorb the wafer.
在前述的晶片接合方法 形成於該取放吸嘴之複數個 在前述的晶片接合方法 貼附於一晶圓切割膠帶。 【實施方式】 中，該取放吸嘴之該些探針係可 真空吸孔内。 中，在該來源區内之該晶片係可 依據本發明之-具體實施例’揭示一種即取即測之 晶片接合方法。第1圖係為該晶片接合方法之工作路徑示 意圖。第2圖係繪示該晶片接合方法中晶片即取即測之 操作示意圖β 請參閱第1圖所示，依據該晶片接合方法，首先係提 供至少一晶片10,該晶片10之主動面12係具有複數 ® 個電極端11。該晶片10係可來自於一已切割之晶圓。 而一晶片接合機台（或稱黏晶機）係包含有至少一個取放吸 嘴30’並規劃有一來源區4〇、複數個黏晶區51、52、53 以及複數個以供該取放吸嘴3〇移動之移動路徑6162、 63。該些移動路徑61、62、63係連接至對應之黏晶區 51 、 52 、 53 ° 可選擇適當之該些移動路徑61、62、63，使該取放 吸嘴30由該來源區4〇移動至該些黏晶區51、52、53之 其中之。該些黏晶區51、52、53係依據晶片之功能 8 200929396 等級加以區隔’以DDR2(雙倍資料傳輸速度）之動態隨 機存取記憶體為例，該些黏晶區51、52、53便可區分 為553Mhz、667Mhz與80 0Mhz，或較佳地，可更區分 有l〇66Mhz與一廢品區。但不受局限地，本發明之晶 片接合方法亦可適用於快閃記憶晶片與其它特殊應用 積體電路（ASIC)。該晶片10係裝載於一來源區4〇。請 參閱第1及2圖所示’在該來源區4〇内之該晶片1〇係 〇 可貼附於一晶圓切割膠帶80，即在晶圓切割之後可直 接進行半導體封裝製程之黏晶作業。該晶圓切割膠帶 80上部分有標記之晶片（如第i圖中打圈之晶片係 為不良或無法運作之晶片。 依據該方法，提供複數個晶片載體2〇，分別裝載於 該些複數個黏晶區51、52、53。該晶片載體20係可為一 基板，可適用於多晶片封裝之基板或是多晶片堆疊之記憶卡 基板。此外，該晶片載體20亦可為另一晶片1〇，以構成多 〇 晶片模組封裝。 該取放吸嘴30係活動於複數個移動路徑61、62、 63，其係由該來源區40分別連接至該些黏晶區5卜52、 53❶首先，該取放吸嘴3〇移動至該來源區4〇並吸取該 晶片10,該取放吸嘴30係具有複數個探針31，用以探 觸位於該晶片10之該些電極端u(如第2圖所示），在 吸取之後隨即測試該晶片1〇之功能等級，並直接加以 分類到對應功能等級範圍之黏晶區5丨、52或53，避免 分類材料（如晶片盒或晶片收納捲帶）之浪費，並能節省 9 200929396 製程步驟。 具體而言，如第2圖所示，該取放吸嘴30係可吸附該 晶片1〇之一主動面12,用以探觸該晶片10之該些電極 端11。較佳地，該取放吸嘴30之該些探針31係可形成於 該取放吸嘴30之複數個真空吸孔32内。該些真空吸孔32 係可利用一真空管線（圖未繪出）連接至一真空源（如真空泵 浦，圖未繪出），以使該取放吸嘴30得以產生一吸附力’以 將該晶片10吸附住。故可在該晶片1 0測試時，減少該些探 針31探觸該晶片10之電極端11造成的微粒污染’以維持 該晶片10之清潔度。 如第1圖所示，依據該晶片10之功能等級，選擇對 應之移動路徑61、62、63，以移動該取放吸嘴30至對 應之該些黏晶區5 1、5 2、5 3之其中之一。根據測試結 果移送至適合之黏晶區51、52、53，可使操作者不需 以人工方式進行揀選分類，進而節省時間。在本實施例 φ 中’該取放吸嘴20係可更活動於一共用路徑70，其係連接 該來源區40與該些移動路徑62,當該取放吸嘴30移動於該 共用路徑70之際，同步完成該晶片10之測試。 最後，放置被該取放吸嘴30吸附之晶片1〇至對應 黏晶區51、52、53内之晶片載體20。可於晶片載體20 預定黏著該晶片1 〇的位置上塗佈黏晶材料，例如環氧 樹脂（epoxy)、銀膠（diver paste)或B階黏膠；或預先貼 上膠片’例如雙面黏性PI膠片，然後利用該取放吸嘴 3 0將該晶片1 〇自晶圓上取出並分類後，選擇對應之移 10 200929396 動路徑61、62、63，並且放置於該晶片載體2〇上。 因此，依據本發明之即取即測之晶片接合方法，在 晶片取放同時完成晶片測試與分類，不需要额外的分類 收藏，可減少流程時間。並且，不會有優質與劣等=片 混雜在同一封裝產品之情況，以達到所希望的高功^等 級封裝產品的產出值。 以上所述，僅是本發明的較佳實施例而已並非對 ❹本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 〇 第1圖.依據本發明之一具體實施例，一種即取即測之 晶片接合方法之工作路徑示意圖。 第2圖·依據本發明之一具體實施例，繪示該晶片接合 方法中晶片即取即測之操作示意圖。 【主要元件符號說明】 10 晶片 11 電極端 12 主動面 20 晶片載體 30 取放吸嘴 31 探針 32 真空吸孔 40 來源區 11 200929396 51 黏晶區 52 黏晶區 53 黏晶區 61 移動路徑 62 移動路徑 63 移動路徑 70 共用路徑 80 晶圓切割膠帶The above-described wafer bonding method is formed by a plurality of the pick-and-place nozzles attached to a wafer dicing tape in the aforementioned wafer bonding method. [Embodiment] The probes of the pick-and-place nozzle are in the vacuum suction hole. The wafer system in the source region can disclose a ready-to-measure wafer bonding method in accordance with the present invention. Figure 1 is a schematic illustration of the working path of the wafer bonding method. FIG. 2 is a schematic diagram showing the operation of the wafer in the wafer bonding method. Referring to FIG. 1 , according to the wafer bonding method, at least one wafer 10 is first provided, and the active surface 12 of the wafer 10 is provided. There are multiple ® electrode ends 11 . The wafer 10 can be from a wafer that has been diced. And a wafer bonding machine (or a die bonding machine) includes at least one pick-and-place nozzle 30' and is planned to have a source region 4〇, a plurality of die-bonding regions 51, 52, 53 and a plurality of for pick-and-place The movement path 6162, 63 of the nozzle 3 〇 moves. The moving paths 61, 62, 63 are connected to the corresponding die-bonding regions 51, 52, 53 °. The moving paths 61, 62, 63 may be selected to be appropriate, so that the pick-and-place nozzle 30 is from the source region. Move to the some of the some of the die-bonding regions 51, 52, and 53. The die-bonding regions 51, 52, and 53 are separated according to the function of the function of the chip 8 200929396. The dynamic random access memory with DDR2 (double data transmission speed) is taken as an example. 53 can be divided into 553Mhz, 667Mhz and 80 0Mhz, or preferably, it can be distinguished from l〇66Mhz and a waste area. However, without limitation, the wafer bonding method of the present invention is also applicable to flash memory chips and other special application integrated circuits (ASICs). The wafer 10 is loaded in a source area 4〇. Please refer to the first and second figures of the wafer in the source area. The wafer can be attached to a wafer dicing tape 80, that is, the die-bonding process can be directly performed after the wafer is diced. operation. The wafer dicing tape 80 is partially marked with a wafer (for example, the wafer in the ith circle is a defective or inoperable wafer. According to the method, a plurality of wafer carriers 2 are provided, respectively, which are respectively loaded on the plurality of wafer carriers The wafer carrier 20 can be a substrate, and can be applied to a multi-chip package substrate or a multi-wafer stack memory card substrate. Further, the wafer carrier 20 can also be another wafer 1取 以 构成 构成 构成 构成 构成 该 该 该 该 该 该 该 该 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取 取First, the pick-and-place nozzle 3 is moved to the source region 4 and sucks the wafer 10. The pick-and-place nozzle 30 has a plurality of probes 31 for detecting the electrode terminals located at the wafer 10. (As shown in Figure 2), the functional level of the wafer is tested immediately after pipetting, and directly classified into the bonded region 5, 52 or 53 of the corresponding functional level to avoid sorting materials (such as wafer cassettes or Waste of wafer storage tape) and can save 9 200929396 Specifically, as shown in FIG. 2, the pick-and-place nozzle 30 can adsorb one of the active faces 12 of the wafer 1 for sensing the electrode ends 11 of the wafer 10. Preferably, The probes 31 of the pick-and-place nozzles 30 can be formed in the plurality of vacuum suction holes 32 of the pick-and-place nozzles 30. The vacuum suction holes 32 can utilize a vacuum line (not shown). Connected to a vacuum source (such as vacuum pumping, not shown) so that the pick and place nozzle 30 can generate an adsorption force to attract the wafer 10. Therefore, the wafer 10 can be reduced during the test. The probes 31 detect the particle contamination caused by the electrode terminals 11 of the wafer 10 to maintain the cleanliness of the wafer 10. As shown in Fig. 1, the corresponding moving paths 61, 62 are selected according to the functional level of the wafer 10. , 63, to move the pick-and-place nozzle 30 to one of the corresponding adhesive crystal regions 5 1 , 5 2 , 5 3 , according to the test result transferred to the suitable die bonding region 51 , 52 , 53 , The operator does not need to manually sort and sort, thereby saving time. In the embodiment φ, the pick-and-place nozzle 20 can be more lively. A common path 70 is connected to the source area 40 and the moving paths 62. When the pick-and-place nozzle 30 moves on the shared path 70, the test of the wafer 10 is completed synchronously. Finally, the placement is performed. The wafer carrier 20 adsorbed by the nozzle 30 is taken up to the wafer carrier 20 in the corresponding die region 51, 52, 53. The die bond material, such as epoxy resin, may be coated on the wafer carrier 20 at a position where the wafer 1 is intended to be adhered. (epoxy), diver paste or B-stage adhesive; or pre-applied with a film such as double-sided adhesive PI film, and then the wafer 1 is taken out of the wafer by the pick-and-place nozzle 30 After sorting, the corresponding shift 10 200929396 moving paths 61, 62, 63 are selected and placed on the wafer carrier 2〇. Therefore, according to the wafer bonding method of the present invention, wafer testing and sorting can be completed while wafer handling is performed, and no additional classification is required, which can reduce the process time. Moreover, there will be no high-quality and inferior = chips mixed in the same package to achieve the desired output value of high-power package products. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. The scope of the present invention is intended to be limited by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing the working path of a wafer bonding method according to an embodiment of the present invention. Fig. 2 is a schematic view showing the operation of the wafer in the wafer bonding method according to an embodiment of the present invention. [Main component symbol description] 10 wafer 11 electrode terminal 12 active surface 20 wafer carrier 30 pick-and-place nozzle 31 probe 32 vacuum suction hole 40 source region 11 200929396 51 die bonding region 52 die bonding region 53 die bonding region 61 moving path 62 Moving path 63 moving path 70 shared path 80 wafer cutting tape
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