JP2002076068A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reduction of a production yield due to defective chips in MTCP ICs. SOLUTION: This manufacturing method of a MTCP IC comprises a process of bonding inner leads to a tape carrier, an inspection process of inspecting plural chips whose inner leads have been bonded, a failure area cut-off process of cutting off the area with which a failure chip on the tape carrier is connected, and a good chip unit connection process connecting a good chip unit mechanically and electrically with a hole which is made by cutting off the failure chip on the tape carrier. In this case, chip-exchange pads are formed in advance on the top surface and under surface of the chip-connection area of the tape carrier. By aligning the chip-exchange pads on the top surface of the tape carrier with the chip-exchange pads on the under surface of a good chip unit, and soldering them, attachment of the good chip unit is achieved. In this manner, since an MTCP IC in total can be rescued by exchanging a defective chip with a good chip unit, the reduction of a production yield due to defective chips can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology for mounting a plurality of semiconductor chips on which a semiconductor integrated circuit including a semiconductor element is fabricated. Technology.

[0002]

2. Description of the Related Art A plurality of semiconductor integrated circuit devices (hereinafter, referred to as ICs) each having a tape carrier package (hereinafter, referred to as TCP) are rectangular as conventional memory modules which meet a demand for an increase in storage capacity. Some are mounted side by side on a module substrate formed in a flat plate shape.

[0003] As an example describing the technology for mounting TCP on a board, see "Practical Course VLSI Packaging Technology (1)", published on May 31, 1993, Nikkei BP, p.
67 to P272.

[0004]

However, in a memory module in which a plurality of ICs each having TCP (hereinafter referred to as TCP ICs) are mounted side by side on a module substrate, each TCP / IC is mounted on the module substrate. Since electric wirings that connect each other are laid at a plurality of locations, there is a limit in improving the mounting density on the module substrate.

Therefore, the present inventor has referred to a plurality of semiconductor chips (hereinafter, referred to as chips) in which a memory is built as T.
A memory module in which the multi-chip TCP (hereinafter, referred to as MTCP) is mounted on a module substrate while being electrically connected (cooperated) with each other while being mechanically connected side by side to the tape carrier of the CP. I thought. That is, according to the memory module using the MTCP, the conventional TCP / IC
In the memory module, a plurality of electric wiring laying regions for connecting TCP / ICs can be omitted, so that the mounting density can be greatly improved.

However, the MTCP has a problem in that if at least one of the plurality of chips has a defective product, the entire MTCP becomes a defective product, so that the manufacturing yield is extremely reduced. Revealed by the inventor.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent a decrease in manufacturing yield due to the presence of a defective product.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a method of manufacturing a semiconductor device includes an inspection step of inspecting a plurality of semiconductor chips mechanically and electrically connected to a tape carrier, and a step of inspecting a region of the tape carrier to which a defective semiconductor chip is connected. The method includes a step of punching out a defective portion to be punched out, and a step of mechanically and electrically connecting a non-defective product piece to a defective chip punching hole of the tape carrier.

According to the above-mentioned means, when a defective product is found in a plurality of semiconductor chips connected to the tape carrier, a defective portion of the tape carrier is punched out and replaced with a non-defective product. Since the entire tape carrier package in which the individual semiconductor chips are mechanically and electrically connected can be saved, it is possible to prevent a reduction in the manufacturing yield due to the presence of a defective semiconductor chip.

[0012]

FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 et seq. Show the respective steps.

In the present embodiment, the method of manufacturing a semiconductor device according to the present invention is applied to a memory device used in a memory module.
IC with TCP (hereinafter referred to as MTCP IC)
And has the flow shown in FIG. Hereinafter, the method of manufacturing the MTCP / IC according to the present embodiment will be described with reference to the flow of FIG.

As shown in FIG. 1, MTCP · I
In the method of manufacturing C, a chip 1 (see FIG. 3 and subsequent figures) is prepared in a chip preparation step, and a tape carrier 2 shown in FIG. 2 is prepared in a tape carrier preparation step.

The chip 1 is manufactured by forming a memory as a semiconductor integrated circuit on the active area side in the state of a semiconductor wafer in a pre-process of so-called IC manufacturing, and dividing it into a square flat plate shape in a dicing process. The surface of the chip 1 on the active area side is covered with a passivation film (not shown), and a plurality of electrode pads (not shown) are exposed in openings formed in the passivation film. Is formed. Bumps (protrusion electrodes, bumps) 1a are respectively provided on the plurality of electrode pads in a bumping step. In addition,
As shown in FIG. 1, when no bump is formed on the chip, the chip is supplied to the inner lead bonding step without going through the bumping step.

As shown in FIG. 2, the tape carrier 2 is made of TAB used in the method of manufacturing a TCP / IC.
(Tape automated bonding) It is equivalent to a tape. The same pattern is repeated in the tape carrier 2 in the longitudinal direction. The tape carrier 2 includes a carrier body 3 in which an insulating resin such as polyimide is used and the same pattern is integrally formed in a tape shape that is continuous in the longitudinal direction. Both ends of the carrier body 3 in the width direction are square. The perforations 4 formed in a small hole shape are arranged in a row in the longitudinal direction. In the middle part of the carrier body 3, window holes 5 formed in a long hole shape are opened at regular intervals in the longitudinal direction.

A plurality of inner leads 6 are laid at the position of each window hole 5 on one side main surface (hereinafter referred to as the upper surface) of the carrier body 3, and the tip of each inner lead 6 is provided at the window hole 5. It is projected to. Window hole 5 for each inner lead 6
On the opposite side, the outer leads 7 are connected in series, respectively, and the inner leads 6 and the outer leads 7 that are connected to each other are mechanically and electrically integrated. The group of inner leads 6 and the group of outer leads 7 are formed using a metal material having good conductivity, such as copper or gold. The inner lead 6 group and the outer lead 7 group can be formed by a method of patterning a copper foil or a gold foil fixed to the carrier body 3 by a fixing means such as welding or bonding by lithography and etching, or by lithography on the carrier body 3. There is a method of selectively performing a gold plating treatment by a treatment.

At the end of the outer lead 7 opposite to the inner lead 6, a chip replacement pad 8 is formed in the shape of a rectangular flat plate, and between the chip replacement pads 8 of the adjacent outer leads 7, 7, an electric connection is provided. Connected. Inner lead 6 and chip replacement pad 8 in outer lead 7
A through-hole conductor 9 is formed through the carrier body 3 on the lower surface side. The lower surface side chip replacement pad 8A is formed on the lower surface of the carrier body 3 in a rectangular flat plate shape so as to correspond to the upper surface side chip replacement pad 8, and the lower surface side chip replacement pad 8A is formed with a through-hole conductor 9 Through the outer lead 7. An insulating film 10 using an insulating material such as a solder resist is applied to the upper and lower surfaces of the carrier body 3 so as to cover the inner leads 6 and the outer leads 7, respectively. However, the insulating film 10 is in a state where the upper and lower chip replacement pads 8 and 8A are exposed.

Chip replacement pad 8 for each window hole 5
Positioning holes 11 are provided at the four outer corners of the group.
And an insulating film 10, each of which is formed so as to penetrate therethrough. As shown by imaginary lines in FIG. It passes through the center of the group.

The tape carrier 2 configured as described above
Is mechanically and electrically connected in the inner lead bonding step shown in FIG. That is, as shown in FIG.
The chip 1 is disposed on the upper surface of the tape carrier 2 such that the bumps 1a are aligned with the respective inner leads 6 and bonded by an adhesive layer 13 to be mechanically connected, and the tip of the inner leads 6 is connected to the bump 1a. Bonding tool (not shown) for inner lead bonding equipment
Thermocompression bonding.

Thereafter, in the appearance inspection step shown in FIG. 1, the appearance of the tape carrier 2 is inspected for the inner lead bonding portion of the chip 1 and the like. That is,
An appearance inspection is performed to determine whether the inner leads 6 are properly bonded to the predetermined bumps 1a.

When the appearance inspection is completed, in the inner lead portion resin coating / curing step shown in FIG.
As shown in FIG. 5, the inner lead 6 group is resin-sealed by the resin sealing portion 14 by potting an insulating material such as an elastomer or silicon rubber into each window hole 5 of the tape carrier 2. You.

As shown in FIG. 1, the resin sealing portion 1
In the tape cutting step, the tape carrier 2 on which the tapes 4 are formed is composed of a plurality of MTCP ICs 1
Each assembly 15 is cut. That is, in the present embodiment, as shown in FIG.
And the MTCP / IC assembly 15 having one as a unit, the carrier body 3 is composed of the chips 1 at both ends of the four chips 1,
1 are sequentially manufactured by being cut transversely outside each of the rows of the chip replacement pads 8 in 1.

As shown in FIG. 1, MTCP · I
C assembly 15 is used in the open / short test process.
It is inspected for open or short defects.
If an open defect or a short defect is found, the process is sent to a defective portion punching step. If no open defect or a short defect is found, the MT is sent.
The CP / IC assembly 15 is sent to a burn-in process.

In the electrical characteristics test step, the electrical characteristics test is simultaneously performed on the four chips 1 of the MTCP / IC assembly 15 on which the burn-in has been performed. In the electrical characteristic test, when a defect is found, it is sent to a defective portion punching step, and when no defect is found, it is sent to a visual inspection step.

In the appearance inspection step, the MTCP / IC assembly 15 in which an appearance defect is found is sent to a defective portion punching step, and the MTCP / IC assembly 15 in which no defect is found is sent to an outer shape cutting step.

Here, the step of punching out a defective portion and the step of separating non-defective products will be described.

MT sent to the defective portion punching process
As shown in FIG. 6, a defective chip punching hole 16 is formed in the CP / IC assembly 15 by punching a region where the defective chip 1 is mounted inside the four alignment holes 11. Be established. In the embodiment shown in FIG. 6, a defective chip punching hole 16 is formed in the second region from the left side of the MTCP / IC assembly 15. Carrier body 3 of MTCP / IC assembly 15
The upper surface side chip replacement pad 8 and the lower surface side chip replacement pad 8A are arranged on the upper surface and the lower surface of the edge of the opening of the chip punching hole 16 in FIG.

As shown in FIG. 1, the MTCP / IC assembly 15 in which a defective chip punching hole 16 has been punched out
Is sent to the non-defective item sorting process. In the non-defective item setting step, non-defective item pieces 17 shown in FIG. 7 are sent.

As shown in FIG. 7, non-defective pieces 17
Are formed in a similar sheet shape larger than the defective chip punching hole 16, and the alignment holes 11 are opened at the four corners of the non-defective piece 17 in the carrier body 3. That is, the non-defective piece 17 is M
This is a substantially square sheet obtained by punching the non-defective chip mounting area in the TCP / IC assembly 15 outside the four alignment holes 11.

As shown in FIGS. 7 and 8, in the non-defective item attaching step, the non-defective item 17 is mechanically and electrically connected to the defective chip punching hole 16. That is, the positioning pins 18 (see FIG. 7) are inserted into at least two positioning holes 11 outside the defective chip punching holes 16 of the MTCP / IC assembly 15, and the non-defective pieces 17 are inserted into the positioning pins 18. When the alignment hole 11 is inserted, the non-defective piece 17 is placed in each of the upper surface side chip replacement pads 8 arranged on the edge of the opening of the defective chip punching hole 16.
Each of the lower surface side chip replacement pads 8A arranged on the outer peripheral edge portion of each of them is aligned. When the reflow soldering process is performed in this state, as shown in FIG. 8, the upper surface side chip replacement pad 8 and the lower surface side chip replacement pad 8A are soldered by the soldering portion 19. Therefore, the good chip 1 of the good piece 17 is MT
It is in a state of being mechanically and electrically connected to the CP / IC assembly 15. In addition, as a solder material, a lead-tin solder, a silver solder, a gold solder, or the like can be used.

As described above, the MTCP / IC assembly 15 in which the non-defective product pieces 17 are aligned with the defective chip punching holes 16 and are mechanically and electrically connected, as shown in FIG. Good quality test piece 17
The electrical characteristics test is simultaneously performed on four chips 1 including the chip 1 mounted on the chip. In the electrical characteristics test, the MTCP / IC assembly 15 in which a defect is found is sent again to the defective portion punching step, and the defective chip area is replaced with a good piece. MT for which no defect was found
The CP / IC assembly 15 is sent to a visual inspection process.

In the appearance inspection step, the MTCP / IC assembly 15 in which the appearance defect has been found is sent again to the defective part punching step, and the defective chip area is replaced with a good piece. On the other hand, the MTCP / IC assembly 15 in which no defect is found is sent to the outer shape cutting step.

The unnecessary portion of the carrier main body 3 is cut off from the MTCP / IC assembly 15 sent to the outer shape cutting step, so that the MTCP / IC 20 is formed as shown in FIG. That is, the carrier body 3 of the MTCP / IC assembly 15 is cut into a rectangular shape near the outside of the four chips 1.

As shown in FIG. 1, the MTCP / IC 20 manufactured by the cutting in the outer shape cutting step is stored in the in-process transfer tray and supplied to the module mounting step.

According to the above embodiment, the following effects can be obtained.

1) When a defective chip is found in the MTCP / IC assembly, a defective portion of the tape carrier is punched out and replaced with a good piece.
Since the entire MTCP / IC assembly can be saved, it is possible to prevent a reduction in the manufacturing yield of the MTCP / IC due to the presence of a defective chip.

2) According to the above 1), it is possible to manufacture an MTCP / IC without using a chip (so-called KGD or WPP) which is previously guaranteed to be a non-defective product. MTCP using chip
The manufacturing cost can be reduced as compared with the case of manufacturing an IC.

3) According to the above 1), the MTCP / IC can be manufactured using chips in the early generations having a relatively low yield, so that a product strategy can be easily established from the beginning of the generation.

4) According to the above 1), 2) and 3), MTCP
・ IC manufacturing cost can be significantly reduced.

5) By manufacturing the MTCP / IC and mounting it on the module substrate, each TCP / IC is compared with a case where a plurality of TCP / ICs are mounted on the module substrate.
Since the laying area of the electrical wiring for connecting the two can be omitted, the mounting density of the memory module can be increased, and the storage capacity of the memory module can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. Needless to say, there is.

For example, the MTCP • IC is not limited to being constituted by four chips, but can be constituted by two or more chips.

The alignment between the good individual piece and the defective chip punching hole is not limited to the alignment using the alignment hole, but may be performed by a method such as an image recognition method using a chip replacement pad.

The means for mechanically and electrically connecting the chip replacement pad of the non-defective product piece and the chip replacement pad of the defective chip punching hole is not limited to the use of the reflow soldering process. A thermocompression bonding method using a crystal layer or a gold-tin eutectic layer, a bonding method using a silver paste or an anisotropic conductive film, or the like may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the method of manufacturing the MTCP / IC used in the memory module, which is the application field as the background, has been described. However, the present invention can be applied to other manufacturing methods of semiconductor devices.

[0047]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

When a defective product is found in a plurality of semiconductor chips connected to the tape carrier, a defective portion of the tape carrier is punched out and replaced with a non-defective product, whereby the plurality of semiconductor chips are mechanically removed. In addition, since the entire electrically connected tape carrier package can be saved, a decrease in manufacturing yield due to the presence of a defective semiconductor chip can be prevented.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B show a tape carrier, wherein FIG. 2A is a partially omitted plan view, and FIG. 2B is a front sectional view taken along line bb of FIG.

FIG. 3 shows a state after inner lead bonding;
(A) is a partially omitted plan view, and (b) is a front sectional view taken along line bb of (a).

4A and 4B show a state after resin sealing, in which FIG. 4A is a partially omitted plan view, and FIG. 4B is a front sectional view taken along line bb of FIG.

FIG. 5 is a partially omitted plan view showing a state after the tape is cut.

6A and 6B show a state after punching out a defective portion, in which FIG. 6A is a partially omitted plan view, and FIG. 6B is a front sectional view taken along line bb of FIG.

FIGS. 7A and 7B show a non-defective item separating step, in which FIG. 7A is a partially omitted plan view, and FIG. 7B is a front sectional view taken along line bb of FIG.

FIGS. 8A and 8B show a state after the non-defective products are separated, in which FIG. 8A is a partially omitted plan view and FIG. 8B is a front sectional view taken along line bb of FIG.

9A and 9B show a state after the outer shape is cut, and FIG. 9A is a partially omitted plan view, and FIG. 9B is a front sectional view taken along line bb of FIG. 9A.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip (semiconductor chip), 1a ... Bump, 2 ... Tape carrier, 3 ... Carrier main body, 4 ... Perforation, 5 ... Window hole, 6 ... Inner lead, 7 ... Outer lead,
8, 8A: pad for chip replacement, 9: through-hole conductor, 10: insulating film, 11: alignment hole, 12: frame line,
13: adhesive layer, 14: resin sealing portion, 15: MTCP
IC assembly, 16: defective chip punching hole, 17: non-defective product piece, 18: positioning pin, 19: soldering part, 20 ...
MTCP IC (semiconductor device).

Continued on the front page (72) Inventor Seiichiro Tsukui 1-1 Nishiyokote-cho, Takasaki City, Gunma Prefecture Inside Hitachi Eastern Semiconductor Co., Ltd. (72) Inventor Kouji Nagaoka 1-1, Nishiyokote-cho, Takasaki City, Gunma Prefecture Eastern Hitachi Semiconductor Corporation (72) Inventor Jun Nakamura 1-1, Nishiyokote-cho, Takasaki City, Gunma Prefecture Inside Hitachi East Semiconductor Semiconductor Co., Ltd. (72) Inventor Toshio Kanno 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor Company, Ltd. F-term (reference) 5F044 KK09 MM48

Claims (5)

[Claims] An inspection step of inspecting a plurality of semiconductor chips mechanically and electrically connected to a tape carrier;
A defective portion punching step of punching out a region where a defective semiconductor chip is connected in the tape carrier, and a non-defective individual piece attaching step of mechanically and electrically connecting non-defective individual pieces to a defective chip punching hole of the tape carrier. A method of manufacturing a semiconductor device. 2. A chip replacement pad is formed in a connection area of the semiconductor chip of the tape carrier, and the non-defective product is mechanically and electrically connected to the tape carrier at the chip replacement pad. The method for manufacturing a semiconductor device according to claim 1, wherein: 3. The chip replacement pad is formed on an upper surface and a lower surface of the tape carrier, respectively, and the chip replacement pad on the upper surface side of the tape carrier is provided with the chip replacement pad on the lower surface side of the good piece. 3. The method according to claim 2, wherein the semiconductor device is mechanically and electrically connected. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said non-defective product pieces are reflow soldered to a tape carrier. 5. A positioning hole is formed in a connection region of the semiconductor chip of the tape carrier, and the non-defective piece is positioned in the defective chip punching hole by the positioning hole. A method for manufacturing a semiconductor device according to claim 1.