CN106158584A - A kind of slot type power device and preparation method thereof - Google Patents
A kind of slot type power device and preparation method thereof Download PDFInfo
- Publication number
- CN106158584A CN106158584A CN201510155117.1A CN201510155117A CN106158584A CN 106158584 A CN106158584 A CN 106158584A CN 201510155117 A CN201510155117 A CN 201510155117A CN 106158584 A CN106158584 A CN 106158584A
- Authority
- CN
- China
- Prior art keywords
- type
- injection zone
- shallow
- groove
- type injection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000002347 injection Methods 0.000 claims abstract description 70
- 239000007924 injection Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000000407 epitaxy Methods 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000009825 accumulation Methods 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention discloses a kind of slot type power device and preparation method thereof, this manufacture method includes: form N-type epitaxy layer on substrate, and N-type epitaxy layer performs etching formation groove；In groove, implanting p-type ion forms deep p-type injection zone, and fills dielectric in groove；Replace implanting p-type ion and N-type ion in non-groove region, N-type epitaxy layer surface, form shallow p-type injection zone and shallow n-type injection zone.The method is combined with shallow p-type injection zone and shallow n-type injection zone by using deep p-type injection zone, shallow n-type injection zone prevents negative charge in oxide layer from forming hole inversion layer on partial-pressure structure surface, shallow p-type injection zone reduces the electric field spike that the electron accumulation layer that in oxide layer, positive charge is formed is formed on partial-pressure structure surface, the combination of above-mentioned injection zone eliminates the impact on partial-pressure structure of the electric field of partial-pressure structure surface accumulation, improves the Performance And Reliability of device.
Description
Technical field
The invention belongs to semiconductor chip fabrication process technical field, be specifically related to a kind of groove-shaped
Power device and preparation method thereof.
Background technology
The most important performance of power device blocks high pressure exactly, and device can be at PN through design
Knot, Metals-semiconductor contacts, the depletion layer at MOS interface bears high pressure, along with powering up outward
The increase of pressure, depletion layer electric field intensity also can increase, and eventually exceeds material limits and occurs that snowslide is hit
Wear.Increase in device edge depletion region electric field curvature, electric field ratio die internal can be caused big,
During voltage raises, can there is avalanche breakdown early than die internal in die edge, in order to
The performance of bigization device, needs to design partial-pressure structure at device edge, reduces active area (cellular
District) curvature of edge PN junction, make depletion layer horizontal expansion, strengthen the resistance to pressure energy of horizontal direction
Power, makes the edge of device and inside puncture simultaneously.Cut-off ring is in partial-pressure structure and scribe line
Between region, it is distributed in the outermost of chip, at the device that high reliability request and module encapsulate
On be indispensable.
Field limiting ring technology is one of partial-pressure structure the most commonly used in current power device.It
Technique very simple, can diffuse to form together with active area, processing step need not be increased.
Main knot all can have influence on breakdown potential with the number of the spacing of field limiting ring, junction depth, the width of ring and ring
The size of pressure.If it is suitable that spacing is chosen so that the electric field intensity that main knot is tied with ring reaches simultaneously
To critical breakdown strength, then can obtain the highest breakdown voltage.Generally breakdown voltage
Increase along with the increase of number of ring, but the most linearly increasing.The number of ring is the most, takies
Chip area is the biggest, is considered as ring number and breakdown voltage size during design.
The most conventional field limiting ring structure is as it is shown in figure 1, the shortcoming of this structure is Surface Oxygen
Device surface electromotive force can be produced a very large impact by the interface charge changing layer, affects dividing potential drop effect, makes
Breakdown voltage reduces.
Summary of the invention
For defect of the prior art, the invention provides a kind of slot type power device and
Manufacture method, this method eliminatess the electric charge shadow to partial-pressure structure in the accumulation of dividing potential drop region surface
Ring, improve the Performance And Reliability of device.
First aspect, the present invention provides the manufacture method of a kind of slot type power device, including:
Substrate is formed N-type epitaxy layer, and described N-type epitaxy layer is performed etching formation ditch
Groove；
In described groove, implanting p-type ion forms deep p-type injection zone, and in described groove
Fill dielectric；
Implanting p-type ion and N-type ion is replaced in non-groove region, described N-type epitaxy layer surface,
Form shallow p-type injection zone and shallow n-type injection zone；
Optionally, described replace in non-groove region, described N-type epitaxy layer surface implanting p-type from
Son and N-type ion, including:
Implanting p-type ion or injection on described N-type epitaxy layer surface between described adjacent trenches
N-type ion.
Optionally, described deep p-type injection zone injects the dosage of described p-type ion more than described shallow
P-type injection zone injects the dosage of described p-type ion.
Optionally, described deep p-type injection zone injects the dosage of described p-type ion more than described shallow
N-type injection zone injects the dosage of described N-type ion.
Optionally, after in described groove, implanting p-type ion forms deep p-type injection zone, and
Before filling dielectric region in described groove, described method also includes:
The structure forming deep p-type injection zone is made annealing treatment.
Optionally, the quantity of described deep p-type injection zone is more than or equal to 3.
Optionally, in described groove, the surface of dielectric is neat with the surface of described N-type epitaxy layer
Flat.
Optionally, the width of described deep p-type injection zone less than described shallow n-type injection zone and
The width of described shallow p-type injection zone.
Optionally, the width of described groove is 1-2um, and the degree of depth is less than or equal to 10um；
The degree of depth of described groove is less than the degree of depth of described N-type epitaxy layer.
Optionally, described substrate is silicon wafer.
Second aspect, present invention also offers a kind of slot type power device, described groove-shaped merit
Rate device is to use the manufacture method described in any of the above-described item to obtain.
As shown from the above technical solution, the present invention provide a kind of slot type power device and system
Making method, the method is noted with shallow p-type injection zone and shallow n-type by using deep p-type injection zone
Entering region to combine, wherein, shallow n-type injection zone prevents in oxide layer negative charge at partial-pressure structure
Surface forms hole inversion layer, and shallow p-type injection zone reduces in oxide layer positive charge in dividing potential drop
The electric field spike that the electron accumulation layer that body structure surface is formed is formed, the combination of above-mentioned injection zone disappears
The electric field impact on partial-pressure structure except the accumulation of partial-pressure structure surface, it is possible to play potential dividing ring
Effect, improves the Performance And Reliability of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of field limiting ring in prior art；
A kind of slot type power device manufacture method that Fig. 2 provides for one embodiment of the invention
Schematic flow sheet；
A kind of slot type power device system that Fig. 3 A to Fig. 3 C provides for one embodiment of the invention
Make the structural representation of process；
The position view of the channel-type power device that Fig. 4 provides for one embodiment of the invention；
The channel-type power device that Fig. 5 provides for one embodiment of the invention section view in B-B direction
Figure；
Reference:
Wherein 11, silicon wafer；21, N-type epitaxy layer；31, p-type injection zone；41、N
Type injection zone；1, silicon wafer；2, N-type epitaxy layer；3, deep p-type injection zone；4、
Dielectric；5, shallow n-type injection zone；6, shallow p-type injection zone；101, dicing lane
Region；102, cut-off ring region territory；103, dividing potential drop region；104, active area.
Detailed description of the invention
Below in conjunction with the accompanying drawings, the detailed description of the invention of invention is further described.Hereinafter implement
Example is only used for clearly illustrating technical scheme, and can not limit this with this
Bright protection domain.
Fig. 2 shows the manufacture method of a kind of slot type power device that the embodiment of the present invention provides
Schematic flow sheet, as in figure 2 it is shown, this manufacture method comprises the steps:
201, on substrate, form N-type epitaxy layer, and described N-type epitaxy layer is performed etching shape
Become groove；
Concrete, described substrate is silicon wafer.
The spacing of described adjacent trenches is identical or different.The width of described groove is 1-2um, deeply
Degree is less than or equal to 10um, and the degree of depth of described groove is less than the degree of depth of described N-type epitaxy layer.
202, in described groove, implanting p-type ion forms deep p-type injection zone, and described
Dielectric is filled in groove；
Concrete, in described groove, the surface of dielectric is neat with the surface of described N-type epitaxy layer
Flat.
203, implanting p-type ion and N-type are replaced in non-groove region, described N-type epitaxy layer surface
Ion, forms shallow p-type injection zone and shallow n-type injection zone.
Described replace implanting p-type ion and N-type in non-groove region, described N-type epitaxy layer surface
Ion, including:
Implanting p-type ion or note on described N-type epitaxy layer surface between described adjacent trenches
Enter N-type ion.
Unlike the prior art, the method is by using deep p-type injection zone and shallow p-type injection region
Territory and shallow n-type injection zone combine, and wherein, shallow n-type injection zone prevents negative electricity in oxide layer
Lotus forms hole inversion layer on partial-pressure structure surface, and shallow p-type injection zone reduces in oxide layer
The electric field spike that the electron accumulation layer that positive charge is formed on partial-pressure structure surface is formed, above-mentioned injection
The combination in region eliminates the impact on partial-pressure structure of the electric field of partial-pressure structure surface accumulation, it is possible to
Play the effect of potential dividing ring, improve the Performance And Reliability of device.
Wherein, energy and the dosage of the described p-type ion of deep p-type injection zone injection is more than described shallow
P-type injection zone injects energy and the dosage of described p-type ion.Being similar to, described deep p-type is noted
The energy and the dosage that enter the described p-type ion of region injection inject more than described shallow n-type injection zone
The energy of described N-type ion and dosage.
In order to make the intensity of electric field weaken step by step, therefore the quantity of described deep p-type injection zone is more than
Equal to 3.
For the p-type ion junction depth injected in making p-type injection zone, in described groove, inject P
After type ion forms deep p-type injection zone, and in described groove, fill dielectric region
Before, the structure forming deep p-type injection zone is made annealing treatment.
In order to prevent two adjacent deep p-type injection zone distances too near, causing connecting, impact should
Device loses the effect of potential dividing ring, the Performance And Reliability of reduction device, therefore described deep p-type
The width of injection zone is less than described shallow n-type injection zone and the width of described shallow p-type injection zone
Degree.
Illustrating using silicon wafer as substrate below, the manufacture method of above-mentioned device specifically includes
Following steps:
301, on silicon wafer 1, form N-type epitaxy layer 2, and described N-type epitaxy layer is carved
Erosion forms groove；
As shown in Figure 3A, the spacing of described adjacent trenches is identical or different.The width of described groove
Degree is 1-2um, and the degree of depth is not more than 10um.
The selection of backing material depends primarily on the following aspects: architectural characteristic, interfacial characteristics,
Chemical stability, thermal property, electric conductivity, optical property and mechanical performance, select lining
Need to consider above-mentioned several aspect when the end and corresponding epitaxial layer.Owing to silicon is the good conductor of heat,
The heat conductivility of device is preferable, thus reaches the purpose extending device lifetime, therefore the present embodiment
In illustrate as a example by monocrystalline substrate, it should be understood that, backing material is except can
Being beyond silicon (Si), it is also possible to be carborundum (SiC), gallium nitride (GaN) or
GaAs (GaAS) etc..
302, (not shown) with photoresist is made as mask, to inject P in described groove
Type ion forms deep p-type injection zone 3, and fills dielectric 4 in described groove, such as figure
Shown in 3B.
Wherein dielectric 4 can be Al2O3, TiO2, ZrO2, MgO, HFO2, Ta2O5,
In in Si3N4, AlN, SINx, SiNO, SiO, SiO2, SiC, SiCNx material one
Or it is multiple；Wherein, x is positive integer.
303, make with photoresist that (not shown) is as mask, in described N-type epitaxy layer
2 non-groove region, surfaces replace implanting p-type ion and N-type ion, form shallow p-type injection region
Territory 6 and shallow n-type injection zone 5, as shown in Figure 3 C.
Described replace implanting p-type ion and N-type in non-groove region, described N-type epitaxy layer surface
Ion, including:
On described N-type epitaxy layer surface between described adjacent trenches implanting p-type ion or
Inject N-type ion.
Utilize slot type power device dividing potential drop region 103 and other region that said method formed
The position of (including street area 101, cut-off ring region territory 102 and active area 104) shows
Being intended to as shown in Figure 4, wherein the sectional view in A-A direction is as shown in Figure 3 C；In B-B side
To sectional view as shown in Figure 5
The embodiment of the present invention additionally provides what manufacture method based on said method embodiment obtained
Slot type power device.
In the description of the present invention, illustrate a large amount of detail.It is to be appreciated, however, that this
Inventive embodiment can be put into practice in the case of not having these details.In some instances,
It is not shown specifically known method, structure and technology, in order to the not fuzzy reason to this specification
Solve.
It is last it is noted that various embodiments above is only in order to illustrate technical scheme,
It is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments,
It will be understood by those within the art that: it still can be to described in foregoing embodiments
Technical scheme modify, or the most some or all of technical characteristic carried out equivalent replace
Change；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the present invention each
The scope of embodiment technical scheme, it all should be contained in the claim of the present invention and description
In the middle of scope.
Claims (10)
1. the manufacture method of a slot type power device, it is characterised in that including:
Substrate is formed N-type epitaxy layer, and described N-type epitaxy layer is performed etching formation ditch
Groove；
In described groove, implanting p-type ion forms deep p-type injection zone, and in described groove
Fill dielectric；
Implanting p-type ion and N-type ion is replaced in non-groove region, described N-type epitaxy layer surface,
Form shallow p-type injection zone and shallow n-type injection zone.
Method the most according to claim 1, it is characterised in that described outside described N-type
Prolong a layer non-groove region, surface and replace implanting p-type ion and N-type ion, including:
Implanting p-type ion or note on described N-type epitaxy layer surface between described adjacent trenches
Enter N-type ion.
Method the most according to claim 1, it is characterised in that described deep p-type injection region
Territory is injected the dosage of described p-type ion and is injected described p-type ion more than described shallow p-type injection zone
Dosage and described shallow n-type injection zone inject described N-type ion dosage.
Method the most according to claim 1, it is characterised in that inject in described groove
After p-type ion forms deep p-type injection zone, and in described groove, fill dielectric region
Before, described method also includes:
The structure forming deep p-type injection zone is made annealing treatment.
Method the most according to claim 1, it is characterised in that described deep p-type injection region
The quantity in territory is more than or equal to 3.
Method the most according to claim 1, it is characterised in that in described groove, insulation is situated between
The surface of matter flushes with the surface of described N-type epitaxy layer.
Method the most according to claim 2, it is characterised in that described deep p-type injection region
The width in territory is less than described shallow n-type injection zone and the width of described shallow p-type injection zone.
Method the most according to claim 1, it is characterised in that the width of described groove is
1-2um, the degree of depth is less than or equal to 10um；
The degree of depth of described groove is less than the degree of depth of described N-type epitaxy layer.
Method the most according to claim 1, it is characterised in that described substrate is silicon wafer.
10. a slot type power device, it is characterised in that described slot type power device is
The manufacture method according to any one of claim 1-9 is used to obtain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510155117.1A CN106158584A (en) | 2015-04-02 | 2015-04-02 | A kind of slot type power device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510155117.1A CN106158584A (en) | 2015-04-02 | 2015-04-02 | A kind of slot type power device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106158584A true CN106158584A (en) | 2016-11-23 |
Family
ID=57338073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510155117.1A Pending CN106158584A (en) | 2015-04-02 | 2015-04-02 | A kind of slot type power device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106158584A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
| CN107658213A (en) * | 2017-09-01 | 2018-02-02 | 中国科学院微电子研究所 | A kind of silicon carbide power device terminal and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| CN102214581A (en) * | 2011-05-26 | 2011-10-12 | 上海先进半导体制造股份有限公司 | Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device |
| CN102214678A (en) * | 2011-05-18 | 2011-10-12 | 电子科技大学 | 3D-RESURF junction terminal structure of power semiconductor |
| WO2012049872A1 (en) * | 2010-10-15 | 2012-04-19 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
-
2015
- 2015-04-02 CN CN201510155117.1A patent/CN106158584A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| WO2012049872A1 (en) * | 2010-10-15 | 2012-04-19 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
| CN102214678A (en) * | 2011-05-18 | 2011-10-12 | 电子科技大学 | 3D-RESURF junction terminal structure of power semiconductor |
| CN102214581A (en) * | 2011-05-26 | 2011-10-12 | 上海先进半导体制造股份有限公司 | Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
| CN107658213A (en) * | 2017-09-01 | 2018-02-02 | 中国科学院微电子研究所 | A kind of silicon carbide power device terminal and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4564510B2 (en) | Power semiconductor device | |
| CN105633168A (en) | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET | |
| CN105097914B (en) | Transverse diffusion metal oxide semiconductor device and its manufacture method | |
| KR102066310B1 (en) | Power Semiconductor Device | |
| CN102339861A (en) | Semiconductor device | |
| JP2010045245A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN104241376A (en) | Super junction structure, preparation method of super junction structure and semiconductor device | |
| KR20110108256A (en) | Semiconductor device and method of manufacturing the same | |
| CN104733301A (en) | Method for Producing a Semiconductor Device Having a Beveled Edge Termination | |
| CN103985746A (en) | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof | |
| CN105826360B (en) | Groove-shaped half super junction power device and preparation method thereof | |
| CN104347475B (en) | Edge termination structure with trench isolation regions | |
| CN113658999B (en) | Power semiconductor device with junction-free termination technology, manufacturing method and application | |
| CN106298479B (en) | A kind of the knot terminal expansion structure and its manufacturing method of power device | |
| CN103681817B (en) | IGBT device and preparation method thereof | |
| CN106356401A (en) | Field limiting ring terminal structure for power semiconductor device | |
| CN102867849A (en) | Fast recovery diode and manufacturing method thereof | |
| CN106158584A (en) | A kind of slot type power device and preparation method thereof | |
| CN206976353U (en) | A kind of channel-type semiconductor device for optimizing terminal structure | |
| EP2551910A1 (en) | Insulated gate semiconductor device with optimized breakdown voltage and manufacturing method thereof | |
| CN103872097A (en) | Power semiconductor device and method for manufacturing the same | |
| KR100902585B1 (en) | Trench gate mosfet and method for fabricating of the same | |
| CN105826195A (en) | Super junction power device and manufacturing method thereof | |
| CN107994067A (en) | The terminal structure and preparation method thereof of semiconductor power device, semiconductor power device | |
| US9029250B2 (en) | Method for producing semiconductor regions including impurities |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161123 |