CN106154737A - A kind of domain processing method reducing ESD risk - Google Patents
A kind of domain processing method reducing ESD risk Download PDFInfo
- Publication number
- CN106154737A CN106154737A CN201610510504.7A CN201610510504A CN106154737A CN 106154737 A CN106154737 A CN 106154737A CN 201610510504 A CN201610510504 A CN 201610510504A CN 106154737 A CN106154737 A CN 106154737A
- Authority
- CN
- China
- Prior art keywords
- mask plate
- esd
- implanted layer
- layer mask
- processing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention provides a kind of domain processing method reducing ESD risk, including: first step: obtain original implanted layer mask plate；Second step: select easily to occur in original implanted layer mask plate the graph edge of ESD effect；Third step: optimize original implanted layer mask plate for the graph edge that ESD effect easily occurs；4th step: the implanted layer mask plate after optimizing is performed optical near-correction and processes to obtain final implanted layer mask plate.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to microelectronics layout data optics correction field；More specifically
Say, the present invention relates to a kind of domain process side reducing ESD (Electro-Static Discharge, static discharge) risk
Method.
Background technology
Static discharge is the hazardness problem generally existed in semi-conductor industry, although the most extensive
Use material and the device of antistatic, still cannot be avoided static discharge and cause the destruction to material Yu product, especially anti-quiet
In the case of electricity measure is improved not, the most in transit etc..The quiet of mask plate it is frequently the problem that in chip manufacturing
Electrodisintegration (ESD Damage), the electrostatic breakdown of mask plate does not only result in scrapping of mask plate, more seriously covers owing to reforming
The prolongation of the production cycle that template causes.
In mask plate electrostatic breakdown, implanted layer mask plate ESD event probability is higher, owing to the mask plate of implanted layer is general
Use light field design (clear tone), and after logical operations, there is the design much not meeting rule, cause some
Special design configuration easily causes electrostatic discharges on mask plate.
The graphic material on implanted layer mask plate surface has crome metal (Cr) to form, due to conductive surface charge density with
The curvature of conductive surface is relevant, and radius of curvature is the least, and its charge density is the biggest, and the radius of curvature of conductor tip is the least, therefore its
Electric charge is the most intensive, and the electric field near tip is strong especially, is susceptible to point discharge phenomenon；Salient angle curvature on mask plate is relatively
Little, so being easily caused point effect.
When two conductor distance within the specific limits time and separate with certain medium, be formed for capacitor, normally
During voltage (or electric field intensity), electric capacity typically will not puncture, actually in the case of a certain fixing dielectric thickness, and electric capacity
Puncture there is dispersibility, generally characterize by average voltage breakdown (or average breakdown strength).Fixed breakdown voltage (or average
Breakdown strength), then may be made that the relation curve of an electric capacity and dielectric thickness.For this relation curve, at less thickness
In the range of, average breakdown strength reduces with the reduction of dielectric thickness, this is because weak spot (electrically conductive particles or hole in medium
Hole) impact increase caused with the reduction of thickness；And in bigger thickness range, the average breakdown strength of capacitor is with Jie
The increase of matter thickness and reduce, this is because along with the increase of thickness, pole plate fringe field inhomogeneities increases, it is possible to make to hit
Wearing region and transfer to edge from media interior, at this moment average breakdown strength is not determined by the character of medium.
On mask plate, the crome metal of bulk will form similar capacitor in the range of a certain distance, and at crome metal
Salient angle exist cause point effect, when field intensity reaches certain level, and the probability punctured increases sharply.
In order to avoid mask plate electrostatic discharges, have employed in mask plate manufacture and add not imaging (non-
Printing) measure or the method such as wire, but needs must be found to add not imaging wire before adding these secondary graphics
Graphic feature, quantify test owing to static discharge cannot be carried out figure, so being difficult to clearly require the district adding secondary graphics
Territory；Additionally add wire improper publication operation, and it is generally required to manually complete, too increase what mask plate was published undoubtedly
Workload.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can reduce
The domain processing method of ESD risk.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of domain processing method reducing ESD risk,
Including:
First step: obtain original implanted layer mask plate；
Second step: select easily to occur in original implanted layer mask plate the graph edge of ESD effect；
Third step: optimize original implanted layer mask plate for the graph edge that ESD effect easily occurs；
4th step: the implanted layer mask plate after optimizing is performed optical near-correction and processes to obtain final implanted layer
Mask plate.
Preferably, the figure of described original implanted layer mask plate uses light field design.
Preferably, distance implanted layer mask plate figure within is less than 1.2 times easily to occur the graph edge of ESD effect to include
Little design rule live width and projection length are less than the graph edge of 2 times of minimum design rule live widths.
Preferably, graph edge ESD effect easily occurring is re-entrant angle graph edge.
Preferably, in third step, carry out supplementary angle process to easily there is the graph edge of ESD effect.
Preferably, determine that supplementary angle processes the supplementary angle size used according to the figure length of side.
Preferably, the step that the graph edge of ESD effect easily occurs in the implanted layer mask plate that described selection is original is passed through
Calibre SVRF instrument realizes.
Preferably, the step of the described implanted layer mask plate original for the graph edge optimization that ESD effect easily occurs is passed through
Calibre SVRF instrument realizes.
The invention provides a kind of domain processing method that can reduce implanted layer mask plate ESD risk, the method based on
Existing domain handling process, to easily occurring the graphic structure of ESD event to be optimized, thus reach to optimize mask plate figure with
Reduce the result of ESD risk.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the stream of the domain processing method reducing ESD risk according to the preferred embodiment of the invention
Cheng Tu.
Fig. 2 to Fig. 5 schematically shows the domain processing method reducing ESD risk according to the preferred embodiment of the invention
A concrete example.
Fig. 6 to Figure 11 schematically shows the domain process side reducing ESD risk according to the preferred embodiment of the invention
Another concrete example of method.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
In implanted layer mask plate, often there is static discharge phenomenon, cause mask plate defect.In order to reduce what ESD occurred
Probability, is optimized process to original layout in domain processing procedure, makes final mask plate figure be formed and is unfavorable for that electrostatic is put
The graphic structure of electricity, reduces the risk that point effect punctures with electric capacity, thus reduces the generation of electrostatic breakdown.Wherein, at mask
In plate pattern treatment procedure, utilize the design margin of implanted layer mask plate, part easily occurs that the graphic structure of electrostatic effect enter
Row optimization processes, the mask plate figure that the figure after optimization obtains after optical near-correction (OPC) processes, and has both avoided straight
Angle graphic structure, adds again the media spacing of electrostatic generation area such that it is able to reduces point effect and occurs electric capacity to hit
The risk worn.
Fig. 1 schematically shows the stream of the domain processing method reducing ESD risk according to the preferred embodiment of the invention
Cheng Tu.
Specifically, as it is shown in figure 1, the domain processing method reducing ESD risk according to the preferred embodiment of the invention includes:
First step S1: obtain original implanted layer mask plate；
Preferably, the figure of described original implanted layer mask plate uses light field design.
Second step S2: select easily to occur in original implanted layer mask plate the graph edge of ESD effect；
Preferably, distance implanted layer mask plate figure within is less than 1.2 times easily to occur the graph edge of ESD effect to include
Little design rule live width and projection length are less than the graph edge of 2 times of minimum design rule live widths.
Preferably, graph edge ESD effect easily occurring is re-entrant angle graph edge.
Third step S3: optimize original implanted layer mask plate for the graph edge that ESD effect easily occurs；
Preferably, in third step S3, carry out supplementary angle process to easily there is the graph edge of ESD effect.And further
Preferably, determine that supplementary angle processes the supplementary angle size used according to the figure length of side.
4th step S4: the implanted layer mask plate after optimizing is performed optical near-correction and processes to obtain final injection
Layer mask plate.
Preferably, the implanted layer mask plate that described selection is original easily occurs step and the institute of the graph edge of ESD effect
State and optimize the step of original implanted layer mask plate by Calibre SVRF instrument in fact for the graph edge that ESD effect easily occurs
Existing.
Specifically, in the figure of implanted layer mask plate, commonly used light field design (clear tone), namely design
Figure is transmission region on mask plate, and the graphics field in addition to design configuration is details in a play not acted out on stage, but told through dialogues on mask plate, at mask plate
Upper formation crome metal.
From the principle of point discharge it will be seen that isolated conductor surface charge density have with the curvature of conductive surface
Closing, radius of curvature is the least, and its charge density is the biggest；It is convex that the figure re-entrant angle of implanted layer mask plate can form crome metal on mask plate
, owing to the curvature on salient angle summit is relatively small, there is point effect in angle, actual layout design generally uses orthogonal figure, also
I.e. graphics vertex becomes an angle of 90 degrees or 270 degree of angles；Figure re-entrant angle (corresponding mask in implanted layer optical near-correction processing procedure
Crome metal salient angle on plate) carry out pretreatment so that and the right angle of mask plate figure becomes " obtuse angle edge ", can reduce figure accordingly
Curvature, thus reduce the generation of point effect.
From the point of view of electric capacity punctures, when dielectric thickness is less than marginal value, what capacitor punctured averagely punctures strong
Degree is directly proportional to dielectric thickness, increases dielectric thickness and can advantageously reduce the risk that electric capacity punctures, implanted layer mask plate is sent out
The spacing of the crome metal of raw electrostatic effect is the least, commonly takes place in spacing close to design rule minimum feature, if therefore
Suitably increase its spacing, average breakdown strength can be improved, thus reduce the probability punctured.
It is the least that the figure that electrostatic breakdown occurs concentrates on spacing between crome metal, and there is the knot at diagonal angle, angle between figure
Structure, punctures and dielectric thickness relation according to point effect principle and electric capacity, by figure in optical near-correction processing procedure
Re-entrant angle (corresponding mask plate crome metal right angle) is passivated, and increases the spacing distance in space in figure, referring to figs. 2 to Fig. 5's
Concrete grammar is following (assuming that design rule minimum feature Wmin):
(1) input original implanted layer figure TGT0, select re-entrant angle limit therein (graph edge becomes 270 degree of angles) Ea, and select
Between Ea, space D 1 is less than 1.2*Wmin, projects length L1 and is less than 2*Wmin, obtain re-entrant angle graph edge Eb between Ea；
(2) obtain Eb according to step (1), select orthogonal with Eb and become 270 degree of angles graph edge Ec；
(3) judge the length of Eb, select length to obtain Eb1 more than or equal to the Eb of 3*Wmin, select length to be less than or equal to
The Eb of 3*Wmin obtains Eb2；
(4) right angle length of side E1 forming isosceles right triangle Ta, Ta at Eb1 Yu Ec common vertex is equal to Wmin,
The typical length of the right-angle side E2 that Eb2 Yu Ec apex forms isosceles right triangle Tb, Tb is 10nm；
(5) original layout figure TGT0 Yu Ta and Tb is carried out logical operations and obtain new figure TGT1；
TGT1=TGT0+ (Ta+Tb)
(6) TGG1 is carried out optical near-correction process, obtain final mask plate figure.
Implanted layer figure generally there are bigger design margin, say, that layout patterns carries out appropriateness adjustment can't
Impacting the performance of product itself, the present invention carries out local optimum to figure re-entrant angle, only has influence on the turning of partial graphical
Sphering result, does not the most affect real ion implanted regions, thus without affecting product key property.
As a example by a certain concrete resolution chart, compare the mask plate figure that the domain processing method of present invention employing obtains
(Fig. 8) with tradition domain processing method mask plate figure (Fig. 9), in the figure being susceptible to electrostatic effect, traditional method
Tip (crome metal salient angle on figure re-entrant angle or mask plate) through optimization process after formed 135 degree angles, its correspondence curvature change
Greatly, thus the generation of point effect can be reduced；In terms of capacitor angle, after improving, problem pattern mechanism mask plate figure
Shape live width adds 50%, namely the dielectric thickness of electric capacity substantially increases, and therefore its average disruptive field intensity increases, it is possible to reduces and sends out
The probability that raw electric capacity punctures.
Relatively this method analog result (Figure 10) and the analog result (Figure 11) of tradition domain processing method, after diagram optimizing
Ion implanted regions is not produced and significantly affect, thus without the performance affecting product device.
Implanted layer handled by this method uses light field design, as a example by the implanted layer figure shown in Fig. 6, selects to conform to
The figure re-entrant angle limit asked, then forms new layout patterns (Fig. 7) at nook, is that new layout patterns carries out optics with Fig. 7
Near-correction processes, and obtains final mask plate graphic diagram 8.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (8)
1. the domain processing method reducing ESD risk, it is characterised in that including:
First step: obtain original implanted layer mask plate；
Second step: select easily to occur in original implanted layer mask plate the graph edge of ESD effect；
Third step: optimize original implanted layer mask plate for the graph edge that ESD effect easily occurs；
4th step: the implanted layer mask plate after optimizing is performed optical near-correction and processes to obtain final implanted layer mask
Plate.
The domain processing method of reduction ESD risk the most according to claim 1, it is characterised in that described original injection
The figure of layer mask plate uses light field design.
The domain processing method of reduction ESD risk the most according to claim 1 and 2, it is characterised in that ESD effect easily occurs
The graph edge answered includes that the distance within implanted layer mask plate figure is less than 1.2 times of minimum design rule live widths and projection length
Graph edge less than 2 times of minimum design rule live widths.
The domain processing method of reduction ESD risk the most according to claim 1 and 2, it is characterised in that ESD effect easily occurs
The graph edge answered is re-entrant angle graph edge.
The domain processing method of reduction ESD risk the most according to claim 1 and 2, it is characterised in that at third step
In, carry out supplementary angle process to easily there is the graph edge of ESD effect.
The domain processing method of reduction ESD risk the most according to claim 5, it is characterised in that come according to the figure length of side
Determine that supplementary angle processes the supplementary angle size used.
The domain processing method of reduction ESD risk the most according to claim 1 and 2, it is characterised in that described selection is original
Implanted layer mask plate in easily occur the step of graph edge of ESD effect to be realized by CalibreSVRF instrument.
The domain processing method of reduction ESD risk the most according to claim 1 and 2, it is characterised in that described for easily sending out
The graph edge of raw ESD effect is optimized the step of original implanted layer mask plate and is realized by CalibreSVRF instrument.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610510504.7A CN106154737B (en) | 2016-06-30 | 2016-06-30 | A kind of domain processing method reducing ESD risk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610510504.7A CN106154737B (en) | 2016-06-30 | 2016-06-30 | A kind of domain processing method reducing ESD risk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106154737A true CN106154737A (en) | 2016-11-23 |
| CN106154737B CN106154737B (en) | 2019-10-25 |
Family
ID=57350827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610510504.7A Active CN106154737B (en) | 2016-06-30 | 2016-06-30 | A kind of domain processing method reducing ESD risk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106154737B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108646515A (en) * | 2018-04-27 | 2018-10-12 | 深圳市华星光电技术有限公司 | A kind of mask plate, array substrate |
| CN109085736A (en) * | 2018-09-10 | 2018-12-25 | 德淮半导体有限公司 | The production method of optical adjacent correction method and mask plate |
| CN109143775A (en) * | 2018-08-29 | 2019-01-04 | 上海华力集成电路制造有限公司 | The light mask image for reducing the method for light shield static discharge risk and its obtaining |
| CN111948900A (en) * | 2020-08-18 | 2020-11-17 | 上海华力微电子有限公司 | Method for identifying characteristic graph of layout |
| CN112631067A (en) * | 2020-12-25 | 2021-04-09 | 上海华力集成电路制造有限公司 | Mask plate graph OPC method, mask plate graph, mask plate and terminal equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050214654A1 (en) * | 2004-03-26 | 2005-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD-resistant photomask and method of preventing mask ESD damage |
| US7419748B1 (en) * | 2004-08-24 | 2008-09-02 | Integrated Device Technology, Inc. | Photomask with reduced electrostatic discharge defects |
| CN101598893A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | Tool prevents the light shield of electrostatic breakdown |
| CN104698736A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Processing method for avoiding photomask graph unit ESD phenomenon |
-
2016
- 2016-06-30 CN CN201610510504.7A patent/CN106154737B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050214654A1 (en) * | 2004-03-26 | 2005-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD-resistant photomask and method of preventing mask ESD damage |
| US7419748B1 (en) * | 2004-08-24 | 2008-09-02 | Integrated Device Technology, Inc. | Photomask with reduced electrostatic discharge defects |
| CN101598893A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | Tool prevents the light shield of electrostatic breakdown |
| CN104698736A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Processing method for avoiding photomask graph unit ESD phenomenon |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108646515A (en) * | 2018-04-27 | 2018-10-12 | 深圳市华星光电技术有限公司 | A kind of mask plate, array substrate |
| CN109143775A (en) * | 2018-08-29 | 2019-01-04 | 上海华力集成电路制造有限公司 | The light mask image for reducing the method for light shield static discharge risk and its obtaining |
| CN109085736A (en) * | 2018-09-10 | 2018-12-25 | 德淮半导体有限公司 | The production method of optical adjacent correction method and mask plate |
| CN111948900A (en) * | 2020-08-18 | 2020-11-17 | 上海华力微电子有限公司 | Method for identifying characteristic graph of layout |
| CN111948900B (en) * | 2020-08-18 | 2024-01-23 | 上海华力微电子有限公司 | Method for identifying characteristic pattern of layout |
| CN112631067A (en) * | 2020-12-25 | 2021-04-09 | 上海华力集成电路制造有限公司 | Mask plate graph OPC method, mask plate graph, mask plate and terminal equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106154737B (en) | 2019-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106154737A (en) | A kind of domain processing method reducing ESD risk | |
| JP5429869B2 (en) | Pattern inspection apparatus and method | |
| CN104903896B (en) | Design rule check | |
| CN102610606A (en) | Semiconductor device and its manufacturing method and optical proximity processing method | |
| CN103309150B (en) | Processing method for layout data | |
| CN103885282B (en) | A kind of wrong method of checking wrong report after reduction OPC amendments | |
| US8151222B2 (en) | Method for decomposing designed pattern layout and method for fabricating exposure mask using the same | |
| CN105093809B (en) | Enhance the optical adjacent correction method of lithographic process window | |
| CN105159026B (en) | The optics of area of grid closes on amendment verification method | |
| KR20080001438A (en) | Method of designing mask layout | |
| CN106919009A (en) | Figure preprocess method before optical near-correction | |
| CN110658696B (en) | Photoetching friendliness design checking method for disconnection hot spot | |
| JP4854319B2 (en) | Verification method of optical proximity correction using layout vs layout inspection method | |
| CN109143773B (en) | Pretreatment method before optical proximity correction | |
| JP2019011972A (en) | Pattern edge detection method | |
| CN106094422A (en) | A kind of simplify the method for mask graph after OPC | |
| CN105807555A (en) | Method for improving OPC (optical proximity correction) precision | |
| JP5533092B2 (en) | Method for identifying data point distribution region on coordinate plane and identification program thereof | |
| CN100592494C (en) | Method for correcting layout design for correcting metallic coating of contact hole | |
| US10990000B2 (en) | Photolithography plate and mask correction method | |
| CN105988301B (en) | For the method and optical adjacent correction method of the coverage rate for checking test graphics library | |
| CN110929470A (en) | Layout optimization method | |
| CN104570584B (en) | A kind of OPC modification method of notch line end | |
| KR100881514B1 (en) | Method for fragmentation of model based optical proximity correction | |
| US8383299B2 (en) | Double patterning mask set and method of forming thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |