CN109143775A - The light mask image for reducing the method for light shield static discharge risk and its obtaining - Google Patents
The light mask image for reducing the method for light shield static discharge risk and its obtaining Download PDFInfo
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- CN109143775A CN109143775A CN201810991767.3A CN201810991767A CN109143775A CN 109143775 A CN109143775 A CN 109143775A CN 201810991767 A CN201810991767 A CN 201810991767A CN 109143775 A CN109143775 A CN 109143775A
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- China
- Prior art keywords
- mask image
- static discharge
- spacing
- light shield
- region
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/40—Electrostatic discharge [ESD] related features, e.g. antistatic coatings or a conductive metal layer around the periphery of the mask substrate
Abstract
The present invention relates to a kind of methods for reducing light shield static discharge risk, it is related to semiconductor integrated circuit manufacturing technology, including carrying out handling to obtain targeted graphical by rule-based OPC to light shield domain, is then handled by the OPC based on model, obtain initial light mask image；The closer Area generation mark layer of spacing between mutual disconnected figure is being selected in initial light mask image, secondary graphics are generated at the mark layer position in targeted graphical, wherein secondary graphics get up figure connection mutually disconnected in targeted graphical, and the size of secondary graphics is less than current layer critical size；And the processing of the OPC based on model is carried out to the targeted graphical after addition secondary graphics, obtain final light mask image, to reduce the risk for generating tip static discharge, to prevent light mask image from influencing exposure results because of static discharge damage, the yield of semiconductor devices is improved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing technology more particularly to a kind of reduction light shield static discharge risks
Method and its obtained light mask image.
Background technique
In semiconductor integrated circuit manufacturing technology, the key component that realize domain to wafer is exactly light shield, light
The quality of cover directly affects exposure results, and then influences the yield of final semiconductor devices.
And with the continuous development of semiconductor process technique, critical size is smaller and smaller, the spacing of graphics field on light shield
Also smaller and smaller, and since daily storage and use process are improper, the electrostatic that will lead to metal layer on light shield is accumulative, when electrostatic is tired
After counting to a certain extent, and since spacing is smaller between disjunct region on light shield metal layer, it is quiet to be just easy to produce tip
The case where discharge of electricity, so as to cause the damage of figure on mask plate.
For the static discharge for preventing metal layer on light shield, existing method is mainly the storage of strict control light shield and used
Environment in journey reduces electrostatic on light shield and generates accumulative possibility.This method requires very the storage of light shield and use environment
Risk that is high and can not actually solving light shield metal layer static discharge.
Therefore, reducing light shield static discharge risk becomes industry problem.
Summary of the invention
One of present invention is designed to provide a kind of method for reducing light shield static discharge risk, comprising: step S1: to light
Cover domain carries out handling to obtain targeted graphical by rule-based OPC, is then handled by the OPC based on model, obtains just
Beginning light mask image；Step S2: spacing is closer between mutual disconnected figure being selected in light mask image in initial light mask image
Area generation mark layer, the mark layer position generates secondary graphics in targeted graphical, and wherein secondary graphics are by targeted graphical
In mutually disconnected figure connection get up, and the size of secondary graphics is less than current layer critical size；And step S3: to adding
Targeted graphical after entering secondary graphics carries out the processing of the OPC based on model, obtains final light mask image.
Further, the closer region of spacing mutually between disconnected figure be mutual disconnected figure it
Between spacing be less than 120nm region.
Further, the closer region of spacing mutually between disconnected figure be mutual disconnected figure it
Between spacing be less than 100nm region.
Further, the size of the secondary graphics is less than the 1/3 of current layer critical size.
Further, the size of the secondary graphics is between 1/4 to the 1/3 of current layer critical size.
Further, further include step S4: the final light mask image being simulated with common software and model,
Corresponding analog result is obtained, and the secondary graphics added in the analog result are not exposed out.
Another object of the present invention is to provide a kind of based on light mask image obtained by the above method, comprising: the first figure
Region and second graph region, wherein first graphics field is got up with the second graph regional connectivity, and communicating position
The closer region of spacing between first graphics field and the second graph region.
Further, the closer region of spacing is less than between first graphics field and second graph region
120nm。
Further, the closer region of spacing is less than between first graphics field and second graph region
100nm。
One embodiment of the invention, by select spacing between mutual disconnected figure in initial light mask image closer
Area generation mark layer, the mark layer position generates secondary graphics in targeted graphical, to the targeted graphical that secondary graphics are added
The OPC based on model is carried out again to handle to obtain final light mask image, is realized in final light mask image by initial light mask image
In mutual disconnected figure connection get up, avoid the presence of metal tip in light shield, and then do not allow to be also easy to produce tip quiet
The case where discharge of electricity, improves the good of semiconductor devices to prevent light mask image from influencing exposure results because of static discharge damage
Rate.
Detailed description of the invention
Fig. 1 is the flow chart of the method for the reduction light shield static discharge risk of one embodiment of the invention.
Fig. 2 is the targeted graphical schematic diagram of one embodiment of the invention.
Fig. 3 is the initial light shield pictorial diagram of one embodiment of the invention.
Fig. 4 is the schematic diagram that secondary graphics are generated in targeted graphical of one embodiment of the invention.
Fig. 5 is the schematic diagram that mark layer is generated in the initial light mask image of one embodiment of the invention.
Fig. 6 is the schematic diagram of the final light mask image of one embodiment of the invention.
Fig. 7 is the light mask image analog result schematic diagram of one embodiment of the invention.
The reference numerals are as follows for main element in figure:
210, the first graphics field；220, second graph region；400, secondary graphics；300, mark layer.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In one embodiment of the invention, provide it is a kind of reduce light shield static discharge risk method, comprising: to light shield domain into
Row closes on amendment (Optical Proximity Correction, OPC) processing by rule-based optics and obtains target figure
Then shape is handled by the OPC based on model, obtains initial light mask image；It selects in initial light mask image and is not connected to mutually
Figure between the closer Area generation mark layer of spacing, in targeted graphical the mark layer position generate secondary graphics, wherein
Secondary graphics get up the mutually disconnected figure connection of targeted graphical, and the size of secondary graphics is less than current layer key ruler
It is very little；And the processing of the OPC based on model is re-started to the targeted graphical after addition secondary graphics, obtain final light mask image.
Specifically, seeing Fig. 1, Fig. 1 is the stream of the method for the reduction light shield static discharge risk of one embodiment of the invention
Cheng Tu.As shown in Figure 1, this method comprises:
Step S1: carrying out handling to obtain targeted graphical by rule-based OPC to light shield domain, then by being based on mould
The OPC of type is handled, and obtains initial light mask image.
Specifically, seeing Fig. 2 and Fig. 3, Fig. 2 is the targeted graphical schematic diagram of one embodiment of the invention, and Fig. 3 is the present invention
The initial light shield pictorial diagram of one embodiment.As shown in Fig. 2, targeted graphical includes the transmission region 100 of photoresist, the first figure
Shape region 210 and second graph region 220.It is illustrated in figure 3 and targeted graphical as shown in Figure 2 is carried out by based on model
OPC processing, obtains initial light mask image.As shown in figure 3, the first graphics field 210 and second graph region in light shield domain
It is not connected to mutually between 220, and the spacing between the first graphics field 210 and second graph region 220 is closer, is then just easy to produce
The case where raw tip static discharge, so as to cause the damage of figure on mask plate.
Step S2: the closer Area generation label of spacing between mutual disconnected figure is being selected in initial light mask image
Layer, the mark layer position generates secondary graphics in targeted graphical, and wherein secondary graphics will be mutually disconnected in targeted graphical
Figure connection is got up, and the size of secondary graphics is less than current layer critical size.
Specifically, seeing Fig. 4 and Fig. 5, Fig. 4 is the generation secondary graphics in targeted graphical of one embodiment of the invention
Schematic diagram, Fig. 5 are the schematic diagram that mark layer is generated in the initial light mask image of one embodiment of the invention.As shown in figure 5, selecting
The closer region 110 of spacing between one graphics field 210 and second graph region 220, and mark layer is generated at region 110
300.It is illustrated in figure 4 and generates secondary graphics 400 in mark layer position as shown in Figure 5, secondary graphics 400 are by the first graph area
Domain 210 is connected to second graph region 220.
In an embodiment of the present invention, the closer region of spacing is not to be connected to mutually between the mutually disconnected figure
Figure between spacing be less than 120nm region.More preferably, the closer region of spacing is between the mutually disconnected figure
Spacing is less than the region of 100nm between mutual disconnected figure.
In an embodiment of the present invention, the size of secondary graphics is less than the 1/3 of current layer critical size.
Further, in an embodiment of the present invention, the size of secondary graphics is 1/4 to the 1/ of current layer critical size
Between 3, in subsequent exposure, the secondary graphics of addition will not be exposed out.
Step S3: the processing of the OPC based on model is carried out to the targeted graphical after addition secondary graphics, obtains final light shield figure
Shape.
Specifically, seeing Fig. 6, Fig. 6 is the schematic diagram of the final light mask image of one embodiment of the invention.As shown in Figure 6
Final light mask image in be connected between the first graphics field 210 and second graph region 220.
In this way, in an embodiment of the present invention, by being selected in initial light mask image between mutual disconnected figure
The closer Area generation mark layer of spacing generates secondary graphics in the targeted graphical mark layer position, to addition secondary graphics
Targeted graphical carries out the OPC based on model again and handles to obtain final light mask image, and realizing in final light mask image will be mutual
Disconnected figure connection is got up, and avoids the presence of metal tip in light shield, and then do not allow to be also easy to produce tip static discharge
Situation improves the yield of semiconductor devices to prevent light mask image from influencing exposure results because of static discharge damage.
Further, in an embodiment of the present invention, the method for reducing light shield static discharge risk further includes step
Rapid S4: simulating final light mask image with common software and model, obtains corresponding analog result, in analog result
The secondary graphics of addition will not be exposed out.Specifically, seeing Fig. 7, Fig. 7 is the light mask image mould of one embodiment of the invention
Quasi- result schematic diagram.As shown in fig. 7, secondary graphics are not exposed out.
Further, in an embodiment of the present invention, the light mask image in a kind of OPC treatment process is also provided,
Specifically it can refer to Fig. 6, final light mask image shown in Fig. 6 is as being added secondary graphics 400 to targeted graphical shown in Fig. 4
The light mask image that further progress is handled based on the OPC of model afterwards.As shown in fig. 6, the first graphics field 210 and the second figure
Shape regional connectivity gets up, and communicating position closer area of spacing between the first graphics field 210 and second graph region 220
Domain.In this way, regional connectivity small-pitch between light shield metal layer is got up, the presence at tip is avoided, and then is not easy to produce
The case where raw tip static discharge, improves semiconductor to prevent light mask image from influencing exposure results because of static discharge damage
The yield of device.
In an embodiment of the present invention, the closer region of spacing is small between first graphics field and second graph region
In 120nm.More preferably, the closer region of spacing is less than 100nm between first graphics field and second graph region.
In this way, in an embodiment of the present invention, by being selected in initial light mask image between mutual disconnected figure
The closer Area generation mark layer of spacing generates secondary graphics in the targeted graphical mark layer position, to addition secondary graphics
Targeted graphical carries out the OPC based on model again and handles to obtain final light mask image, and realizing in final light mask image will be mutual
Disconnected figure connection is got up, and avoids the presence of metal tip in light shield, and then do not allow to be also easy to produce tip static discharge
Situation improves the yield of semiconductor devices to prevent light mask image from influencing exposure results because of static discharge damage.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (9)
1. a kind of method for reducing light shield static discharge risk characterized by comprising
Step S1: light shield domain is carried out handling to obtain targeted graphical by rule-based OPC, then by based on model
OPC processing, obtains initial light mask image；
Step S2: selecting the closer Area generation mark layer of spacing between mutual disconnected figure in initial light mask image,
The mark layer position generates secondary graphics in targeted graphical, and wherein secondary graphics are by disconnected figure mutual in targeted graphical
Connection is got up, and the size of secondary graphics is less than current layer critical size；And
Step S3: the processing of the OPC based on model is carried out to the targeted graphical after addition secondary graphics, obtains final light mask image.
2. the method according to claim 1 for reducing light shield static discharge risk, which is characterized in that described not to be connected to mutually
Figure between the closer region of spacing be spacing is less than 120nm between mutual disconnected figure region.
3. according to claim 1 or 2 it is described in any item reduce light shield static discharge risks methods, which is characterized in that it is described
The closer region of spacing is the region that spacing is less than 100nm between mutual disconnected figure between mutual disconnected figure.
4. the method according to claim 1 for reducing light shield static discharge risk, which is characterized in that the secondary graphics
Size is less than the 1/3 of current layer critical size.
5. according to claim 1 or 4 it is described in any item reduce light shield static discharge risks methods, which is characterized in that it is described
The size of secondary graphics is between 1/4 to the 1/3 of current layer critical size.
6. the method according to claim 1 for reducing light shield static discharge risk, which is characterized in that further include step S4:
The final light mask image is simulated with common software and model, obtains corresponding analog result, and in the simulation
As a result the secondary graphics added in are not exposed out.
7. a kind of light mask image that the method using reduction light shield static discharge risk described in claim 1 obtains, feature
It is, comprising: the first graphics field and second graph region, wherein first graphics field and the second graph region connect
Lead to, and communicating position closer region of spacing between first graphics field and the second graph region.
8. light mask image according to claim 7, which is characterized in that first graphics field and second graph region it
Between the closer region of spacing be less than 120nm.
9. according to the described in any item light mask images of claim 7 or 8, which is characterized in that first graphics field and second
The closer region of spacing is less than 100nm between graphics field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810991767.3A CN109143775A (en) | 2018-08-29 | 2018-08-29 | The light mask image for reducing the method for light shield static discharge risk and its obtaining |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810991767.3A CN109143775A (en) | 2018-08-29 | 2018-08-29 | The light mask image for reducing the method for light shield static discharge risk and its obtaining |
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| CN109143775A true CN109143775A (en) | 2019-01-04 |
Family
ID=64828996
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| CN201810991767.3A Pending CN109143775A (en) | 2018-08-29 | 2018-08-29 | The light mask image for reducing the method for light shield static discharge risk and its obtaining |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024045204A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Method and apparatus for locating production monitoring point of photomask, and electronic device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000098585A (en) * | 1998-09-25 | 2000-04-07 | Seiko Epson Corp | Semiconductor manufacture equipment and storage facility therefor |
| CN1372321A (en) * | 2001-02-27 | 2002-10-02 | 矽统科技股份有限公司 | Anti-electrostatic optical cover |
| US20070128526A1 (en) * | 2005-12-07 | 2007-06-07 | Intel Corporation | Non-collinear end-to-end structures with sub-resolution assist features |
| US7419748B1 (en) * | 2004-08-24 | 2008-09-02 | Integrated Device Technology, Inc. | Photomask with reduced electrostatic discharge defects |
| CN101398612A (en) * | 2007-09-29 | 2009-04-01 | Hoya株式会社 | Photomask, manufacturing method thereof and pattern transfer printing method |
| CN101598893A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | Tool prevents the light shield of electrostatic breakdown |
| CN103777457A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method for contact hole graphic design |
| KR20150057028A (en) * | 2013-11-18 | 2015-05-28 | 엘지디스플레이 주식회사 | Photo mask and manufacturing method of display device using the same |
| CN104698736A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Processing method for avoiding photomask graph unit ESD phenomenon |
| CN106154737A (en) * | 2016-06-30 | 2016-11-23 | 上海华力微电子有限公司 | A kind of domain processing method reducing ESD risk |
-
2018
- 2018-08-29 CN CN201810991767.3A patent/CN109143775A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000098585A (en) * | 1998-09-25 | 2000-04-07 | Seiko Epson Corp | Semiconductor manufacture equipment and storage facility therefor |
| CN1372321A (en) * | 2001-02-27 | 2002-10-02 | 矽统科技股份有限公司 | Anti-electrostatic optical cover |
| US7419748B1 (en) * | 2004-08-24 | 2008-09-02 | Integrated Device Technology, Inc. | Photomask with reduced electrostatic discharge defects |
| US20070128526A1 (en) * | 2005-12-07 | 2007-06-07 | Intel Corporation | Non-collinear end-to-end structures with sub-resolution assist features |
| CN101398612A (en) * | 2007-09-29 | 2009-04-01 | Hoya株式会社 | Photomask, manufacturing method thereof and pattern transfer printing method |
| CN101598893A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | Tool prevents the light shield of electrostatic breakdown |
| CN103777457A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method for contact hole graphic design |
| KR20150057028A (en) * | 2013-11-18 | 2015-05-28 | 엘지디스플레이 주식회사 | Photo mask and manufacturing method of display device using the same |
| CN104698736A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Processing method for avoiding photomask graph unit ESD phenomenon |
| CN106154737A (en) * | 2016-06-30 | 2016-11-23 | 上海华力微电子有限公司 | A kind of domain processing method reducing ESD risk |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024045204A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Method and apparatus for locating production monitoring point of photomask, and electronic device |
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Application publication date: 20190104 |
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