CN106154648B

CN106154648B - Display panel

Info

Publication number: CN106154648B
Application number: CN201510130414.0A
Authority: CN
Inventors: 余翊菱; 卓暐清; 朱夏青; 黄鹏丞
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2015-03-24
Filing date: 2015-03-24
Publication date: 2021-03-19
Anticipated expiration: 2035-03-24
Also published as: CN112859453A; CN106154648A; CN112859453B

Abstract

An embodiment of the invention provides a display panel, which includes a first substrate, a second substrate, a scan line, a channel layer, a data line, and a spacer. The second substrate is combined with the first substrate. The scanning line is positioned on the first substrate. The channel layer is configured on the scanning line. The data line is positioned on the channel layer, the data line is provided with at least one overlapping area overlapping with the channel layer and the scanning line, and the data line is provided with a first area and a second area overlapping with the scanning line. The spacer is located between the data line and the second substrate, and the spacer partially corresponds to the overlapping region and partially corresponds to at least one of the first region and the second region.

Description

Display panel

Technical Field

The present invention relates to a display panel structure, and more particularly, to a display panel having spacers.

Background

A conventional Thin film transistor liquid crystal display (TFT-LCD) includes an active device array substrate, a color filter and a backlight module. The active element array substrate is provided with a thin film transistor arranged on the substrate, and the thin film transistor is used for controlling the voltage of a sub-pixel (sub-pixel), so as to adjust the deflection angle of liquid crystal molecules and further determine the gray scale of the sub-pixel through a polaroid. The light emitted by the backlight element or the self-luminous element passes through the gray scale of the sub-pixel and is matched with the color filter, thereby forming an image picture.

Because of the improvement of touch technology, touch is often used to replace the conventional mouse and keyboard control devices to control the cursor, the drawing, etc. on the display panel, and when the user uses the display panel, the user will touch the surface of the display panel, and at this time, the substrate of the display panel is easy to slightly press down due to the force. Generally, the spacers used for the upper and lower substrates of the cell in the display panel are deformed or shifted and slide along with the pressing of the substrates, however, the shift of the spacers easily causes abnormal deflection of the liquid crystal, which results in abnormal image display of the display panel.

Disclosure of Invention

Embodiments of the present invention provide a display panel, in which an active device array layer is formed to improve the displacement of spacers due to stress.

An embodiment of the present invention provides a display panel, which includes a first substrate, a second substrate, a scan line, a channel layer, a data line, and a spacer. The scanning line is positioned on the first substrate. The channel layer is configured on the scanning line. The data line is positioned on the first substrate and is arranged in a staggered mode with the scanning line, the data line is provided with at least one overlapping area which is overlapped with the scanning line, the data line is also provided with a first area which is overlapped with the channel layer in the overlapping area, a through hole spacer is formed in the first area and is positioned on the data line, and the spacer partially corresponds to the first area and partially corresponds to the overlapping area outside the first area.

Another embodiment of the present invention provides a display panel, which includes a first substrate, a scan line, a channel layer, a data line, and a pixel electrode. The scanning line is located on the first substrate and has a first side and a second side. The channel layer is configured on the scanning line. The pixel electrode is positioned on the first substrate. The data line is positioned on the first substrate and arranged in a staggered mode with the scanning line, the data line is provided with at least one overlapping area overlapped with the scanning line, the data line is further provided with a first area overlapped with the channel layer in the overlapping area, and a through hole is formed in the first area. The first side edge and the fifth side edge have a first shortest distance therebetween, the second side edge and the sixth side edge have a second shortest distance therebetween, and the first shortest distance is greater than the second shortest distance.

In summary, the display panel provided in the embodiments of the invention has the spacers PS partially corresponding to the first region and partially corresponding to at least one of the second region and the third region. Further, the data line is overlapped on the channel layer and the scan line within the range corresponding to the overlap region, and the spacer partially corresponds to the data line, the channel layer and the scan line. Because the active element array layer is formed with the step structure, when a user touches the second substrate of the display panel, the second substrate is stressed and slightly pressed, so that the spacers are pressed against the data lines. Since part of the spacers corresponds to the first region and the other part of the spacers corresponds to the second region or the third region, the spacers correspondingly collide with the step structure of the active device array layer having the first height and the second height. Therefore, when the spacer partially corresponds to the first region and partially corresponds to the second region or the third region, the step structure of the active device array layer is used to increase the friction force when the spacer receives an external force, so that the spacer is less prone to shift, and the abnormal liquid crystal deflection caused by the shift of the spacer is further reduced.

In addition, the channel layer may be farther from the pixel electrode electrically connected to the channel layer than the pixel electrode not electrically connected to the channel layer, and the pixel electrode may be disposed partially overlapping the channel layer and covering the first side of the scan line. Therefore, the situation that the convex part of the pixel electrode is likely to be overlapped with the data line due to offset in the manufacturing process can be avoided, and the formation of a back channel or the increase of parasitic capacitance can be further improved.

In addition, the scan line may have a first inner concave portion, where the scan line formed with the first inner concave portion may reduce an area overlapping with the data line, thereby reducing an increase in parasitic capacitance existing at an overlapping portion of the scan line and the data line. In addition, when the step of preparing the data line on the channel layer and the scan line, the data line is easier to be manufactured on the scan line formed with the first concave portion compared with the scan line not formed with the first concave portion because the gradient of the scan line of the first concave portion is relatively slow.

It should be noted that, in other embodiments, the scan line may further have a second inner recess portion, and the second inner recess portion is disposed opposite to the first inner recess portion and disposed at the intersection of the scan line and the data line, so that the data line is easier to be fabricated on the scan line on which the first inner recess portion and the second inner recess portion are formed, and the parasitic capacitance existing at the overlapping portion of the scan line and the data line is better reduced.

For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description, and are not intended to be limiting.

Drawings

Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Fig. 2 is a schematic top view of a first substrate according to an embodiment of the invention.

Fig. 3 is a schematic partial structure diagram of an active device array layer according to an embodiment of the invention.

Fig. 4A is a schematic cross-sectional view taken along the line M-M' in fig. 3.

Fig. 4B is a cross-sectional view of the usage state in fig. 4A.

FIG. 4C is a cross-sectional view of the usage state of the device shown in FIG. 3 along the line N-N'.

Fig. 5 is a schematic top view of a display panel according to another embodiment of the invention.

Fig. 6 is a schematic top view of a display panel according to another embodiment of the invention.

Fig. 7 is a schematic top view of a display panel according to another embodiment of the invention.

[ symbol simple description of the figure ]:

100 display panel 110 scan lines

120 channel layer 130 data line

131 drain electrode 140 protective layer

B1 first substrate B2 second substrate

CFa light shielding layer CFb color filter

lQ liquid crystal layer CF colour filter layer

T1 active device array layer PI alignment film

PS spacer V1, V2 through hole

Detailed Description

Some exemplary embodiments are shown in the accompanying drawings, and various exemplary embodiments will be described more fully below with reference to the accompanying drawings. It should be noted that the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In each of the drawings, the relative proportions of layers and regions are exaggerated in order to provide clarity and understanding, and like numerals designate like elements throughout.

Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. In the present embodiment, the display panel 100 is a liquid crystal panel. The display panel 100 includes a first substrate B1, a second substrate B2, a color filter layer CF, a liquid crystal layer LQ, an active device array layer T1, and a spacer PS. The first substrate B1 is combined with the second substrate B2, and the liquid crystal layer LQ, the active device array layer T1 and the spacers PS are located between the first substrate B1 and the second substrate B2. Generally, the active device array layer T1 is disposed on the first substrate B1 to form an active device array substrate. The color filter layer CF may be disposed on the second substrate B2 and include a light-shielding layer CFa and a plurality of color filters CFb of various colors. The liquid crystal layer LQ is disposed in the gap between the first substrate B1 and the second substrate B2 for changing the direction of incident light. In addition, the display panel 100 may further include an alignment film PI. The alignment film PI is substantially located between the liquid crystal layer LQ and the active device array layer T1 and sandwiched outside the liquid crystal layer LQ, and the rotation direction of the liquid crystal is controlled by the active device array layer T1 and the alignment film PI.

Fig. 2 is a schematic top view of a first substrate according to an embodiment of the invention. Fig. 3 is a schematic partial structure diagram of an active device array layer according to an embodiment of the invention. Referring to fig. 2 and 3, the data line driving unit U1 is disposed on one side of the active device array substrate, and the scan line driving unit U2 is disposed on the other side of the active device array substrate. In the present embodiment, the active device array layer T1 includes a scan line 110, a channel layer 120 and a data line 130. The scan line 110 is located on the first substrate B1, the channel layer 120 is disposed on the scan line 110, and the data line 130 is located on the first substrate B1, is staggered with the scan line 110, and is located on the channel layer 120. In practice, the scan lines 110 extend in a row direction and are parallel to each other, and the data lines 130 extend in a column direction and are substantially parallel to each other. The scan lines 110 and the data lines 130 are stacked alternately and define a plurality of sub-pixel units FN, N is greater than 1, such as F1, F2, etc.

The channel layer 120 is a semiconductor layer, and the material thereof may be selected from one of the group consisting of a polysilicon layer, a metal oxide semiconductor layer, and an amorphous silicon layer. In the present embodiment, the material of the channel layer 120 may be one selected from the group consisting of Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Tin Oxide (SnO), Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GaZnO), Zinc-Tin Oxide (ZTO), Indium-Tin Oxide (ITO), and a mixture thereof. In the present embodiment, the material of the channel layer 120 is indium gallium zinc oxide. However, the present invention is not limited thereto. Specifically, the channel layer 120 may be formed by magnetron sputtering (MOCVD), Metal Organic Chemical Vapor Deposition (MOCVD), or Pulsed Laser Deposition (PLD).

The protection layer 140 is disposed on the channel layer 120 and serves as an Etch Stop Layer (ESL) of the channel layer 120 to prevent the subsequent channel layer 120 from being damaged in the subsequent process to cause electrical abnormality. The material of the protection layer 140 is silicon oxide (SiO)_x) And the like. The passivation layer 140 may be patterned by a photolithography process to form a via hole V1 and a via hole V2 in the passivation layer 140, and the data line 130 overlaps the passivation layer 140 and may form a source electrode in contact with the channel layer 120 through the via hole V1. In forming the data line and the source electrode, the drain electrode 131 contacting the channel layer 120 may be formed on the inner wall of the via hole V2 by the same process or the same process, and the drain electrode 131 is disposed to be insulated from the data line 130 and the source electrode.

The spacer ps (spacer) is disposed between the data line 130 of the active device array layer T1 and the second substrate B2 to maintain a gap (Cell gap) between the first substrate B1 and the second substrate B2. In the present embodiment, the spacers PS are formed on the color filter layer CF and extend toward the active device array layer T1. In general, the spacers PS correspond to the crossing of the scan lines 110 and the data lines 130, and are approximately in contact with the alignment film PI located above the data lines 130. Specifically, the spacer PS may be designed in a spherical shape, a polygonal pillar shape, a conical shape, a polygonal pyramid shape, a multilayer stack shape, a separator shape, or the like. It should be noted that the spacers PS can be made of various colors or transparent photoresist materials, polymer materials or silicon oxide materials, and are formed by photolithography, Sputtering, Chemical Vapor Deposition (CVD), or spraying. However, the present invention does not limit the design and process conditions of the spacer PS.

Specifically, the scan line 110 has a first side S1 and a second side S2, and the data line 130 has a third side S3 and a fourth side S4. The data line 130 is located above the scan line 110 and overlaps the scan line 110, wherein a portion of the data line 130 is located directly above the channel layer 120 and the scan line 110, when viewed from a top view from the spacer PS toward the first substrate B1. Accordingly, the data line 130 has at least one overlap area AA overlapping with the scan line 110, wherein the data line further has a first area a1 overlapping with the channel layer 130 in the overlap area AA. The overlapping area AA is surrounded by the first side S1, the second side S2, the third side S3 and the fourth side S4, and the first area a1 has the fifth side S5 and the sixth side S6, and the first area a1 is surrounded by the third side S1, the fourth side S4, the fifth side S5 and the sixth side S6. The fifth side S5 is a side of the first region A1 adjacent to the first side S1, and the sixth side S6 is a side of the overlapping region AA adjacent to the second side S2. Substantially, the fifth side S5 and the sixth side S6 are parallel to the extending direction of the scan line 110.

From a top view, when viewed from the spacer PS toward the first substrate B1, a portion of the data line 130 is only located above the scan line 110 and does not overlap with the channel layer 120, so the overlapping area AA outside the first area a1 further includes the second area a2 and the third area A3. The second area a2 is composed of a first side S1, a third side S3, a fourth side S4 and a fifth side S5, and the third area A3 is composed of a second side S2, a third side S3, a fourth side S4 and a sixth side S6. It should be noted that the spacer PS partially corresponds to the first area a1 and partially corresponds to the overlapping area AA outside the first area a1, such as at least one of the second area a or the third area A3.

Fig. 4A is a schematic cross-sectional view taken along the line M-M' in fig. 3. Fig. 4B is a cross-sectional view of the usage state in fig. 4A. FIG. 4C is a schematic cross-sectional view taken along the line N-N' in FIG. 3. Referring to fig. 4A to 4C and referring to fig. 3, in the present embodiment, the spacer PS partially corresponds to the first region a1 and partially corresponds to the third region A3. Further, within a range corresponding to the first region a1, the data line 130 is stacked on the channel layer 120 and the scan line 110, the spacer PS partially corresponds to the data line 130, the channel layer 120 and the scan line 110, and the second surface E2 of the data line 130 is spaced apart from the first surface E1 of the first substrate B1 by a first height H1. Within a range corresponding to the third region a3, the data line 130 substantially overlaps only the scan line 110, the spacer PS partially corresponds to the outside of the channel layer 120 above the data line 130 and the scan line 110, and a second height H2 is formed between the second surface E2 of the data line 130 and the first surface E1 of the first substrate B1. Since the thickness of the channel layer 120 is reduced in different regions (the overlapping region AA and the second region a2), the second surface E2 of the data line 130 is spaced apart from the first surface E1 of the first substrate B1 by a different height, and the first height H1 is greater than the second height H2. Accordingly, the active device array layer T1 has a plurality of step heights to form a step structure.

As shown in fig. 4B and 4C, when the user touches the second substrate B2 of the display panel 100, the second substrate B2 is pressed slightly by the force, such that the spacer PS is abutted on the data line 130 (or the alignment film PI). Since a portion of the spacer PS corresponds to the first region a1 and another portion of the spacer PS corresponds to the third region A3, the spacer PS correspondingly interferes with the offset structure of the active device array layer T1 having the first height H1 and the second height H2. Therefore, when the spacer PS partially corresponds to the overlapping area AA and partially corresponds to the second area a2, the step structure of the active device array layer T1 increases the friction force of the spacer PS when receiving an external force, so that the spacer PS is less prone to shift, and the abnormal liquid crystal deflection caused by the shift of the spacer PS is further reduced.

Fig. 5 is a schematic top view of a display panel according to another embodiment of the invention. Referring to fig. 5, a first shortest distance W1 is between the first side S1 and the fifth side S5, and a second shortest distance is between the second side S2 and the sixth side S6, wherein the first shortest distance W1 is greater than the second shortest distance W2. That is, the fifth side S5 and the sixth side S6 of the first region a1 are separated from the first side S1 and the second side S2 of the scan line 110 by the first shortest distance W1 and the second shortest distance W2, respectively. In one embodiment, preferably, the first shortest distance W1 is greater than the second shortest distance W2. That is, the first shortest distance W1 between the fifth side S5 and the first side S1 is greater than the second shortest distance W2 between the sixth side S6 and the second side S2. It should be noted that, from the top view, when viewed from the spacer PS toward the first substrate B1, the channel layer 120 is located closer to the next sub-pixel F2 than the sub-pixel F1 surrounded by the scan line 110 and the data line 130. That is, the channel layer 120 is far from the pixel electrode PX to which it is electrically connected, and is relatively close to the pixel electrode PX' to which it is not electrically connected.

Therefore, when the spacer PS partially corresponds to the first region a1 and partially corresponds to the third region A3, the spacer PS can correspond to the offset structure of the active device array layer T1 within a shorter range, so that the friction force of the spacer PS to be shifted due to external force is increased, and the spacer PS is less likely to shift.

Fig. 6 is a schematic top view of a display panel according to another embodiment of the invention. Referring to fig. 6, in practice, the shape of the pixel electrode PX may be designed with at least one protrusion PX1 in consideration of the requirement of meeting the process parameter design or the liquid crystal alignment condition. In an embodiment, preferably, in a case that the first shortest distance W1 is greater than the second shortest distance W2, that is, the channel layer 120 is farther from the pixel electrode PX to which it is electrically connected and is closer to the pixel electrode PX' to which it is not electrically connected, the pixel electrode PX may be disposed at a position partially overlapping the channel layer 120 and covering the first side S1 of the scan line 110. In this way, the convex PX1 of the pixel electrode PX may easily overlap the data line 130 due to offset in the manufacturing process, and the formation of the back channel or the increase of the parasitic capacitance may be further improved.

Fig. 7 is a schematic top view of a display panel according to another embodiment of the invention. Referring to FIG. 7, in an embodiment, the scan line 110 extends in a row direction and has a first inner recess 110a, and the first inner recess 110a is located at an intersection of the scan line 110 and the data line 130. In this embodiment, the first concave portion 110a is located at the first side S1 of the scan line 110 and at the intersection of the scan line 110 and the data line 130. The data line 130 is stacked on the channel layer 120 and the scan line 110 and passes through the first inner recess 110 a. Here, the scan line 110 having the first inner concave portion 110a formed therein can reduce the area overlapping the data line 130, that is, the area of the second region a2, thereby reducing the increase in parasitic capacitance existing at the overlapping portion of the scan line 110 and the data line 130. In addition, when the step of fabricating the data line 130 on the channel layer 120 and the scan line 110, since the slope of the scan line 110 of the first inner recess 110a is gentle, the data line 130 is easier to be fabricated at the position of the scan line 110 where the first inner recess 110a is formed than the scan line 110 where the first inner recess 110a is not formed without a problem of breaking the data line 130 due to a height difference of the scan line 110. It should be noted that, in other embodiments, the scan line 110 may further have a second inner concave portion (not shown), where the second inner concave portion and the first inner concave portion 110a are disposed opposite to each other at two sides of the scan line 110 and are disposed at the intersection of the scan line 110 and the data line 130, so that the data line 110 is easier to be fabricated on the scan line 110 formed with the first inner concave portion 110a and the second inner concave portion, and the areas of the second region a2 and the third region A3 are reduced, thereby further reducing the parasitic capacitance existing at the overlapping portion of the scan line 110 and the data line 130.

[ possible effects of the embodiment ]

In summary, the display panel provided in the embodiments of the invention has the spacers PS partially corresponding to the first region and partially corresponding to at least one of the second region and the third region. Further, the data line is overlapped on the channel layer and the scan line within the range corresponding to the overlap region, and the spacer partially corresponds to the data line, the channel layer and the scan line. Because the active element array layer is formed with the step structure, when a user touches the second substrate of the display panel, the second substrate is stressed and slightly pressed, so that the spacers are pressed against the data lines. Since part of the spacers corresponds to the first region and the other part of the spacers corresponds to the second region or the third region, the spacers correspondingly collide with the step structure of the active device array layer having the first height and the second height. Therefore, when the spacers partially correspond to the first region and partially correspond to the second region or the third region, the active device array layer has a step structure to increase the friction force when the spacers are subjected to an external force, so that the spacers are less prone to shift, and the abnormal deflection of the liquid crystal caused by the shift of the spacers is further reduced.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, so that equivalent technical changes made by using the contents of the present specification and drawings are included in the scope of the present invention.

Description of the symbols

100 display panel 110 scan lines

110a first inner recess 120 channel layer

130 data line 131 drain electrode

140 protective layer AA overlap region

A1 first region A2 second region

A3 third region B1 first substrate

B2 second substrate CFa shading layer

CF color filter layer of CFb color filter

E1 first surface E2 second surface

F1, F2, FN sub-pixel unit H1 first height

H2 second height LQ liquid crystal layer

PS spacer of PI alignment film

PX, PX' pixel electrode PX1 convex part

S1-S6 first side-sixth side T1 active device array layer

U1 data line driving unit U2 scanning line driving unit

V1, V2 through hole W1 first shortest distance

W2 second shortest distance

Claims

1. A display panel, comprising:

a first substrate;

a scanning line on the first substrate;

a channel layer configured on the scanning line;

a protective layer disposed on the channel layer;

a pixel electrode on the first substrate;

a data line on the first substrate and disposed to be staggered with the scan line, the data line having at least one overlap region overlapping with the scan line, wherein the data line further has a first region overlapping with the channel layer in the overlap region, and the protective layer has a via hole formed corresponding to the first region, the data line overlaps on the protective layer, and a source electrode contacting with the channel layer is formed through the via hole;

wherein the scan line has a first side and a second side, the data line has a third side and a fourth side, the first region has a fifth side adjacent to the first side and a sixth side adjacent to the second side, and the pixel electrode covers the first side,

in the overlapping region, the scanning line is provided with a first concave part, and the data line is overlapped on the channel layer and the scanning line and passes through the first concave part; and

a spacer on the data line,

wherein the data line further has a second region in the overlap region not overlapping with the channel layer, the second region being formed by the fifth side, the first side, the third side, and the fourth side,

wherein the gap corresponds in part to the first region and in part to the second region.

2. The display panel of claim 1, wherein the overlap region outside the first region further comprises a third region, the third region being formed by the sixth side, the second side, the third side, and the fourth side.

3. The display panel according to claim 1, wherein the fifth side and the sixth side of the first region are parallel to an extending direction of the scan line.

4. The display panel of claim 2, wherein the first substrate has a first surface and the data line has a second surface, the second surface is spaced apart from the first surface by a first height in the first region, the second surface is spaced apart from the first surface by a second height in the third region, and the first height is greater than the second height.

5. The display panel of claim 1, wherein the scan line further has a second concave portion, the second concave portion being disposed opposite to the first concave portion.

6. The display panel of claim 1, wherein the channel layer is a metal oxide semiconductor layer.

7. A display panel, comprising:

a first substrate;

a scanning line on the first substrate;

a channel layer configured on the scanning line;

a protective layer disposed on the channel layer;

a pixel electrode on the first substrate; and

in the overlapping region, the scan line has a first concave portion, and the data line is overlapped on the channel layer and the scan line and passes through the first concave portion.

8. The display panel of claim 7, wherein the display panel further comprises a spacer, the spacer sub-portion corresponding to the first region.

9. The display panel of claim 8, wherein the gap sub-portion corresponds to the overlap region outside the first region.

10. The display panel of claim 9, wherein the overlap region outside the first region further comprises a second region and a third region, the second region is formed by the fifth side, the first side, the third side and the fourth side, the third region is formed by the sixth side, the second side, the third side and the fourth side, and the gap sub-portion corresponds to the first region and the third region.

11. The display panel of claim 10, wherein the first substrate has a first surface and the data line has a second surface, the gaps partially correspond to the first region and the third region, the second surface is spaced apart from the first surface by a first height in the first region, the second surface is spaced apart from the first surface by a second height in the third region, and the first height is greater than the second height.

12. The display panel according to claim 7, wherein the fifth side and the sixth side of the first region are parallel to an extending direction of the scan line.

13. The display panel of claim 7, wherein the scan line further has a second concave portion, the second concave portion being disposed opposite to the first concave portion.

14. The display panel according to claim 7, wherein the channel layer is a metal oxide semiconductor layer.