CN103901684A - Liquid crystal display in IPS (in-plane switching) mode - Google Patents
Liquid crystal display in IPS (in-plane switching) mode Download PDFInfo
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Abstract
The invention provides a liquid crystal display in an IPS (in-plane switching) mode. The liquid crystal display comprises a TFT (thin film transistor) substrate, a plurality of pairs of gate lines, a plurality of data lines and a plurality of pixels, wherein the gate lines and the data lines are formed on the TFT substrate, the pixels are limited by intersecting of the gate lines and the data lines, each pixel comprises a first sub pixel and a second sub pixel, each sub pixel comprises a TFT switch element, pixel electrodes and common electrodes, the pixel electrodes and the common electrodes are arranged at intervals, source electrodes of the TFT switch elements in two sub pixels on two sides of a same data line are connected onto a same data line, gate electrodes of the TFT switch elements in two sub pixels on two sides of the same data line are connected on a pair of gate lines on two sides of the data line, and the first sub pixels and the second sub pixels are provided with odd columns. By manufacturing an odd-column IPS mode driver, manufacturing difficulty of engineering is lowered, in addition, an aperture opening ratio of the liquid crystal display is increased by arranging common lines between the first sub pixels and the second sub pixels.
Description
Technical field
The present invention relates to a kind of liquid crystal display, more specifically, relate to the liquid crystal display of switching (IPS) pattern in a kind of face.
Background technology
The liquid crystal display (LCD) of switching (IPS) pattern in face is because its good viewing angle characteristic is widely used.Horizontal component of electric field in the IPS pattern of switching in the LCD use face of described IPS pattern is as LCD drive method.
The LCD of IPS pattern comprises: have the CF substrate and the TFT substrate that are oppositely arranged, and have the liquid crystal layer between described CF substrate and TFT substrate.Described TFT substrate comprises multiple gate lines, multiple data line, TFT, public electrode and pixel electrode, and multiple described gate lines and multiple described data line are arranged in a crossed manner, and adjacent described gate line and described data line limit a pixel.Described TFT, public electrode and pixel electrode are positioned at described pixel.Public electrode and pixel electrode are intervally installed on same substrate.Described CF substrate comprises black matrix and color filter, and described black matrix is corresponding with the position of gate line, data line and TFT on TFT substrate, and the position of described color filter arranges according to the position of each pixel.Described liquid crystal layer is driven by the horizontal component of electric field between public electrode and pixel electrode.In order to guarantee transmittance, described public electrode and described pixel electrode are transparency electrode.
Below IPS mode LCD of the prior art is described.Fig. 1 is the vertical view of the liquid crystal display of the IPS pattern of prior art.Fig. 2 is the sectional view of Fig. 1 along A-A direction.
As depicted in figs. 1 and 2, the TFT substrate of the IPS mode LCD of prior art comprises substrate 101, the multiple gate lines 102 and the multiple concentric line 103 that on substrate 101, extend along first direction, described gate line 102 is parallel to each other and is separated from each other with described concentric line 103, multiple data lines 104 are arranged in a crossed manner with described multiple gate lines 102, pixel of adjacent gate line 102 and data line 104 restriction arranged in a crossed manner, multiple pixel electrodes 106 are formed in the described pixel being limited by gate line 102 and data line 104, described TFT is arranged on the infall of gate line 102 and data line 104.Each described TFT comprises grid 107, active layer 108, and source electrode 109 and drain electrode 110, public electrode 111 is arranged on described substrate 101, and described public electrode 111 arranges with described pixel electrode 106 intervals.
Described grid 107 is positioned on described substrate 101, described grid 107 is insulated from each other with described active layer 108, between described grid 107 and described active layer 108, gate insulation layer 112 is set, described source electrode 109 and drain electrode 110 are positioned on described active layer 108, in described source electrode 109 and drain electrode 110, passivation layer 113 is set, described pixel electrode 106 is positioned on described passivation layer 113.
Described grid 107 is one-body molded with described gate line 102, and described source electrode 109 is one-body molded with described data line 104, and described drain electrode 110 can be electrically connected with pixel electrode 106 by via hole.Described gate line 102 provides the sweep signal from gate drivers (not shown), and described data line 104 provides the data-signal from data driver (not shown).
In the time inputting Continuity signal in gate line 102, active layer 108 conducts electricity, and the data-signal of data line 104 can arrive drain electrode 110 through the raceway groove of active layer 108 from source electrode 109, finally inputs to pixel electrode 106.Pixel electrode 106 obtains being formed for public electrode 111 horizontal component of electric field that drives liquid crystal to rotate after signal.
As shown in Figure 2, in the array base-plate structure of the IPS of prior art mode LCD, the first memory capacitance C1 is formed between pixel electrode 106 and concentric line 103, between described pixel electrode 106 and described concentric line 103, be provided with gate insulation layer 112 and passivation layer 113, the second memory capacitance C2 be formed on drain electrode 110 and and the overlapping concentric line 103 of drain electrode between, between described drain electrode 110 and described concentric line 103, be provided with gate insulation layer 112.
As shown in Figure 1, in the LCD of IPS pattern design, in order to reach maximum open rate, data line 102 on TFT substrate overlaps with public electrode 105, and a pair of pixel electrode/public electrode pivot region is called hurdle (column), so in any case all can only obtain even number hurdle with layer making pixel electrode and public electrode, such as 4 hurdles or 6 hurdles, like this, smaller to design parameter choice, the manufacture difficulty of engineering is strengthened.
In addition, in the prior art, memory capacitance is the Main Means that maintains pixel electrode current potential after liquid crystal display pixel sweep signal finishes, and unification increases the memory capacitance of pixel, can effectively improve the homogeneity of picture.But in prior art, to improve the memory capacitance of pixel, just need to take more space, thereby can cause the reduction of aperture opening ratio.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of liquid crystal display of IPS pattern, increases aperture opening ratio when increasing the selection of design parameter.
According to the liquid crystal display of a kind of IPS pattern of the present invention, comprising:
TFT substrate;
Be formed on the multipair gate line on described TFT substrate, every pair of described gate line comprises first grid polar curve and second gate line parallel to each other;
Be formed on many data lines on described TFT substrate, with vertical setting of described multipair gate line;
Multiple pixels, are intersected and are limited by described multipair gate line and described many data lines, and every row pixel is corresponding to a pair of described gate line and be sandwiched between described pair of grid lines;
Each described pixel comprises the first sub-pixel and the second sub-pixel;
Each described sub-pixel comprises the public electrode of TFT on-off element, pectination and the pixel electrode of pectination, and described pixel electrode and described public electrode interval arrange;
The source electrode of the TFT on-off element in two sub-pixels of same data line both sides is connected on described same data line, and grid connects respectively in the pair of grid lines of both sides;
A pair of pixel electrode and public electrode pivot region are called hurdle, and the number on the hurdle in described the first sub-pixel and described the second sub-pixel is odd number.
Preferably, in each pixel, the adjacent setting of pixel electrode of described the first sub-pixel and the second sub-pixel.
Preferably, between the first sub-pixel in each described pixel and the second sub-pixel, be provided with concentric line, described concentric line has overlapping with the pixel electrode of described two sub-pixels respectively.
Preferably, described liquid crystal display also comprises the first auxiliary capacitor substrate and the second auxiliary capacitor substrate, and described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are with layer with the grid of described TFT switch element; Described the first auxiliary capacitor substrate is connected with the drain electrode of the TFT switch element in described the first sub-pixel, described the second auxiliary capacitor substrate is connected with the drain electrode of the TFT switch element in described the second sub-pixel, and described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are all overlapping with described concentric line.
Preferably, described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are and the grid of the described TFT switch element metal level with layer.
Preferably, between described concentric line and pixel electrode, form the first memory capacitance, between described concentric line and auxiliary capacitor substrate, form the second memory capacitance.
Preferably, described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are not communicated with.
Preferably, described concentric line is and the source-drain electrode of the described TFT switch element metal level with layer.
Preferably, described liquid crystal display also comprises the passivation layer being formed on TFT substrate, the same layer of described pixel electrode and public electrode, and be all formed on the passivation layer of described pixel.
Preferably, data line is all covered by described public electrode.
Preferably, the number on described hurdle is 3～7.
Compared with prior art, the present invention has the following advantages:
The liquid crystal display of a kind of IPS pattern provided by the invention, adopts bigrid wiring, on the one hand, can make the driving of odd number hurdle IPS pattern, has increased the selection of design parameter, has reduced the difficulty that engineering is manufactured.In addition, utilize a utilizable part of every middle existence of two pixels to be set to public electrode wire, can in forming memory capacitance, increase aperture opening ratio.
Accompanying drawing explanation
Fig. 1 is the vertical view of the array base-plate structure of IPS mode LCD in prior art.
Fig. 2 is the sectional view of Fig. 1 along A-A direction.
Fig. 3 is the vertical view of the array base-plate structure of IPS mode LCD in the present invention.
Fig. 4 is the vertical view of the array base-plate structure of the IPS mode LCD of memory capacitance improvement design in the present invention.
Fig. 5 is the sectional view of Fig. 4 the first sub-pixel along B-B direction.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment mono-
Fig. 3 is the vertical view of the array base palte of IPS mode LCD in the embodiment of the present invention.As shown in Figure 3, the liquid crystal display of the IPS pattern of the present embodiment, comprise: TFT substrate 301, described TFT substrate 301 is transparency carrier, concrete, its material can be glass or transparent organic material etc., be formed on the multipair gate line 302 on described TFT substrate 301, every pair of described gate line 302 comprises first grid polar curve 302a parallel to each other and second gate line 302b, be formed on many data lines 303 on described TFT substrate, with the vertical setting of described multipair gate line 302 and insulated from each other, described gate line 302 and described data line 303 can comprise molybdenum (Mo), chromium (Cr), aluminium (Al), silver (Ag), titanium (Ti), in tantalum (Ta) and tungsten (W) at least one.
Intersect by described multipair gate line 302 and described many data lines 303 the multiple pixels 304 that limit, every row pixel 304 is corresponding to a pair of described gate line and be sandwiched between described pair of grid lines, each described pixel 304 comprises the first sub-pixel 304a and the second sub-pixel 304b, each described the first sub-pixel 304a and described the second sub-pixel 304b comprise the public electrode 305 of TFT on-off element, pectination and the pixel electrode 306 of pectination, and described pixel electrode 306 and described public electrode 305 intervals arrange.
Described TFT on-off element comprises grid 307, active layer 308, source electrode 309 and drain electrode 310.The source electrode of the TFT on-off element in two sub-pixels of same data line both sides is connected on described same data line, and grid connects respectively in the pair of grid lines of both sides; Described grid 307 is integrally formed with described gate line 302, described active layer 308 be positioned on described grid 307 and described grid 307 insulated from each other with described active layer 308, described active layer 308 can be amorphous silicon layer.
Described source electrode 309 and drain electrode 310 are positioned at source-drain electrode layer, be formed on described active layer 308, described source electrode 309 is integrally formed with described data line 303, described pixel electrode 306 is formed on the passivation layer on source-drain electrode layer, described pixel electrode 306 is transparent conductive material, can be indium tin oxide.Described pixel electrode 306 is electrically connected with drain electrode 310 by via hole Q.Between described public electrode 305 and pixel electrode 306, form horizontal component of electric field and drive liquid crystal to rotate, a pair of pixel electrode/public electrode pivot region is called hurdle.Described public electrode 305 overlaps with described data line 303, and described public electrode 305 covers described data line 303.Concentric line 312, described concentric line 312 is positioned at same layer with described gate line 302, and described concentric line 312 is insulated from each other and overlapping with described drain electrode 310, and described concentric line 312 is insulated from each other and overlapping with described pixel electrode 306.
In the present embodiment, first pixel electrode and public electrode in the first sub-pixel 304a are described.In the first sub-pixel 304a, the number that can select to arrange public electrode 305 is 3, as shown in Figure 3, accordingly, in each sub-pixel 304a, can select to arrange 3 pixel electrodes 306, because one of them public electrode 305 is overlapping with data line 303, therefore, the number on the hurdle in the first sub-pixel 304a is 5.
In the present embodiment, the number of public electrode 305 and pixel electrode 306 is 3, thereby the number that obtains described hurdle is 5.Technical scheme of the present invention is not limited to this, and for example, the number of public electrode and pixel electrode can select to be 2, and the number on described hurdle is 3, if the number of public electrode and pixel electrode is selected to be 4, the number on described hurdle is 7.Equally, in the second sub-pixel 304b, described pixel electrode 306 can arrange with reference to the first sub-pixel 304a with public electrode 305.
In the present embodiment, described TFT is bottom gate thin film transistor, and in other embodiments of the invention, described TFT can be also top gate type thin film transistor, and described grid is positioned at the top of described active layer, and in addition, described active layer can be polysilicon layer.
Hence one can see that, and technical scheme according to the present invention is by bigrid the connect up public electrode and the pixel electrode that set, and the number on described hurdle is odd number, in actual applications, in the time that the number on hurdle is odd number, the choice of design parameter is larger, thereby has reduced the manufacture difficulty of engineering.
Embodiment bis-
Embodiment bis-is with the difference of embodiment mono-, between the first sub-pixel and the second sub-pixel, is provided with concentric line.Fig. 4 is the vertical view of the array base-plate structure of the IPS mode LCD of memory capacitance improvement design in embodiment bis-.Fig. 5 be in Fig. 4 the first sub-pixel along the sectional view of B-B direction.
Below in conjunction with Fig. 4 and Fig. 5, the array base-plate structure in the present embodiment is described.
Described array base palte comprises substrate 401, be formed on the multipair gate line 402 on described substrate 401, every pair of described gate line 402 comprises first grid polar curve 402a parallel to each other and second gate line 402b, be formed on many data lines 403 on described TFT substrate, with the vertical setting of described multipair gate line 402 and insulated from each other, intersect by described multipair gate line 402 and described many data lines 403 the multiple pixels 404 that limit, every row pixel 404 is corresponding to a pair of described gate line and be sandwiched between described pair of grid lines, each described pixel 404 comprises the first sub-pixel 404a and the second sub-pixel 404b, each described the first sub-pixel 404a and described the second sub-pixel 404b comprise TFT on-off element, the public electrode 405 of pectination and the pixel electrode 406 of pectination, described pixel electrode 406 and described public electrode 405 intervals arrange.Described TFT on-off element comprises grid 407, active layer 408, source electrode 409 and drain electrode 410.Described grid 407 is integrally formed with described gate line 402, described source electrode 409 is integrally formed with described data line 403, described grid 407 is insulated from each other with described active layer 408, between described grid 407 and active layer 408, gate insulation layer 411 is set, described gate insulation layer 411 can by chemical vapor deposition or physical vapour deposition (PVD) form monox or silicon nitride individual layer or comprise monox and silicon nitride in the multilayer of one deck at least, described active layer 408 can be amorphous silicon layer, described source electrode 409 and drain electrode 410 are positioned at source-drain electrode layer and are positioned on described active layer 408, on described source-drain electrode layer, passivation layer 412 is set.
Described pixel electrode 406 and described public electrode 405 are positioned on described passivation layer 412, and described pixel electrode 406 and public electrode 405 are transparent conductive material, can be indium tin oxide.Described pixel electrode 406 can be electrically connected with drain electrode 410 by via hole K.Between described public electrode 405 and pixel electrode 406, form horizontal component of electric field and drive liquid crystal to rotate, a pair of pixel electrode/public electrode pivot region is called hurdle.Described public electrode 405 overlaps with described data line 403, and described public electrode 405 covers described data line 403.
The first auxiliary capacitor substrate 414a and the second auxiliary capacitor substrate 414b, described the first auxiliary capacitor substrate 414a, is not communicated with between described the first auxiliary capacitor substrate 414a and described the second auxiliary capacitor substrate 414b.Described the first auxiliary capacitor substrate 414a and described the second auxiliary capacitor substrate 414b are and the metal of described grid 407 with layer to comprise at least one in molybdenum (Mo), chromium (Cr), aluminium (Al), silver (Ag), titanium (Ti), tantalum (Ta) and tungsten (W).Described the first auxiliary capacitor substrate 414a and the second auxiliary capacitor substrate 414b are all electrically connected by via hole L with drain electrode 410 respectively.Because described drain electrode 410 is electrically connected with described pixel electrode 406, so the current potential of described the first auxiliary capacitor substrate 414a and the second auxiliary capacitor substrate 414b all equates with the current potential of described pixel electrode 406.
The memory capacitance of the liquid crystal display of the present embodiment comprise be formed at the first memory capacitance Cs1 between described concentric line 413 and described pixel electrode 406 and be formed at described concentric line 413 and described auxiliary capacitor substrate between the second memory capacitance Cs2, be formed between concentric line 413 and the first auxiliary capacitor substrate 414a at the second memory capacitance Cs2 described in the first sub-pixel 404a, be formed between concentric line 413 and the second auxiliary capacitor substrate 414b at the second memory capacitance Cs2 described in the second sub-pixel 404b.
In the present embodiment, described TFT is bottom gate thin film transistor, and in other embodiments of the invention, described TFT can be also top gate type thin film transistor, and described grid is positioned at the top of described active layer, and in addition, described active layer can be polysilicon layer.
In addition, in the present embodiment, concentric line and pixel electrode have overlapping, and in other embodiments of the invention, concentric line and pixel electrode can not have overlapping yet.
In addition, in the present embodiment, concentric line and pixel electrode have overlapping, and in the middle of two sub-pixels, auxiliary capacitor substrate are set.In other embodiments of the invention, can not establish auxiliary capacitor substrate, memory capacitance is only present between concentric line and pixel electrode.Or concentric line and pixel electrode do not have overlapping, memory capacitance is only present between concentric line and auxiliary capacitor substrate.
By bigrid wiring in the present embodiment, concentric line is arranged between the first sub-pixel and the second sub-pixel, and the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are set, when can increasing the aperture opening ratio of liquid crystal display, form memory capacitance.In addition, in bigrid wiring by pixel electrode and public electrode are overlapped, thereby can obtain the pattern-driven aperture opening ratio that simultaneously increases of odd number hurdle IPS.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (11)
1. a liquid crystal display for IPS pattern, comprising:
TFT substrate;
Be formed on the multipair gate line on described TFT substrate, every pair of described gate line comprises first grid polar curve and second gate line parallel to each other;
Be formed on many data lines on described TFT substrate, with vertical setting of described multipair gate line;
Multiple pixels, are intersected and are limited by described multipair gate line and described many data lines, and every row pixel is corresponding to a pair of described gate line and be sandwiched between described pair of grid lines;
Each described pixel comprises the first sub-pixel and the second sub-pixel;
Each described sub-pixel comprises the public electrode of TFT on-off element, pectination and the pixel electrode of pectination, and described pixel electrode and described public electrode interval arrange;
The source electrode of the TFT on-off element in two sub-pixels of same data line both sides is connected on described same data line, and grid connects respectively in the pair of grid lines of both sides;
A pair of pixel electrode and public electrode pivot region are called hurdle, and the number on the hurdle in described the first sub-pixel and described the second sub-pixel is odd number.
2. liquid crystal display as claimed in claim 1, is characterized in that, in each pixel, and the adjacent setting of pixel electrode of described the first sub-pixel and the second sub-pixel.
3. liquid crystal display as claimed in claim 1, is characterized in that,
Between the first sub-pixel in each described pixel and the second sub-pixel, be provided with concentric line,
Described concentric line has overlapping with the pixel electrode of two described sub-pixels respectively.
4. liquid crystal display as claimed in claim 3, is characterized in that, also comprises the first auxiliary capacitor substrate and the second auxiliary capacitor substrate, and described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are with layer with the grid of described TFT switch element; Described the first auxiliary capacitor substrate is connected with the drain electrode of the TFT switch element in described the first sub-pixel, described the second auxiliary capacitor substrate is connected with the drain electrode of the TFT switch element in described the second sub-pixel, and described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are all overlapping with described concentric line.
5. liquid crystal display as claimed in claim 4, is characterized in that, described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are and the grid of the described TFT switch element metal level with layer.
6. liquid crystal display as claimed in claim 4, is characterized in that, forms the first memory capacitance between described concentric line and pixel electrode, between described concentric line and auxiliary capacitor substrate, forms the second memory capacitance.
7. liquid crystal display as claimed in claim 4, is characterized in that, described the first auxiliary capacitor substrate and the second auxiliary capacitor substrate are not communicated with.
8. liquid crystal display as claimed in claim 1, is characterized in that: described concentric line is and the source-drain electrode of the described TFT switch element metal level with layer.
9. liquid crystal display as claimed in claim 1, also comprises the passivation layer being formed on TFT substrate, it is characterized in that, and the same layer of described pixel electrode and public electrode, and be all formed on the passivation layer of described pixel.
10. liquid crystal display as claimed in claim 1, is characterized in that, described data line is all covered by described public electrode.
11. liquid crystal display as claimed in claim 1, is characterized in that, the number on described hurdle is 3～7.
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| WO2019080596A1 (en) * | 2017-10-24 | 2019-05-02 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US11527556B2 (en) | 2017-10-24 | 2022-12-13 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| JP2020034748A (en) * | 2018-08-30 | 2020-03-05 | 株式会社ジャパンディスプレイ | Liquid crystal display |
| JP7191596B2 (en) | 2018-08-30 | 2022-12-19 | 株式会社ジャパンディスプレイ | liquid crystal display |
| WO2020082543A1 (en) * | 2018-10-23 | 2020-04-30 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| JP2022503257A (en) * | 2018-10-25 | 2022-01-12 | 京東方科技集團股▲ふん▼有限公司 | Array board, display panel and display device |
| JP7390895B2 (en) | 2018-10-25 | 2023-12-04 | 京東方科技集團股▲ふん▼有限公司 | Array substrates, display panels and display devices |
| WO2020103774A1 (en) * | 2018-11-19 | 2020-05-28 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| US11215890B2 (en) * | 2018-11-19 | 2022-01-04 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate, display panel and display device |
| CN111583841A (en) * | 2020-04-27 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel inspection method and device and electronic equipment |
| US11907626B2 (en) | 2020-04-27 | 2024-02-20 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method, device, and electronic apparatus of inspecting display panel |
| WO2023221200A1 (en) * | 2022-05-16 | 2023-11-23 | 广州华星光电半导体显示技术有限公司 | Display panel |
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