CN106129005A - The preparation method of grid - Google Patents
The preparation method of grid Download PDFInfo
- Publication number
- CN106129005A CN106129005A CN201610828387.9A CN201610828387A CN106129005A CN 106129005 A CN106129005 A CN 106129005A CN 201610828387 A CN201610828387 A CN 201610828387A CN 106129005 A CN106129005 A CN 106129005A
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- work function
- regulating course
- function regulating
- layer
- dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides the preparation method of a kind of grid, including: Semiconductor substrate is provided；The dielectric layer of stacking, high-k dielectric layer, work function regulating course, barrier layer and polysilicon layer is formed successively on the surface of described Semiconductor substrate；Etch described polysilicon layer and described barrier layer, expose part described work function regulating course；The surface of described work function regulating course is carried out nitrogen treatment；Etch described work function regulating course, described high-k dielectric layer and described dielectric layer, form grid structure.In the present invention, after work function regulating course is come out by etches polycrystalline silicon layer and barrier layer, the surface of work function regulating course is carried out nitrogen treatment so that the surface of work function regulating course forms the structure of densification, prevent moisture from entering work function regulating course, thus improve the performance of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly relate to the preparation method of a kind of grid.
Background technology
In prepared by CMOS transistor device and circuit, along with development and the crucial chi of CMOS integrated circuit fabrication process
Very little reduces, due to SiO2The reduction of gate oxide dielectric thickness makes grid leakage current increase, simultaneously in order to avoid polysilicon
The depletion effect of grid, HKMG (high k metal gate) technique becomes main flow, especially below 28nm technique node.
Owing to the threshold voltage of NMOS with PMOS is different, NMOS and PMOS needs to use different work function regulating courses, gold
The forming process belonging to grid (metal gate) can be divided into gate first and gate last.Wherein, gate first technique
Simply, but work function regulating course easily absorbs the moisture in follow-up cleaning process, affects device performance.
Summary of the invention
It is an object of the invention to provide the preparation method of grid, solve work function regulating course in prior art and absorb moisture
Affect the technical problem of device performance.
For solving above-mentioned technical problem, the present invention provides the preparation method of a kind of grid, including:
Semiconductor substrate is provided；
The dielectric layer of stacking, high-k dielectric layer, work function regulating course, resistance is formed successively on the surface of described Semiconductor substrate
Barrier and polysilicon layer；
Etch described polysilicon layer and described barrier layer, expose part described work function regulating course；
The surface of described work function regulating course is carried out nitrogen treatment；
Etch described work function regulating course, described high-k dielectric layer and described dielectric layer, form grid structure.
Optionally, described Semiconductor substrate has mutually isolated first area and second area, and described work function regulates
Layer includes that the first work function regulating course being positioned on described first area and the second work function being positioned on described second area are adjusted
Ganglionic layer, the step forming described first work function regulating course and described second work function regulating course includes:
The first oxide membranous layer is formed on the surface of described high-k dielectric layer；
Remove described first oxide membranous layer on described second area；
Forming the second oxide membranous layer, described second oxide membranous layer covers described second area and described first oxide
Film layer；
Second oxide membranous layer described in cmp and described first oxide membranous layer, in the institute of described first area
State and in high-k dielectric layer, form the first work function regulating course, the described high-k dielectric layer of described second area is formed the second work content
Number regulating course.
Optionally, described first area is used for being formed NMOS, and described second area is used for being formed PMOS, described first area
And separated by shallow trench between described second area.
Optionally, the material of described first work function regulating course is lanthana, the thickness of described first work function regulating course
For
Optionally, the material of described second work function regulating course is aluminium oxide, the thickness of described second work function regulating course
For
Optionally, while etching described polysilicon layer and described barrier layer, also etch described work function regulating course, expose
Go out the described high-k dielectric layer of part.
Optionally, use the mixed gas containing nitrogen and ammonia that described work function regulating course is carried out a heat treatment process,
The temperature carrying out heat treatment process employing is 600 DEG C～900 DEG C.
Optionally, use the plasma of nitrogen, ammonia and hydrogen that the surface of described work function regulating course is nitrogenized
Process.
Optionally, the material of described dielectric layer is silicon oxynitride, and the thickness of described dielectric layer is
Optionally, the material of described high-k dielectric layer is hafnium oxide, and the thickness of described high-k dielectric layer is
Optionally, the material on described barrier layer is titanium nitride, and the thickness on described barrier layer is
Compared with prior art, in the preparation method of the grid that the present invention provides, etches polycrystalline silicon layer and barrier layer are by merit
After function regulating course comes out, the surface of work function regulating course is carried out nitrogen treatment so that the surface of work function regulating course
Form fine and close structure, prevent moisture from entering work function regulating course, thus improve the performance of device.
Accompanying drawing explanation
Fig. 1 is the flow chart of grid preparation method in one embodiment of the invention；
Fig. 2 is the structural representation forming high-k dielectric layer in one embodiment of the invention；
Fig. 3 is the structural representation forming the first oxide membranous layer in one embodiment of the invention；
Fig. 4 is the structural representation forming the second oxide membranous layer in one embodiment of the invention；
Fig. 5 is to form the first work function regulating course and the structural representation of the second work function regulating course in one embodiment of the invention
Figure；
Fig. 6 is formation group top layer and the structural representation of polysilicon layer in one embodiment of the invention；
Fig. 7 is etches polycrystalline silicon layer and the structural representation on barrier layer in one embodiment of the invention；
Fig. 8 is the structural representation carrying out nitrogen treatment in one embodiment of the invention；
Fig. 9 is the structural representation forming grid in one embodiment of the invention；
Figure 10 is the structural representation carrying out nitrogen treatment in another embodiment of the present invention.
Detailed description of the invention
Below in conjunction with schematic diagram, the preparation method of the grid of the present invention is described in more detail, which show this
The preferred embodiment of invention, it should be appreciated that those skilled in the art can revise invention described herein, and still realizes this
The advantageous effects of invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art, and does not make
For limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make to due to the fact that unnecessary details and chaotic.Will be understood that opening in any practical embodiments
In Faing, it is necessary to make a large amount of implementation detail to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, an embodiment change into another embodiment.Additionally, it should think that this development is probably complexity and consuming
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
The core concept of the present invention is, it is provided that grid preparation method in, etches polycrystalline silicon layer and barrier layer are by merit
After function regulating course comes out, the surface of work function regulating course is carried out nitrogen treatment so that the surface of work function regulating course
Form fine and close structure, prevent moisture from entering work function regulating course, thus improve the performance of device.
Being described in detail the preparation method of the grid of the present invention below in conjunction with accompanying drawing, Fig. 1 is grid preparation method
Flow chart, Fig. 2～Fig. 9 is the structural representation that each step is corresponding, concrete, and the preparation method of grid comprises the steps:
First, with reference to shown in Fig. 2, perform step S1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 can be
The substrat structures known in those skilled in the art such as silicon substrate, germanium silicon substrate, carbon silicon substrate, SOI substrate.Described quasiconductor serves as a contrast
Having mutually isolated first area 110 and second area 120, wherein, described first area 110 is used for being formed at the end 100
Nmos pass transistor, described second area 120 is used for being formed PMOS transistor, described first area 110 and described second area 120
Between isolated by fleet plough groove isolation structure 130.Certainly, other embodiments of the present invention can also be: first area 110 is used
In forming PMOS, second area 120 is used for forming NMOS, is actually needed the setting carried out according to this, and this is refused by the present invention
Limit.
Perform step S2, form the dielectric layer of stacking, high-k dielectric layer, merit successively on the surface of described Semiconductor substrate 100
Function regulating course, barrier layer and polysilicon layer.
Concrete, first, with reference to shown in Fig. 2, described Semiconductor substrate 100 forms dielectric layer 140 and high-k dielectric layer
150, the material of described dielectric layer 140 is silicon oxynitride, for isolation will be formed between Semiconductor substrate 100 and grid,
The thickness of described dielectric layer 140 isSuch as, Described high-k dielectric layer 150
Material be hafnium oxide, as gate dielectric layer, the thickness of described high-k dielectric layer 150 isSuch as,
Then, forming work function regulating course in described high-k dielectric layer 150, described work function regulating course includes being positioned at institute
State the first work function regulating course on first area 110 and be positioned at the second work function regulating course of described second area 120.This reality
Executing in example, the concrete steps forming described first work function regulating course and described second work function regulating course include the following:
With reference to shown in Fig. 3, form the first oxide membranous layer 160, described first oxygen on the surface of described high-k dielectric layer 150
Compound film layer 160 is for forming the first work function regulating course of nmos pass transistor.In the present embodiment, described first oxide membranous layer
The material of 160 is the one in Co, Ni, Cu, Pt, Ta, Ni, Hf, Ti, Al or its compound, it is preferred that the first oxide membranous layer
The material oxidation lanthanum of 160, thus the lanthana of the material of described first work function regulating course 160.
With reference to shown in Fig. 4, etch described first oxide membranous layer 160, remove described first on described second area 120
Oxide membranous layer 160, thus the high-k dielectric layer 150 on second area 120 is come out.
Afterwards, with continued reference to shown in Fig. 4, sealing coat is formed on the surface of described first oxide membranous layer 160 and sidewall
170, and form the second oxide membranous layer 180, described second oxide membranous layer 180 covers described second area 120 and described
Sealing coat 170 on monoxide film layer 160, sealing coat 170 is for by the first oxide membranous layer 160 and the second oxide membranous layer
180 keep apart, and described sealing coat 170 can be silicon oxide, silicon nitride etc..Wherein, described second oxide membranous layer 180 is used for
Formed PMOS transistor the second work function regulating course, the material of described second oxide membranous layer 180 is Co, Ni, Cu, Pt, Ta,
One in Ni, Hf, Ti, Al or its compound, it is preferred that described second oxide membranous layer 180 is for for aluminium oxide, thus institute
The material stating the second work function regulating course 181 is aluminium oxide.
Again, with reference to shown in Fig. 5, the second oxide membranous layer 180, described sealing coat 170 and institute described in cmp
State the first oxide membranous layer 160, the described high-k dielectric layer 150 of described first area 110 is formed the first work function regulating course
161, the described high-k dielectric layer 150 of described second area 120 is formed the second work function regulating course 181.Wherein, described
The thickness of one work function regulating course 161 isSuch as,Deng, described second work content
The thickness of number regulating course 181 isSuch as,Deng.
Afterwards, with reference to shown in Fig. 6, formation group top on the first work function regulating course 161 and the second work function regulating course 181
Layer 190, in the present embodiment, the material on described barrier layer 190 is titanium nitride, for preventing the electrode on upper strata from spreading downwards, described
The thickness on barrier layer 190 isSuch as, Described barrier layer 190 is formed many
Crystal silicon layer 210, the thickness of described polysilicon layer 210 is
With reference to shown in Fig. 7, performing step S3, the photoresistance forming patterning on described polysilicon layer 210 (does not shows in figure
Go out), polysilicon layer 210 and described barrier layer 190 described in the photoresistance of patterning as mask etching, thus expose described first
Work function regulating course 161 and the second work function regulating course 181.
Then, with reference to shown in Fig. 8, perform step S4, described first work function regulating course 161 and the second work function are regulated
The surface of layer 181 carries out nitrogen treatment.In the present invention, the mixed gas containing nitrogen and ammonia can be used described first work content
Number regulating course 161 and described second work function regulating course 181 carry out a heat treatment process, and the temperature used in heat treatment process is
600 DEG C～900 DEG C, such as, 700 DEG C, 800 DEG C, 850 DEG C etc..Certainly, can also use in other embodiments of the invention
Plasma etching processes described first work function regulating course 161 and the second work function regulating course 181, such as, uses nitrogen, ammonia
And the surface of described first work function regulating course 161 and the second work function regulating course 181 is nitrogenized by the plasma of hydrogen
Process.It should be noted that the surface of the first work function regulating course 161 and the second work function regulating course 181 is carried out at nitridation
After reason, the surface of the first work function regulating course 161 and the second work function regulating course 181 forms nitride structure so that the first merit
The surface of function regulating course 161 and the second work function regulating course 181 forms the structure of densification, prevents moisture from entering the first work function
Regulating course 161 and the second work function regulating course 181, thus improve the performance of device.
With reference to shown in Fig. 9, perform step S5, etch described first work function regulating course 161, described second work function regulation
Layer 181, described high-k dielectric layer 150 and described dielectric layer 140, form grid knot in described first area and second area respectively
Structure.
Additionally, in other embodiments of the invention, while etching described polysilicon layer 210 and described barrier layer 190,
Also etch described first work function regulating course 161 and the second work function regulating course 181, expose the described high-k dielectric layer of part
150 so that when the first work function regulating course 161 and the second work function regulating course 181 are carried out nitrogen treatment, the first work function
The sidewall of regulating course 161 and the second work function regulating course 181 forms the structure of densification.Further, in order to the first work function is being adjusted
During ganglionic layer 161 and the second work function regulating course 181 carry out nitrogen treatment, high-k dielectric layer will not be produced damage, this reality
Execute and example uses heat treatment process the first work function regulating course and the second work function regulating course are carried out nitrogen treatment.
In sum, in the preparation method of the grid that the present invention provides, work function is adjusted by etches polycrystalline silicon layer and barrier layer
After ganglionic layer comes out, the surface of work function regulating course is carried out nitrogen treatment so that the surface of work function regulating course is formed and causes
Close structure, prevents moisture from entering work function regulating course, thus improves the performance of device.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. the preparation method of a grid, it is characterised in that including:
Semiconductor substrate is provided；
The dielectric layer of stacking, high-k dielectric layer, work function regulating course, barrier layer is formed successively on the surface of described Semiconductor substrate
And polysilicon layer；
Etch described polysilicon layer and described barrier layer, expose part described work function regulating course；
The surface of described work function regulating course is carried out nitrogen treatment；
Etch described work function regulating course, described high-k dielectric layer and described dielectric layer, form grid structure.
2. the preparation method of grid as claimed in claim 1, it is characterised in that described Semiconductor substrate has mutually isolated
First area and second area, described work function regulating course include the first work function regulating course of being positioned on described first area and
The the second work function regulating course being positioned on described second area, forms described first work function regulating course and described second work function
The step of regulating course includes:
The first oxide membranous layer is formed on the surface of described high-k dielectric layer；
Remove described first oxide membranous layer on described second area；
Forming the second oxide membranous layer, described second oxide membranous layer covers described second area and described first oxidation film
Layer；
Second oxide membranous layer described in cmp and described first oxide membranous layer, at the described height of described first area
Form the first work function regulating course on k dielectric layer, the described high-k dielectric layer of described second area is formed the second work function and adjusts
Ganglionic layer.
3. the preparation method of grid as claimed in claim 2, it is characterised in that described first area is used for being formed NMOS, institute
State second area for forming PMOS, separated by shallow trench between described first area and described second area.
4. the preparation method of grid as claimed in claim 3, it is characterised in that the material of described first work function regulating course is
Lanthana, the thickness of described first work function regulating course is
5. the preparation method of grid as claimed in claim 3, it is characterised in that the material of described second work function regulating course is
Aluminium oxide, the thickness of described second work function regulating course is
6. the preparation method of grid as claimed in claim 1, it is characterised in that etch described polysilicon layer and described barrier layer
While, also etch described work function regulating course, expose the described high-k dielectric layer of part.
7. the preparation method of the grid as described in claim 1 or 6, it is characterised in that use containing nitrogen and the gaseous mixture of ammonia
Body carries out a heat treatment process to described work function regulating course, and the temperature carrying out heat treatment process employing is 600 DEG C～900 DEG C.
8. the preparation method of grid as claimed in claim 1, it is characterised in that use nitrogen, ammonia and the plasma of hydrogen
Body carries out nitrogen treatment to the surface of described work function regulating course.
9. the preparation method of grid as claimed in claim 1, it is characterised in that the material of described dielectric layer is silicon oxynitride,
The thickness of described dielectric layer is
10. the preparation method of grid as claimed in claim 1, it is characterised in that the material of described high-k dielectric layer is oxidation
Hafnium, the thickness of described high-k dielectric layer is
The preparation method of 11. grids as claimed in claim 1, it is characterised in that the material on described barrier layer is titanium nitride, institute
The thickness stating barrier layer is
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| CN201610828387.9A CN106129005A (en) | 2016-09-18 | 2016-09-18 | The preparation method of grid |
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| CN201610828387.9A CN106129005A (en) | 2016-09-18 | 2016-09-18 | The preparation method of grid |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000471A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
| US11894374B2 (en) | 2021-07-19 | 2024-02-06 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| CN101421839A (en) * | 2005-04-21 | 2009-04-29 | 国际商业机器公司 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices |
| US20140097507A1 (en) * | 2012-01-04 | 2014-04-10 | United Microelectronics Corp. | Semiconductor Device Having a Metal Gate and Fabricating Method Thereof |
| CN105336598A (en) * | 2014-06-20 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of metal gate c semiconductor device and preparation method thereof |
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2016
- 2016-09-18 CN CN201610828387.9A patent/CN106129005A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101421839A (en) * | 2005-04-21 | 2009-04-29 | 国际商业机器公司 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices |
| US20140097507A1 (en) * | 2012-01-04 | 2014-04-10 | United Microelectronics Corp. | Semiconductor Device Having a Metal Gate and Fabricating Method Thereof |
| CN105336598A (en) * | 2014-06-20 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of metal gate c semiconductor device and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000471A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
| US11894374B2 (en) | 2021-07-19 | 2024-02-06 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20161116 |