CN1061202C - Video signal expansion and compression and computer graph and image overlapping device - Google Patents

Abstract

The present invention relates to a video signal expansion and compression and computer graph and image overlapping device which comprises a video signal expansion and compression buffer (1), a programmable image overlapping controller (2) and an automatic adjustment time sequence generator (3), wherein the video signal expansion and compression buffer is magnified or reduced according to expansion and compression coefficients; the programmable image overlapping controller uses the methods of controlling a key signal by a color and a visual window for together generating a control signal of image overlapping; moreover, the programmable image overlapping controller provides a programmable color key type and the field of defining the visual window; the automatic adjustment time sequence generator can refer a horizontal synchronous signal of a computer graph for automatically generating a needed pixel clock according to needed point number displayed by a video signal.

Description

Video signal expansion and with the device of computer graphic image overlap

The present invention relates to a kind of vision signal (Video) flexible (Scale) and with the device of computer graphic (Computer Graphics) image overlap.

The mode of video signal expansion is in the past amplified and when dwindling, in order to cooperate the sequential of input and output, the circuit that image dwindles must be made in before the video signal buffer handling.This method is before pixel (Pixel) data deposit buffer in, and circuit will be according to flexible demand, deposits in or loses certain pixel data.And relative, the image amplifying circuit of this method then must be made in after the video signal buffer, and before pixel was sent buffer, circuit will repeat to send present pixel data or jump to the pixel of starting writing according to flexible demand.Such way is too little for the elasticity in the image processing.If it is flexible for the second time then not too convenient to do original image again.And must use two cover circuit to handle the amplification of vision signal and dwindle, on circuit design and uneconomical.

And in vision signal and the overlapping processing of computer graphic, common way has two kinds at present.The one, shared image lattice (frame) buffer is directly filled out digitized video on the display-memory (Display Memory) at computer graphic by vision signal.Another kind then is to use the mode of operating key (Key) signal, and the overlapping effect of vision is caused with multiplexer in two image sources (vision signal and computer graphic).The former, it plans that in the display-memory of computer graphic certain zone deposits video signal data.Vision signal just sees through on the memory that certain video signal interface deposits data on the computer graphic to be planned.So when computer graphic was sent demonstration to image data, the vision signal image will be sent together along with the computer graphic image data.Use this practice, computer graphic just must provide video signal interface.So just must matching computer figure and video signal interface in the system design of vision signal.This just is subjected to the hardware configuration restriction in the development design of system and system cost is considered.And on the mode of using the operating key signal, the rule of knowing of doing is to send image data by computer graphic, transmits digital image data by the another one digital interface.System must provide operating key signal controlling multiplexer, reaches superimposed image.The method of commonly seen is that the data according to computer graphic produce the operating key signal, and its method has two kinds again.First kind is the mode of color key signals, and it is the pixel data of computer graphic relatively, if the color of pixel meets the pre-color of definition, then the image source is switched to the vision signal source.Otherwise, then switch to computer graphic.The method of another kind of control is the form key signals, and the position of its compared pixels is if the address of pixel meets the window area of definition, then display video signal data.Otherwise, then show the data of computer graphic.But these methods all have some shortcomings.The method of color key signals in the zone of display video signal not, if the pixel identical with pre-color arranged, can be replaced by vision signal (noise).And the method for form key signals but can make the form of vision signal be stacked in the top of computer graphic forever, makes some computer graphic form index (for example the arrow of slide-mouse indicates) be hidden under the form of vision signal.In addition, because these data must provide a digital interface to transmit these data by computer graphic in addition, and these digital interfaces have numerous standards and specification, and make the development of system face restriction and inconvenience.If computer graphic does not provide a digital interface in addition, single from the obtained data of computer graphic output, and be not easy to do the control of image overlap.Because it has only comprised level, the vertical synchronizing signal of the pixel data and the control monitor of simulation usually.And in order to provide computer graphic different resolutions, level, vertical synchronizing signal are not single specification.Simultaneously, this output does not provide pixel synchronous clock yet.Why up till now Here it is, still must provide a digital interface in addition again by computer graphic, and can't directly use the reason of its fan-out certificate.

The objective of the invention is to provide a kind of video signal expansion used in the multimedia computer and device overlapping of being highly suitable for computer graphic at the problems referred to above of the prior art.The mode that it is different from old video signal expansion structure and handles image overlap.

In this device, through flexible buffer vision signal is done and to be amplified or dwindle.Utilize image overlap controller and clock generator to receive the generation that video data that the computer graphic output sent and horizontal-drive signal are come the overlapping of control of video signal and computer graphic and vision signal pixel clock.

In flexible buffer, it has used adjustable address indicator device on output port, and mat address indicator device is skipped the address or the repeat to address (RA) of some pixel, skips or duplicates some pixel and reach dwindling or amplifying of vision signal.

In the image overlap controller, it has adopted the way of color key signals and form key signals simultaneously.Result by they produce determines the place that vision signal shows jointly on computer graphic.In addition in design, do not having under the situation of digital interface, analogue data form, suitable design color key signals and the ruling circuit of exporting at computer graphic of form key signals yet.In addition, the digital comparator that uses analog comparator to substitute in the past produces the color key signals.And in the control of form key signals, because the output of computer graphic does not comprise pixel clock, so and the position that can't learn computer graphic aspect current pixel.But the horizontal-drive signal of computer graphic and vision signal each other must be synchronously and both clock frequencies be under the situation of fixed ratio, can utilize the pixel clock of vision signal to extrapolate the present position of computer graphic pixel.So can be by the comparison that relatively replaces the computer graphic location of pixels of vision signal location of pixels.But under the uncertainty of no computer graphic pixel clock and horizontal-drive signal, be the clock that vision signal output is provided and the signal level synchronizing signal requirement synchronized with each other of aforementioned computer graphic and video, clock generator uses the design of phase-locked loop (phase lock loop), horizontal-drive signal with reference to computer graphic, and according to the level of the vision signal demand of counting, and calculate pixel clock and the horizontal-drive signal that produces vision signal.Vision signal is just according to these signals, and synchronous exports data, and form key signals controller just can be according to the action of these signal controlling form key signals in addition.

Use above-mentioned method, whole device can be with vision signal full screen or amplification or overlapping being presented on any resolution computer graphic of dwindling.And between vision signal and the computer graphic, only need this device is directly delivered in the output of computer graphic, and need not to provide in addition again digital interface.

A kind of video signal expansion device provided by the invention, for the vision signal that output one is stretched, it has flexible ratio value N/D, comprising:

Control device, it advances value signal in response to a resizing control signal so that produce an address of corresponding described flexible ratio value;

The OPADD pointer is advanced the pixel clock of a value signal and a vision signal in response to the address, for producing an OPADD;

One dual-ported memory, it stores a video signal digital pixel data, and, in response to OPADD, producing a flexible video signal digital pixel data, this flexible video signal digital pixel data is to should the magnification example being worth.

Objects and advantages of the present invention are by the description to most preferred embodiment will be more obvious with reference to the accompanying drawings.

Brief Description Of Drawings:

Fig. 1 is the functional-block diagram of apparatus of the present invention;

Fig. 2 is the functional-block diagram of the flexible buffer in apparatus of the present invention;

Fig. 3 is the functional-block diagram of the interior address control unit of the flexible buffer in apparatus of the present invention;

How the control of Fig. 4 read-me sets the value of interior each register of address control unit among Fig. 3;

Fig. 5 is the flow chart of the address corrected signal action in the flexible buffer in apparatus of the present invention;

Fig. 6 is the functional-block diagram of clock generator in apparatus of the present invention;

Fig. 7 is the functional-block diagram of image overlap controller in apparatus of the present invention.

In Fig. 1, device of the present invention accepts to simulate pixel data 111 and vertical and horizontal-drive signal 115,113, the superimposed image data 13 of outputting video signal and computer graphic then from computer graphic output 11.Processor by processor bus 15 with the action of the register in the control data writing station with control device.Processor can be any processor, and processor bus provides the control signal of data/address bus, address bus and read-write, for the processing of processor control data.In Fig. 1, it comprises a video signal decoder 10 that produces video signal digital pixel data 101; One video signal digital pixel data 101 made flexible flexible buffer 12; The video signal digital pixel data 121 that will stretch converts the transducer 18 of vision signal analog pixel data 181 to; A multiplexer 17 that is used for Switch Video signal imitation pixel data 181 and computer graphic analog pixel data 111; The image overlap controller 16 that control multiplexer 17 switches; And clock generator 14 that produces flexible vision signal pixel clock 143 and horizontal lock signal 141.

Video signal decoder 10 among Fig. 1 is sent out video signal digital pixel data 101 according to vision signal pixel clock signal 103, and flexible simultaneously buffer 12 also utilizes vision signal pixel clock 103 that data are write in dual-port (two ports) memory of the flexible buffer 12 of Fig. 2.Video signal level synchronizing signal 105 shows level in video signal decoder 10, is a time point that opens the beginning, and for the memory in the flexible buffer 12, is the initial point that opens of Data Position.So after 105 actions of video signal level synchronizing signal, first position of the dual-ported memory of video signal digital pixel data 101 from flexible buffer 12 begins to deposit.

When video signal digital pixel data 101 by being stored in after the memory in the flexible buffer 12 in regular turn, flexible buffer 12 just can be according to flexible vision signal pixel clock signal 143, and the video signal digital pixel data 121 that will stretch passes out to transducer 18 from memory.Form key signals 161 is used for guaranteeing that the flexible the first stroke data of video signal digital pixel data 121 in the vision signal form are that first position from memory is sent.In transducer 18,, just be sent to multiplexer 17 then according to the data of flexible vision signal pixel clock signal 143 with the data transaction one-tenth simulation of numeral.And another input source of multiplexer 17 is exactly computer graphic analog pixel data 111, utilizes the input source that switches multiplexer 17 just can overlap image data, and causes computer graphic and the overlapping visual effect of vision signal.

As for the switching of multiplexer 17, then be to control by image overlap controller 16.Computer graphic analog pixel data 111 also are used as the reference frame of control signal 163 simultaneously except as the input source of multiplexer 17.After computer graphic analog pixel data 111 are sent to image overlap controller 16, compare with predetermined (target) color, when both conform to, the color key signals action in the image overlap controller 16, but overlapping key signals might not move.As for the opportunity of overlapping key signals action, color key signals and form key signals in must image overlap controller 16 move simultaneously, and its is moved, and make multiplexer 17 switch to the demonstration of vision signal from the demonstration of computer graphic.The input signal of flexible vision signal pixel clock 143, horizontal lock signal 141 and the computer graphic vertical synchronizing signal 115 of image overlap controller 16 in the drawings, be used for controlling the form key signals exactly, it monitors the pixel position in display at present with these signals in image overlap controller 16, when if pixel drops in the vision signal form scope, then the form key signals will move, and influences the action of overlapping key signals 163.

Before having mentioned flexible vision signal pixel clock 143 and horizontal lock signal 141 is produced by clock generator 14.In order to make these two signals can be synchronous with computer graphic, it produces this two signals with reference to computer graphic horizontal-drive signal 113.

For this device elasticity in the use is provided, processor can see through the register in the flexible buffer 12 of processor bus 15 settings, image overlap controller 16 and the sequential generator 14.The amplification of the flexible 12 pairs of vision signals of buffer of these register may command or dwindle, the pre-color of the color key signals in the image overlap controller 16, form key signals form scope, and sequential generator 14 in the parameter of video signal level number of pixels.The explanation of these registers will be mentioned in the back.

This device is except producing the video signal decoder 10 of video signal digital pixel data 101, converts flexible video signal digital pixel data 121 to vision signal and simulates the transducer 18 of pixel data 181 and switch outside the multiplexer 17 of image data.The most important thing is that it has comprised that flexible buffer 12, image overlap controller 16 and clock generator 14 just can accomplish video signal expansion of this device and the function overlapping with computer graphic.

Fig. 2 is the functional-block diagram in the flexible buffer 32 of Fig. 1.Four function square frames in Fig. 2, have been comprised: dual-ported memory 20, Input Address pointer 22, OPADD pointer 24, and address Correction and Control device 26.

This dual-ported memory 20 is in order to deposit video signal digital pixel data 101, and it also utilizes it to do the work of vision signal image flexible 121 simultaneously except as vision signal and the computer graphic sync buffering device.This memory 20 provides an input port and output port, and the address that data 101 are input to memory 20 and export from memory 20 is respectively to be decided by Input Address pointer 22 and OPADD pointer 24.Though these two address indicator devices all are the addresses that is used to refer to data, because the demand difference is also different on the structure.In order to import the position of deposit data in continuous adjacent, so Input Address pointer 22 is to produce address indicator 221 with counter in design, with the vision signal pixel clock 103 tired values that increase address indicator device 22, input data 101 can be left on the continuous address in order.Use video signal level synchronizing signal 105 that the first stroke data of video signal level direction can be left on first address in the memory 20.But in the design of OPADD pointer 24, then be to use an accumulator (accumulator).After reading a pixel data at every turn, value 261 will be advanced in the address in the address control unit 26 and be added to OPADD pointer 24.But sometimes for adjusting flexible error, the address corrected signal 263 in the address control unit 26 can make OPADD pointer 24 advance except the increase address during to certain degree at deviation accumulation and also add 1 the value, the address that made next record data multi-hop.It is exactly to utilize this address of skipping some pixel to reach to skip some pixel and dwindle image.For the demonstration of normal (Normal), what then value 261 was advanced in the address is exactly 1, and address corrected signal 263 just is failure to actuate.As for the method that image amplifies, also be similar, only when doing pixel and read, the value that value 261 is advanced in the address is zero, just moves when the number of times that address corrected signal 263 duplicates in pixel reaches demand.The address of these control image expanding-contracting actions revises and address corrected signal 263 is produced by address control unit 26.The functional-block diagram of its inside is illustrated among Fig. 3.

In Fig. 3, two flexible buffers 12 of control are carried out outside the address correction and address corrected signal 263 of image expanding-contracting action, also have the action of a processor bus 15 for processor control address controller 26.

Four registers are arranged in Fig. 3.Storage device 30 storage address correction values 261 are advanced to be worth in the address, and it has determined OPADD pointer 24 each basic values that increase among Fig. 2.Reference register 34 is used for depositing and Yu value (Remains) adder 33 fiducial value relatively, the opportunity that its decision error is adjusted.Yu value summand (Remain Addend) register 36 is the basic values that add up of Yu value adder 33.Control register 31 then is that to set flexible function be to amplify (Scale up), dwindle (Scale down) or normal size.These several registers all are to be set by processor.Yu value adder 33 is adders of one three input in the drawings, it also is worth Yu addend register 36 and complement circuit 35 in addition and delivers to its two other input except output valve is feedback it to input when flexible vision signal pixel clock 143 is failure to actuate.Form key signals 161 content that is used for Yu is worth adder 33 resets to " 0 " in addition.Complement circuit 35 is complementary circuits, and it is used for getting the complement of reference register 34 contents at this.Effect is just as the value that cuts reference register 34 when Yu value adder 33 adds this complement.Address corrected signal 263, normal 311, dwindle 312, amplify signals such as 313 and receive comparator 32, complement circuit 35 and Yu value addend register 36 respectively, the action that is used for controlling it is whether.During action, value output is arranged, otherwise output " 0 ".

In Fig. 4, processor decides control to address control unit 26 according to the contraction-expansion factor of mark kenel (D/N), and processor reads the molecule (N) and the denominator (D) of contraction-expansion factor in 41.In 42, processor compares the size of molecule and denominator then.If denominator will amplify less than a minute subrepresentation image, heart palpus execution in step 46; If equal then represent that image is flexible, then execution in step 45; If less than, then for image dwindles, execution in step 43,44.After 46,45,43,44 steps execute.Processor is just given flexible buffer 12 task and is carried out the flexible work of image.At each form key signals 161 after, the OPADD pointer 24 of Fig. 2 and the Yu value adder 33 among Fig. 3 will be from initial values, and after each flexible vision signal pixel clock 143, the Yu value adder 33 of OPADD pointer 24 and Fig. 3 will be upgraded once, and address corrected signal 263 also can change according to the flow process of Fig. 5.The action that flexible buffer 12 just so goes round and begins again is modified up to the value of next register.

When normal the demonstration, processor advances the address of Fig. 3 to insert " 1 " in the value register 30 in the step 45 of Fig. 4, is set at normal (normal) then in control register 31.Normal signal 311 will make address corrected signal 263 be failure to actuate.So will make flexible buffer 12 when whenever sending a pixel data, OPADD pointer 24 adds one automatically, point to the address of next memory, so can deliver to the data of dual-ported memory 20 in the flexible buffer 12, send out completely from input port.

Dwindle for image, processor is in the step 43 of Fig. 4, with the denominator of contraction-expansion factor divided by molecule, advance in the value register 30 in the address that step 44 is deposited Fig. 3 with the quotient (Quotient) of gained then, numerical)remainder (remainder) is placed on Yu value addend register 36, the molecule of contraction-expansion factor is deposited in the reference register 34 again, and then control register 31 is set at dwindles, make flexible buffer 12 in the process of dwindling, except OPADD pointer 24 when sending pixel data at every turn, add the address and advance outside the value of value register 30, Yu value adder 33 also can add other value with numerical)remainder in the addend register 36 (short error of stretching).Had error just must adjust, so the value of Yu value adder 33 just must compare with reference register 34, this two number has produced address corrected signal 263 at comparator 32 after relatively, can be used to adjust the error in the telescopic process.Corrected signal 263 control flows in address are just as Fig. 5.Complement circuit 35 in Fig. 3 is the complements that are used for getting value in the reference register 34.Its objective is to make Yu value adder 33 when adding this value, as the value that deducts in the reference register 34, with the correction value of payment adjustment.

After being defined as dwindling, step 53 is the form key signals 161 of image overlap controller 16 in waiting for Fig. 1 just in Fig. 5, to prepare after flexible buffer 12 is sent pixel data and the adjustment error.Otherwise Yu value adder 33 just keeps null value, if form key signals action 161 just enters the value that step 57 compares Yu value adder 33 and reference register 34.If the error that the value of Yu value adder 33 adds up more than or equal to expression is enough to skip a pixel data and just enters step 572, set one of the address multi-hop that address corrected signal 263 makes pixel data, Yu value adder 33 deducts correction value simultaneously in the flexible error of this pixel data of adding simultaneously, if but the value of Yu value adder 33 is less, then expression is not enough to skip a pixel, then enter step 571, address corrected signal 263 is failure to actuate, Yu value adder 33 adds up into the error amount in the Yu value addend register 36 simultaneously, and then enters step 53.Repeat above-mentioned action, carry out the work of dwindling.

For the action of amplifying, the function of each function square frame among Fig. 3, similar with dwindling, but register 30,34,31,36 contents are inequality.After processor is judged as the action of amplification according to contraction-expansion factor, value register 30 is advanced in the address that it fills out Fig. 3 in the step 46 of Fig. 4 with " 0 ", the molecule of contraction-expansion factor is filled out Yu value addend register 36, denominator is filled out in the reference register 34, and then control register 31 is set at amplification.At this, the address is advanced value register 30 and is set at " 0 ", makes pixel data can repeat the data of last time.Determined by the number of times that denominator had subtracted by molecular energy as for the number of times that repeats, so numerical)remainder not enough in, remove and to make address indicator device 24 add to jump to the address of next pixel, again the value of denominator is added to Yu value adder 33, make the error of pen remain into next pixel data and go to handle, in Fig. 5, showed the flow chart of these actions.In Fig. 5, amplify just as dwindling the action of checking form key signals 161 in step 52, unless form key signals 161 actions, otherwise remain in the value that step 54 is worth adder 33 with Yu and to open initial value, in case after 161 actions of form key signals, just enter the value that step 56 compares Yu value adder 33 and reference register 34.If Yu value adder 33 is bigger, then address corrected signal 263 is failure to actuate, and makes the value of OPADD pointer 24 constant, and Yu value adder 33 adds the complement (just cutting the value in the reference register) of reference register 34 contents simultaneously.If but be that the value of reference register 34 is bigger in step 56, then enter step 562,263 actions of address corrected signal, make OPADD pointer 24 add one, Yu value adder 33 is removed and is deducted reference register 34 and add value in the Yu value addend register 36, controlling the number of times of next pixel repetition, and then gets back to step 52, repeat above-mentioned action, to carry out the action of amplifying.

In this device, use the adjustment of address difference and the method for error accumulation, the image that makes vision signal is evenly amplified or is dwindled when flexible.

Fig. 6 is the functional-block diagram of clock generator.It is the circuit of a phase-lock loop basically, the characteristics of its maximum are its phase places with reference to computer graphic horizontal-drive signal 113, produce flexible vision signal pixel clock 143 and horizontal lock signal 141 and make vision signal and computer graphic when overlapping demonstration, the vision signal full screen is presented on the computer graphic of any resolution.In Fig. 6, it accepts computer graphic horizontal-drive signal 113, and can see through the horizontal direction number of pixels that processor bus 15 is set vision signal by processor, produce flexible vision signal pixel clock 143 and horizontal lock signal 141 then with pixel clock and horizontal-drive signal as the flexible buffer 12 among Fig. 1, transducer 18 and image overlap controller 16.Voltage control oscillator 67 among the figure is oscillating waveform devices of being controlled by voltage, and the frequency of its vibration can speed changes along with the height of control voltage 651.The signal that produces removes when flexible vision signal pixel clock 143 is exported, also delivers to frequency divider 61 frequency divisions and produces horizontal lock signal 141.Can see through processor bus 15 and set the number that frequency divider 61 will remove.In this device, owing to make the horizontal signal of computer graphic and vision signal synchronous, and the horizontal signal 141 of vision signal is by producing after pixel clock 143 frequency divisions, so the divisor of frequency divider 61 just is made as the number of pixels of video signal level direction.The horizontal lock signal 141 that it produced is except that the horizontal signal that serves as vision signal, the phase place of also delivering to phase detectors 63 and computer graphic horizontal-drive signal 113 compares, through both phase differences, adjust the control voltage 651 of voltage control oscillator 67 and change its frequency, and the variation of frequency is feedback to phase detectors 63 phase difference is reduced, and both are tending towards synchronous and make it.But in the process of feedbacking, voltage control oscillator 67 can not be directly just controlled in the output 631 of phase detectors 63.Because still have some unnecessary signals in phase detectors 63 outputs 631, so will will send into voltage control oscillator 67 again after the unnecessary filtering signals through filter 65, so can produce correct flexible vision signal pixel clock 143 and the horizontal lock signal 141 synchronous with computer graphic horizontal-drive signal 113.

Had after correct stable flexible vision signal pixel clock 143 and the synchronous horizontal lock signal 141, this device just can carry out the control of image overlap.It has comprised two parts in Fig. 7, and one is color key signals controller 70, and another is a form key signals controller 78.The former mat simulates pixel data 111 with reference to computer graphic to be controlled, and the latter utilizes flexible vision signal pixel clock 143, horizontal lock signal 141 and computer graphic vertical synchronizing signal 115 to control.In the drawings, it has two output signals, form key signals 161 and overlapping key signals 163.Form key signals 161 is produced by form key signals controller 78, and it removes the actions that the overlapping key signals of sending with (AND) door 75 and color key (Color key) controller 70 163 of color key signals 711 common decisions is also delivered in the action deliver to the flexible vision signal output of flexible buffer 12 controls.Have only when color key signals 163 and form key signals 161 move simultaneously, just can make overlapping key signals 163 output actions with door, and the multiplexer 17 that switches Fig. 1 simulates pixel data to vision signal.

Though the former does not have directly connection with flexible vision signal pixel clock 143 and horizontal lock signal 141, but for the action that makes color key signals 711 can with the data close fit of vision signal, the horizontal signal of computer graphic and vision signal reaches synchronously that the pixel clock of computer graphic and vision signal is proportional also to remain essential.But pre-color R, G, the B-register in the processor mat processor bus 15 setting transducers 721,722,723 selected to control the color of color key signals 711, and set the scope of predetermined video signal form in the vision signal form register 79 in the drawings.In color key signals controller 70, it has received computer graphic and has simulated R, the G of pixel data 111, the data of B three compositions.Processor is set R, G, the B three composition analogue datas of pre-color in the register in transducer 721,722,723.For simplifying the design of analog comparator, these two data all integrate R, G, B three compositions through the adder 741,742 of simulation earlier.But adder may make different R, G, B color to arriving identical value, so selection at pre-color, must be unique color of adder output valve, R, G, B three compositions be under this design selection only to be arranged for " 0 " or complete black or white for " 1 " entirely.Therefore the selection of color key signals color at present has only complete deceiving and complete white two kinds.Because present selected pre-color is unique color of respective adders output valve in the color space (ColorSpace), to have adder 741 output valves only identical with adder 742 output valves so color key signals 711 will move.And this output valve corresponds to the color space also is unique color, and this color relation is the color of pre-color.As for other colors owing to can't correspond to the respective value of pre-color, so analog comparator 71 just can not make the action of color key signals.Analog comparator 71 in the drawings, it is the output valve of two adders 741,742 relatively.If two values meet, 711 actions of color key signals, otherwise color key signals 711 is failure to actuate.If but the control of color key signals 711 is to be compared by three R, G, each other analog comparator of B, controls color key signals 711 then jointly, then the selection of pre-color will be more, but just change complexity of relative design.

As for form key signals controller 78 aspects, it has comprised the vision signal form register 79 among Fig. 7, location counter 77 and vision signal form comparator 73.In vision signal form register 79, it has four registers to define upper left corner X, the Building Y mark of vision signal form respectively, reaches the high and wide of form.Under the situation that does not have the computer graphic pixel clock, can't learn the position of present display pixel, but synchronously and under the proportional situation of pixel clock of vision signal and computer graphic, the location of pixels that can compare vision signal is to replace the location of pixels of computer graphic at vision signal and computer graphic horizontal signal.So processor the location coordinate of vision signal form on computer graphic, and width, altitude conversion become the unit of vision signal pixel, fill out vision signal form register 79, and monitor the current pixel display position with flexible vision signal pixel clock 143, the horizontal lock signal 141 of vision signal.Having vertical synchronizing signal 115 only is still provided by computer graphic.In location counter 77 the insides horizontal direction counter and vertical direction counter are arranged, horizontal lock signal 141 has started the horizontal direction counter.The flexible vision signal pixel clock 143 of counting is just known the position of current pixel horizontal direction.Computer graphic vertical synchronizing signal 115 has started the vertical direction counter, and count level locking signal 141 just can be learnt the vertical direction position that pixel is present.The output valve of these two counters is exactly a vision signal location of pixels 771.In the drawings, these data 771 vision signal window area of being sent to vision signal form comparator 73 and vision signal form register 79 compares.At this, if the value position of vision signal location of pixels 771 in the zone of vision signal window definition, form key 161 will move.Otherwise form key signals 161 will be failure to actuate.The action of form key signals 161 has not only influenced among the figure has also controlled the action of flexible buffer 12 among Fig. 1 with door 75.Making overlapping key signals 163 to set up simultaneously at color key signals 711 and form key signals 161 with door 75 in Fig. 7 just can move, avoid color key signals and form key signals to control the shortcoming of image overlap separately.

Claims (9)

1, a kind of video signal expansion device, for the vision signal that output one is stretched, it has flexible ratio value N/D, comprises control device, it is characterized in that this video signal expansion device comprises:

Control device, it advances value signal in response to a resizing control signal so that produce an address of corresponding described flexible ratio value;

The OPADD pointer is advanced the pixel clock of a value signal and a vision signal in response to the address, for producing an OPADD;

One dual-ported memory, it stores a video signal digital pixel data, and, in response to OPADD, producing a flexible video signal digital pixel data, this flexible video signal digital pixel data is to should the magnification example being worth.

2, video signal expansion device as claimed in claim 1 is characterized in that, the generation of OPADD is further in response to an address corrected signal, and the accumulated roundoff error that is caused when flexible ratio value is during greater than a fiducial value, the action of address corrected signal.

3, video signal expansion device as claimed in claim 2, it is characterized in that, control device comprises a control register, itself and a bus link receive described resizing control signal one normal to produce, one dwindle or an amplifying signal, reach an address and advance value register, itself and described bus link to produce the address advances value signal.

4, video signal expansion device as claimed in claim 3, it is characterized in that, control device further comprises a reference register and a numerical)remainder addend register, this the two all link with bus, the numerical)remainder addend register has first input end reception and dwindles signal and one second input receiver address corrected signal, and reference register stores fiducial value.

5, video signal expansion device as claimed in claim 4 is characterized in that, when flexible ratio value is shown as when dwindling, the quotient of D/N is deposited in the address and advances value register, and the numerical)remainder of D/N deposits the numerical)remainder addend register in, and the N value deposits reference register in.

6, video signal expansion device as claimed in claim 4 is characterized in that, when flexible ratio value was shown as amplification, zero is deposited in the address advanced value register, and N deposits the numerical)remainder addend register in, and the D value deposits reference register in.

7, video signal expansion device as claimed in claim 4, it is characterized in that, control device further comprises the ones complement circuit, its output with a first input end and reference register links, reach one second its receiver address of input and advance value signal, and one the 3rd input receives amplifying signal.

8, video signal expansion device as claimed in claim 7, it is characterized in that, control device further comprises a numerical)remainder adder and a comparator, the output that the numerical)remainder adder has a first input end and complement circuit links, and one second input and the binding of numerical)remainder addend register one output, the numerical)remainder adder, in response to address corrected signal and flexible vision signal pixel clock signal, to export its value, the fiducial value of comparator benchmark register and the output of numerical)remainder adder, to produce the address corrected signal, comparator has an input and receives normal signal.

9, video signal expansion device as claimed in claim 1, it is characterized in that, the pixel clock of flexible vision signal is produced by a sequential generator, this clock generator, in response to number of pixels on a horizontal-drive signal of a computer graphic and the video signal level scan line that stretches, produce the pixel clock of vision signal.

Images