CN106094424A - Redundant pattern adding method with auxiliary figure with low resolution - Google Patents
Redundant pattern adding method with auxiliary figure with low resolution Download PDFInfo
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- CN106094424A CN106094424A CN201610585198.3A CN201610585198A CN106094424A CN 106094424 A CN106094424 A CN 106094424A CN 201610585198 A CN201610585198 A CN 201610585198A CN 106094424 A CN106094424 A CN 106094424A
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- redundant pattern
- low resolution
- redundant
- auxiliary
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
Abstract
The invention provides the redundant pattern adding method of a kind of band auxiliary figure with low resolution, including: first step: obtain original design figure and all design layout dodging layer, and marked the redundant area allowing to add redundant pattern in design layout by logical operations；Second step: use DRC instrument to add rectangle redundant pattern in redundant area in a computer；Third step: design layout is divided into multiple isolated area, in using computer to calculate each isolated area, design configuration is plus the areal concentration after rectangle redundant pattern；4th step: adjust the areal concentration of isolated area；5th step: use DRC instrument to add auxiliary figure with low resolution.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of band auxiliary figure with low resolution
Redundant pattern adding method.
Background technology
Under less technology node, redundant pattern as manufacturability design (design for manufactory,
DFM) important content, plays indispensable effect to the planarization of silicon chip surface, so reduce silicon chip surface concavo-convex not
The flat impact on lithographic process window.And ic manufacturing technology node constantly develops redundancy figure to less critical size
Shape is had higher requirement, and the thickness of such as depositing operation and figure girth also exist dependency, and girth is the longest, pattern side wall
Area is the biggest, and under identical sedimentary condition and time, deposit thickness can be the least, and therefore redundant pattern is when design and interpolation
Not only to consider its impact on flatening process, also to consider that the unit are girth making it is tried one's best close to design drawing simultaneously
Shape.
Generally, in order to save software and hardware resources and shorten mask plate publication time, redundant pattern does not the most do light
Close on correction (OPC)；Therefore to make it have enough lithographic process windows, the size of single redundant pattern is typically much deeper than
Design configuration；So that by contrast, the unit are girth of redundant pattern is much smaller than design configuration.Both unit ares
The huge contrast of girth can cause the inequality of domain zones of different deposit thickness, thus affects the homogeneity of device performance and controlled
Property.In the case of not changing the overall pattern density of redundant pattern, the size reducing single redundant pattern is to increase its unit plane
One of optimal path of long-pending girth.But in the case of not being OPC, the size reducing redundant pattern is possible to reduce it originally
The lithographic process window of body, even causes the defects such as photoresist lift off, affects product yield.It is thus desirable to consider in redundant pattern
Around add auxiliary figure with low resolution (sub resolution assist feature, SRAF) and improve its photoetching work
Skill window.
Adding auxiliary figure with low resolution is one of basic means improving key stratum design configuration lithographic process window.Secondary
The necessary being of resolution secondary graphics own is on mask plate, but owing to the size of itself is not reaching to the minimum of photoetching process
Resolution, thus without imaging on silicon chip, but its existence can change the optical environment of neighbouring design configuration, therefore just
Add auxiliary figure with low resolution on true position and can improve the lithographic process window of isolation pattern.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can be favourable
Redundant pattern adding method in the band auxiliary figure with low resolution of depositing operation and the control of product device performance.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that the redundancy figure of a kind of band auxiliary figure with low resolution
Shape adding method, including:
First step: obtain original design figure and all design layout dodging layer, and marked by logical operations
Design layout allows to add the redundant area of redundant pattern；
Second step: use DRC instrument to add rectangle redundancy figure in redundant area in a computer
Shape；
Third step: design layout is divided into multiple isolated area, uses computer to calculate in each isolated area
Design configuration is plus the areal concentration after rectangle redundant pattern；
4th step: adjust the areal concentration of isolated area；
5th step: use DRC instrument to add auxiliary figure with low resolution.
Preferably, dodging layer is to need the layer with redundant pattern holding predetermined relative location or mark layer.
Preferably, in the second step, the width of described rectangle redundant pattern is more than when layer design configuration is in current skill
The minima that under art node, design rule allows, and the width of described rectangle redundant pattern is being worked as less than when layer redundant pattern
The minima that under front technology node, design rule allows.
Preferably, in the second step, the distance between size and the rectangle redundant pattern of square redundant pattern meets
When layer redundant pattern design rule under current techniques node.
Preferably, in the 4th step, if the areal concentration of an isolated area is more than preset value, use design rule
Checking tool reduces the size of the rectangle redundant pattern of this isolated area；If the areal concentration of an isolated area is not more than
Preset value, use DRC instrument increases the size of the rectangle redundant pattern of this isolated area.
Preferably, the redundant pattern size after the 4th step adjusts and distance each other meet when layer redundancy figure
Shape design rule under current techniques node.
Preferably, in the 5th step, use DRC instrument in the both sides of redundant pattern long side direction respectively
Produce an auxiliary figure with low resolution.
Preferably, in the 5th step, produce a Sub-reso auxiliary in the centre position of redundant pattern long limit spacing
Figure.
Preferably, in the 5th step, control the width of auxiliary figure with low resolution and auxiliary figure with low resolution with
Minimum range between adjacent redundant figure so that auxiliary figure with low resolution will not become on silicon chip under the conditions of current photolithographic
Picture.
The present invention is creating the redundant pattern of band auxiliary figure with low resolution by domain logical operations, is substantially reduced list
The size of individual redundant pattern, increases the control of unit are girth, beneficially depositing operation and product device performance, protects simultaneously
Demonstrate,prove redundant pattern itself and still there is enough lithographic process windows.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the redundant pattern of band auxiliary figure with low resolution according to the preferred embodiment of the invention and adds
The flow chart of adding method.
Fig. 2 schematically shows the redundant pattern of band auxiliary figure with low resolution according to the preferred embodiment of the invention and adds
First schematic diagram of adding method.
Fig. 3 schematically shows the redundant pattern of band auxiliary figure with low resolution according to the preferred embodiment of the invention and adds
Second schematic diagram of adding method.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
The general step adding auxiliary figure with low resolution all completes in the domain OPC stage.Due to redundant pattern originally
Body is the repeated arrangement of simple graph (generally rectangular cross-section), it can be considered to use DRC instrument (design
Rule check, DRC) while redundant pattern is added, producing the auxiliary figure with low resolution of repeated arrangement about, i.e.
The lithographic process window of small size redundant pattern can be improved, OPC resource can be saved again, shorten mask plate publication time.
Fig. 1 schematically shows the redundant pattern of band auxiliary figure with low resolution according to the preferred embodiment of the invention and adds
The flow chart of adding method.
As it is shown in figure 1, the redundant pattern adding method of band auxiliary figure with low resolution according to the preferred embodiment of the invention
Including:
First step S1: obtain original design figure and all design layout dodging layer (keep off layers), and
The redundant area allowing to add redundant pattern (dummy) in design layout is marked by logical operations；
Wherein, dodge layer and refer to need the layer with redundant pattern holding predetermined relative location or mark layer, prevent redundancy figure
The addition of shape produces harmful effect to circuit or manufacturing process.
Second step S2: use DRC instrument to add rectangle redundancy figure in redundant area in a computer
Shape；Wherein, the width of described rectangle redundant pattern allows more than when layer design configuration design rule under current techniques node
Minima, and the width of described rectangle redundant pattern is less than when layer redundant pattern design rule under current techniques node
The minima allowed.Distance between size and the rectangle redundant pattern of rectangle redundant pattern meets when layer redundant pattern exists
Design rule under current techniques node.
Third step S3: design layout is divided into multiple isolated area, uses computer to calculate each isolated area
Interior design configuration is plus the areal concentration after rectangle redundant pattern；
4th step S4: adjust the areal concentration of isolated area；Wherein, if the areal concentration of an isolated area is more than
Preset value, use DRC instrument reduces the size of the rectangle redundant pattern of this isolated area；Whereas if one
The areal concentration of isolated area is not more than preset value, uses DRC instrument to increase the rectangle redundancy of this isolated area
The size of figure；Thus, make the areal concentration in each region close to preset value.Redundant pattern size after being adjusted and phase
Distance between Hu still conforms to when layer redundant pattern design rule under current techniques node.
5th step S5: use DRC instrument to add auxiliary figure with low resolution.
Such as, in the 5th step S5, use DRC instrument in the both sides of redundant pattern long side direction respectively
Produce an auxiliary figure with low resolution (auxiliary figure with low resolution), as shown in Figure 2.
Or, such as, in the 5th step S5, produce a Sub-reso in the centre position of redundant pattern long limit spacing
Secondary graphics, as shown in Figure 3.
In the 5th step S5, the width and the auxiliary figure with low resolution that control auxiliary figure with low resolution are superfluous with adjacent
Minimum range between complementary graph so that under the conditions of current photolithographic auxiliary figure with low resolution will not imaging on silicon chip, and
Redundant pattern can also be made to have enough lithographic process windows.
The present invention uses DRC instrument to create band auxiliary figure with low resolution by domain logical operations
Redundant pattern.Owing to the existence of auxiliary figure with low resolution ensure that small size redundant pattern itself still has enough photoetching
Process window, will not cause the defect such as pattern lacks and photoresist lift off.The redundant pattern that the present invention produces can break through works as layer
Redundant pattern design rule under current techniques node, it is achieved less size.Therefore keeping layout patterns density basic
In the case of identical, the redundant pattern produced due to the present invention is smaller, and its unit are girth increases, and reduces and sets
The difference of meter grapheme area girth, is more beneficial for the control of the most even device performance of depositing operation thickness.
<the first example>
First, it is thus achieved that 32nm technology node polysilicon layer (PO) original design figure and all design layout dodging layer,
And mark the region of permission addition polysilicon layer redundant pattern, referred to as redundant area in design layout by logical operations.
Wherein dodge layer to refer to need the layer with polysilicon layer redundant pattern holding certain relative position or mark layer, prevent polysilicon layer
The addition of redundant pattern produces harmful effect to circuit or manufacturing process.
Subsequently, DRC instrument is used to add rectangle polysilicon layer redundancy in redundant area in a computer
Figure, its width is 80nm, more than the polysilicon layer design configuration minima that design rule allows under 32nm technology node
40nm, less than polysilicon layer redundant pattern minima 120nm that design rule allows under 32nm technology node.Polysilicon layer is superfluous
The a length of 3um of complementary graph, the distance between the long limit of polysilicon layer redundant pattern is 240nm, and minimum range is 120nm, meets
Polysilicon layer redundant pattern design rule under 32nm technology node.
Hereafter, design layout is divided into the isolated area of substantial amounts of 80um*80um, uses computer to calculate each district
In territory, polysilicon layer design configuration is plus the areal concentration after polysilicon layer redundant pattern.If areal concentration is more than preset value
25%, use DRC instrument to reduce the size of polysilicon layer redundant pattern；Whereas if areal concentration is less than
25%, use DRC instrument to increase the size of redundant pattern, make the areal concentration in each region close to 25%.Warp
Cross the polysilicon layer redundant pattern size after adjusting and the condition described in the previous step to be met of distance each other.
Subsequently, DRC instrument is used to produce one respectively in the both sides of polysilicon layer redundant pattern long side direction
Width is the auxiliary figure with low resolution (auxiliary figure with low resolution) of 20nm, and auxiliary figure with low resolution is from adjacent polysilicon layer
Minimum range 70nm of redundant pattern, it is ensured that under the conditions of current photolithographic auxiliary figure with low resolution will not imaging on silicon chip,
And make polysilicon layer redundant pattern have enough lithographic process windows.
<the second example>
First, it is thus achieved that 45nm technology node metal level (M1) original design figure and all design layout dodging layer, and
The region allowing to add metal level redundant pattern in design layout, referred to as redundant area is marked by logical operations.Wherein
Dodge layer to refer to need the layer with metal level redundant pattern holding certain relative position or mark layer, prevent metal level redundant pattern
Addition circuit or manufacturing process are produced harmful effect.
Subsequently, DRC instrument is used to add rectangle metal level redundancy figure in redundant area in a computer
Shape, its width is 120nm, more than metal level design configuration minima 70nm that design rule allows under 45nm technology node,
Less than metal level redundant pattern minima 130nm that design rule allows under 45nm technology node.Metal level redundant pattern
A length of 2um, the distance between the long limit of metal level redundant pattern is 160nm, and minimum range is 140nm, meets metal level redundancy
Figure design rule under 45nm technology node.
Hereafter, design layout is divided into the isolated area of substantial amounts of 150um*150um, uses computer to calculate each
Region inner metal layer design configuration is plus the areal concentration after metal level redundant pattern.If areal concentration is more than preset value
42%, use DRC instrument to reduce the size of metal level redundant pattern；Whereas if areal concentration is less than 42%,
Use DRC instrument to increase the size of redundant pattern, make the areal concentration in each region close to 42%.Through toning
Metal level redundant pattern size after whole and the condition described in the previous step to be met of distance each other.
Subsequently, use DRC instrument wide the centre position of metal level redundant pattern long limit spacing generation one
Degree is the auxiliary figure with low resolution of 25nm, and auxiliary figure with low resolution from the minimum range of adjacent metal redundant pattern is
60nm, it is ensured that under the conditions of current photolithographic auxiliary figure with low resolution will not imaging on silicon chip, and make metal level redundancy figure
Shape has enough lithographic process windows.
The present invention is creating the redundant pattern of band auxiliary figure with low resolution by domain logical operations, is substantially reduced list
The size of individual redundant pattern, increases the control of unit are girth, beneficially depositing operation and product device performance, protects simultaneously
Demonstrate,prove redundant pattern itself and still there is enough lithographic process windows.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (9)
1. the redundant pattern adding method of a band auxiliary figure with low resolution, it is characterised in that including:
First step: obtain original design figure and all design layout dodging layer, and mark design by logical operations
Domain allows to add the redundant area of redundant pattern；
Second step: use DRC instrument to add rectangle redundant pattern in redundant area in a computer；
Third step: design layout is divided into multiple isolated area, uses computer to calculate design in each isolated area
Figure is plus the areal concentration after rectangle redundant pattern；
4th step: adjust the areal concentration of isolated area；
5th step: use DRC instrument to add auxiliary figure with low resolution.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1, it is characterised in that dodge
Layer is to need the layer with redundant pattern holding predetermined relative location or mark layer.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the second step, the width of described rectangle redundant pattern is more than when layer design configuration design rule under current techniques node
The minima allowed, and the width of described rectangle redundant pattern designs under current techniques node less than when layer redundant pattern
The minima that rule allows.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the second step, the distance between size and the rectangle redundant pattern of square redundant pattern meets when layer redundant pattern is being worked as
Design rule under front technology node.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the 4th step, if the areal concentration of an isolated area is more than preset value, DRC instrument is used to reduce this
The size of the rectangle redundant pattern of isolated area；If the areal concentration of an isolated area is not more than preset value, use sets
Meter rule checking tool increases the size of the rectangle redundant pattern of this isolated area.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
Redundant pattern size after the 4th step adjusts and distance each other meet when layer redundant pattern saves in current techniques
Design rule under Dian.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the 5th step, DRC instrument is used to produce a Sub-reso respectively in the both sides of redundant pattern long side direction
Secondary graphics.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the 5th step, produce an auxiliary figure with low resolution in the centre position of redundant pattern long limit spacing.
The redundant pattern adding method of band auxiliary figure with low resolution the most according to claim 1 and 2, it is characterised in that
In the 5th step, control between width and auxiliary figure with low resolution and the adjacent redundant figure of auxiliary figure with low resolution
Minimum range so that auxiliary figure with low resolution will not imaging on silicon chip under the conditions of current photolithographic.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107657115A (en) * | 2017-09-26 | 2018-02-02 | 上海华力微电子有限公司 | A kind of metal redundant pattern drawing method of raising CMP patterns |
| CN108573858A (en) * | 2018-05-21 | 2018-09-25 | 上海华力集成电路制造有限公司 | Improve the method for epitaxial growth uniformity |
| CN108763723A (en) * | 2018-05-23 | 2018-11-06 | 上海华力微电子有限公司 | A kind of redundant pattern adding method |
| CN109101756A (en) * | 2018-08-31 | 2018-12-28 | 上海华力微电子有限公司 | A kind of redundant pattern adding method |
| CN109459910A (en) * | 2018-11-22 | 2019-03-12 | 上海华力集成电路制造有限公司 | For the Sub-resolution assist features setting method of metal layer process hot spot |
| CN111596521A (en) * | 2020-05-25 | 2020-08-28 | 上海华力集成电路制造有限公司 | Layout structure for improving exposure resolution and manufacturing method |
| CN112765893A (en) * | 2021-01-27 | 2021-05-07 | 广东省大湾区集成电路与系统应用研究院 | Mask side wall angle control method, system, device and medium based on genetic algorithm |
| CN113109990A (en) * | 2020-01-09 | 2021-07-13 | 中芯国际集成电路制造(北京)有限公司 | Method for correcting mask layout |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107657115A (en) * | 2017-09-26 | 2018-02-02 | 上海华力微电子有限公司 | A kind of metal redundant pattern drawing method of raising CMP patterns |
| CN108573858A (en) * | 2018-05-21 | 2018-09-25 | 上海华力集成电路制造有限公司 | Improve the method for epitaxial growth uniformity |
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| CN113109990B (en) * | 2020-01-09 | 2022-08-26 | 中芯国际集成电路制造(北京)有限公司 | Method for correcting mask layout |
| CN111596521A (en) * | 2020-05-25 | 2020-08-28 | 上海华力集成电路制造有限公司 | Layout structure for improving exposure resolution and manufacturing method |
| CN111596521B (en) * | 2020-05-25 | 2023-08-15 | 上海华力集成电路制造有限公司 | Layout structure for improving exposure resolution and manufacturing method |
| CN112765893A (en) * | 2021-01-27 | 2021-05-07 | 广东省大湾区集成电路与系统应用研究院 | Mask side wall angle control method, system, device and medium based on genetic algorithm |
| CN112765893B (en) * | 2021-01-27 | 2023-04-25 | 广东省大湾区集成电路与系统应用研究院 | Mask side wall angle control method, system, equipment and medium based on genetic algorithm |
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