CN106067821B - Protection circuit of high-speed buffer and implementation method thereof - Google Patents
Protection circuit of high-speed buffer and implementation method thereof Download PDFInfo
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- CN106067821B CN106067821B CN201610572272.8A CN201610572272A CN106067821B CN 106067821 B CN106067821 B CN 106067821B CN 201610572272 A CN201610572272 A CN 201610572272A CN 106067821 B CN106067821 B CN 106067821B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
Abstract
The invention discloses a protection circuit of a high-speed buffer and an implementation method thereof, wherein the circuit comprises a working point establishment detection circuit, a working point protection circuit, a multi-power supply electrifying detection circuit, a clamping circuit, a first main current path switch and a second main current path switch, wherein the working point establishment detection circuit is used for detecting whether a normal working point is established or not; the working point protection circuit is used for preventing the MOSFET from exceeding a voltage withstanding range before a normal working point is established; the multi-power supply electrifying detection circuit is used for detecting whether all the associated multi-power supplies are electrified normally; and the multi-power supply electrifying detection circuit is used for detecting whether the multiple power supplies are all electrified. The voltage resistance of each port of the source-following MOSFET can not exceed the voltage resistance range before the working point of the cache buffer is established and before the multi-power supply is electrified.
Description
Technical Field
The present invention relates to a high-speed buffer and a method for implementing the same.
Background
Because the corresponding input impedance difference is large when the high-speed analog-to-digital converter (high-speed ADC for short) performs the sample/hold switching, the difference will cause the high-speed ADC to perform transient impact on the external passive impedance matching network during the switching, the impact strength is directly related to the input signal, which ultimately results in a large degradation of the performance of the high-speed ADC and other converters or signal processing devices connected to the same impedance matching network.
In order to solve the above-mentioned problems, a cache buffer is introduced, used to isolate the ADC core from the external passive impedance matching network. For a high performance cache, the design requires that it must have both good isolation over a specified input signal swing, while at the same time having to have a very high bandwidth in driving the ADC core to help minimize the error caused by the impact at a given sampling time. With the progress of integrated circuit technology, MOSFETs with smaller process line widths can be used to meet both requirements, but MOSFETs with smaller process line widths also have the problem of lower withstand voltage, which must be operated within an acceptable range when used. However, in a multi-power design, because the power-on speeds of different power supplies cannot be completely consistent, even in the same power supply domain, the establishment of a normal operating point may have a relatively long process, and if no protection circuit is provided, the MOSFET electrodes will be damaged due to a voltage difference exceeding a bearing range during the power-on process.
Disclosure of Invention
The invention aims to overcome the defect that a MOSFET exceeds a withstand voltage range due to the fact that working points are established and the power-on time of multiple power supplies is inconsistent in the power-on process in the prior art, and provides a protection circuit of a high-speed buffer and an implementation method thereof.
<xnotran> : </xnotran> A protection circuit of a high-speed buffer comprises a working point establishing detection circuit, a working point protection circuit, a multi-power supply power-on detection circuit, a clamping circuit, a first main current path switch and a second main current path switch, wherein the input end of the working point establishing detection circuit is connected with an input working point, the output end of the working point establishing detection circuit is respectively connected with the input end of the working point protection circuit and the first end of the first main current path switch, the output end of the working point protection circuit and the second end of the first main current path switch are connected with the drain electrode of a first MOS (metal oxide semiconductor) tube, the first end of the first main current path switch is also connected with a first power supply voltage, the grid electrode of the first MOS tube is connected with the input working point, the source electrode of the first MOS tube is connected with the output end of the clamping circuit and the first end of the second main current path switch, and the second end of the second main current path switch is grounded; the input end of the multi-power supply power-on detection circuit is connected with a first power supply voltage and a second power supply voltage, the output end of the multi-power-supply power-on detection circuit is connected with the first end of the second main current path switch and the input end of the clamping circuit.
The protection circuit further comprises a first bias circuit, a second bias circuit, a third bias circuit, a load circuit and a first current source; the first end of the first main current path switch is connected with a first power supply voltage through a first bias circuit, the source electrode of the first MOS tube is connected with the first end of the second main current path switch through a second bias circuit, the second end of the second main current path switch is connected with a first current source, the other end of the first current source is grounded, the source electrode of the first MOS tube is further connected with a load circuit, the input end of the load circuit is connected with a second power supply voltage, and the input end of the third bias circuit is connected with an input working point.
The working point establishment detection circuit comprises a comparator, a first input end of the comparator inputs preset voltage, a second input end of the comparator is connected with the input working point, an output end of the comparator is connected with a first end of a third switch, and meanwhile, an output end of the comparator is connected with a first end of a first main current path switch through a phase inverter.
The working point protection circuit comprises a second current source, a source following PMOSFET tube and a third switch, wherein the grid electrode of the source following PMOSFET tube is connected with the second input end of the comparator, the source electrode of the source following PMOSFET tube is connected with the first end of the third switch and the second current source, the other end of the second current source is connected with the first power supply voltage, the drain electrode of the source following PMOSFET tube is grounded, and the second end of the third switch is connected with the second end of the second main current path switch.
The multi-power-supply power-on detection circuit comprises a first resistor, a second resistor, a third MOS tube, a fourth MOS tube and an OR-NOT gate, wherein the grid electrode of the third MOS tube is connected with a second power supply voltage, the source electrode is grounded, the drain electrode is connected with a first resistor and a first input end of the NOR gate, and the other end of the first resistor is connected with a first power supply voltage; the grid electrode of the fourth MOS tube is connected with the first power supply voltage, the source electrode of the fourth MOS tube is grounded, the drain electrode of the fourth MOS tube is connected with the second resistor and the second input end of the NOR gate, and the other end of the second resistor is connected with the second power supply voltage.
A method for realizing the protection circuit of a high-speed buffer comprises two parts of protection related to the establishment of an operating point and protection related to the electrification of multiple power supplies, wherein the two parts operate independently;
the protection related to the establishment of the working point comprises the following steps:
s11: the working point establishment detection circuit compares the input working point input comparator with a preset voltage, and when the voltage value of the input working point is lower than the preset voltage value, the working point detection circuit considers that the establishment of the voltage of the input working point is not completed and skips step S12, otherwise, the establishment is completed;
s12: the working point establishment detection circuit sends out a control signal to control the working point protection circuit to be started, and closing the third switch and opening the first main current path switch;
s13: when the working point protection circuit is started, enabling VD1= VG1+ VTH2, wherein VD1 is the drain voltage of the first MOS tube, VG1 is the gate voltage of the first MOS tube, and VTH2 is the threshold voltage of a source-source PMOSFET tube;
s14: after the working point protection circuit is started, if the input working point is higher than the preset voltage, the working point detection circuit considers that the establishment of the working point voltage is finished, and simultaneously controls the protection circuit to be closed, and returns to the establishment completion state described in S11;
the protection related to multi-power-supply power-on comprises the following steps:
s21: the multi-power-supply electrifying detection circuit detects whether all the power supplies are electrified, if all the power supplies are not electrified, the multi-power-supply electrifying detection circuit considers that all the power supplies are not electrified, and the step S22 is skipped, otherwise, all the power supplies are electrified, and in the state that all the power supplies are electrified, the clamping circuit is switched off, and the second main current path switch is switched on;
s22: the multi-power-supply power-on detection circuit sends out a control signal to enable a first current source used for providing current for a main current path in the buffer to be disconnected, namely a switch of a second main current path is disconnected, meanwhile, the clamping circuit is started, and the output of the buffer is clamped on a specified level;
s23: after the multi-power-supply power-on protection circuit is started, if all power supplies are completely powered on, the circuit will return to the full power-up complete state described in S21.
When the working point protection circuit is started, the third switch is closed, the first main current path switch is disconnected, the drain voltage of the first MOS tube is determined by the source voltage of the source-following PMOSFET tube, and the source-following PMOSFET tube is connected with the second current source, so that VD1= VG1+ VTH2.
When the multi-power-supply power-on detection circuit detects, only when the first power supply voltage and the second power supply voltage are powered on completely, the first input end and the second input end of the NOR gate are at low level at the same time, and the output of the NOR gate is high.
The invention has the beneficial effects that: the invention provides a high-speed buffer protection circuit and a realization method thereof, which comprises protection schemes for coping with the following two different conditions in the circuit work, so that an MOSFET with the minimum line width in the circuit can not be damaged due to exceeding a voltage-resistant range in the two conditions.
1. When the working point of the high-speed buffer is not established, the MOSFET is protected from exceeding a voltage withstanding range;
2. when a multi-power design is adopted, when the multi-power is not completely electrified, the MOSFET is protected from exceeding a voltage withstanding range.
Drawings
FIG. 1 is a diagram of a protection circuit of a cache;
<xnotran> 2 ; </xnotran>
FIG. 3 is a block diagram of a multi-power-on detection circuit.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
As shown in fig. 1, a protection circuit of a cache includes an operating point establishing detection circuit, an operating point protection circuit, a multi-power supply power-on detection circuit, a clamp circuit, a first main current path switch SW1, and a second main current path switch SW2, wherein an input end of the operating point establishing detection circuit is connected to an input operating point, an output end of the operating point establishing detection circuit is connected to an input end of the operating point protection circuit and a first end of the first main current path switch SW1, respectively, an output end of the operating point protection circuit and a second end of the first main current path switch SW1 are connected to a drain of a first MOS transistor M1, a first end of the first main current path switch SW1 is further connected to a first power supply voltage VDD1, a gate of the first MOS transistor M1 is connected to the input operating point, a source of the first MOS transistor M1 is connected to an output end of the clamp circuit and a first end of the second main current path switch SW2, and a second end of the second main current path switch SW2 is grounded; the input end of the multi-power-supply power-on detection circuit is connected with a first power supply voltage VDD1 and a second power supply voltage VDD2, and the output end of the multi-power-supply power-on detection circuit is connected with a first end of a second main current path switch SW2 and the input end of the clamping circuit.
The protection circuit further comprises a first bias circuit, a second bias circuit, a third bias circuit, a load circuit and a first current source idc1; a first terminal of the first main current path switch SW1 is connected to a first supply voltage VDD1 via a first bias circuit, the source of the first MOS transistor M1 is connected to the first terminal of the second main current path switch SW2 through the second bias circuit, the second terminal of the second main current path switch SW2 is connected to the first current source idc1, the other end of the first current source idc1 is grounded, the source electrode of the first MOS tube M1 is further connected with a load circuit, the input end of the load circuit is connected with a second power supply voltage VDD2, and the input end of the third bias circuit is connected with an input working point.
As shown in fig. 2, the operating point establishment detection circuit includes a comparator CMP having a first input terminal for inputting a predetermined voltage V1, a second input terminal connected to the input operating point, the output terminal of the comparator CMP is connected to the first terminal of the third switch SW3, and the output terminal of the comparator CMP is also connected to the first terminal of the first main current path switch SW1 through an inverter.
The operating point protection circuit comprises a second current source idc2, a source follower PMOSFET M2 and a third switch SW3, wherein the grid electrode of the source follower PMOSFET M2 is connected with the second input end of a comparator CMP, the source electrode of the source follower PMOSFET M2 is connected with the first end of the third switch SW3 and the second current source idc2, the other end of the second current source idc2 is connected to the first power supply voltage VDD1, the drain of the source follower PMOSFET M2 is grounded, and the second end of the third switch SW3 is connected to the second end of the second main current path switch SW 2.
As shown in fig. 3, the multi-power-supply power-on detection circuit includes a first resistor R0, a second resistor R1, a third MOS transistor M3, a fourth MOS transistor M4, and an NOR gate NOR1, a gate of the third MOS transistor M3 is connected to a second power voltage VDD2, a source is grounded, a drain is connected to a first input terminal of the first resistor R0 and the NOR gate NOR1, and the other end of the first resistor R0 is connected to the first power voltage VDD 1; the gate of the fourth MOS transistor M4 is connected to the first power supply voltage VDD1, the source is grounded, the drain is connected to the second resistor R1 and the second input terminal of the NOR gate NOR1, and the other end of the second resistor R1 is connected to the second power supply voltage idc 2.
A method for realizing the protection circuit of a high-speed buffer comprises two parts of protection related to the establishment of an operating point and protection related to the electrification of multiple power supplies, wherein the two parts operate independently;
the protection related to the establishment of the working point comprises the following steps:
s11: the working point establishment detection circuit compares the input working point input comparator with a preset voltage, when the voltage value of the input working point is lower than the preset voltage value, the working point detection circuit considers that the establishment of the input working point voltage is not completed, and the step S12 is skipped, otherwise, the establishment is completed, and in the establishment completion state, the working point protection circuit is closed, the third switch SW3 is opened, and the first main current path switch SW1 is closed;
s12: the working point establishment detection circuit sends out a control signal to control the working point protection circuit to be opened, and the third switch SW3 is closed, and the first main current path switch SW1 is opened;
s13: when the working point protection circuit is started, enabling VD1= VG1+ VTH2, wherein VD1 is the drain voltage of a first MOS tube M1, VG1 is the grid voltage of the first MOS tube M1, and VTH2 is the threshold voltage of a source-follower PMOSFET tube M2;
s14: after the working point protection circuit is started, if the input working point is higher than the preset voltage, the working point detection circuit considers that the establishment of the working point voltage is finished, and simultaneously controls the protection circuit to be closed, and returns to the establishment completion state described in S11;
the protection related to multi-power-supply power-on comprises the following steps:
s21: the multi-power-supply electrifying detection circuit detects whether all the power supplies are electrified, if all the power supplies are not electrified, the multi-power-supply electrifying detection circuit considers that all the power supplies are not electrified, and the step S22 is skipped, otherwise, all the power supplies are electrified, and in the state that all the power supplies are electrified, the clamping circuit is switched off, and the second main current path switch SW2 is switched on;
s22: the multi-power-on detection circuit will issue a control signal to turn off the first current source idc1 in the buffer for supplying current to the main current path, namely, the switch SW2 of the second main current path is switched off, and simultaneously the clamping circuit is switched on to clamp the output of the buffer at a specified level;
s23: after the multi-power-supply power-on protection circuit is turned on, if all power supplies are completely powered on, the circuit will return to the all power-on complete state described in S21.
When the working point protection circuit is started, the third switch SW3 is closed, the first main current path switch SW2 is opened, at the moment, the drain voltage of the first MOS tube M1 is determined by the source voltage of the source following PMOSFET tube M2, and the source following PMOSFET tube M2 is connected with the second current source idc2, so that VD1= VG1+ VTH2 is formed by the source following PMOSFET tube M2.
When the multi-power-supply power-on detection circuit detects, only when the first power supply voltage VDD1 and the second power supply voltage VDD2 are completely powered on, the first input terminal and the second input terminal of the NOR gate NOR1 are simultaneously low, the NOR gate output is high.
Claims (7)
1. A protection circuit for a cache, comprising: it comprises a working point establishing detection circuit, a working point protection circuit, a multi-power supply electrifying detection circuit, a clamping circuit, a first main current path switch and a second main current path switch, wherein the input end of the working point establishing detection circuit is connected with an input working point, the output end of the working point establishing detection circuit is respectively connected with the input end of the working point protection circuit and the control end of the first main current path switch, the output end of the working point protection circuit and the second end of the first main current path switch are connected with the drain electrode of a first MOS (metal oxide semiconductor) tube, the control end of the first main current path switch is also connected with a first power supply voltage, the grid electrode of the first MOS tube is connected with the input working point, the source electrode of the first MOS tube is connected with the output end of the clamping circuit and the first end of the second main current path switch, and the second end of the second main current path switch is grounded; the input end of the multi-power-supply power-on detection circuit is connected with a first power supply voltage and a second power supply voltage, and the output end of the multi-power-supply power-on detection circuit is connected with a first end of a second main current path switch and the input end of the clamping circuit; the first main current path switch is switched on when detecting that the voltage of the input working point exceeds a detection threshold value, and the working point establishing detection circuit sends a control signal to control the working point protection circuit to be switched off after being switched on; and the second main current path switch is switched on when the multi-power-supply electrification detection is finished by completely electrifying the detected power supply, and the second main current path switch is switched off after the multi-power-supply electrification detection circuit sends out a control signal to switch off the first current source used for supplying current to the main current path in the buffer.
2. The protection circuit of claim 1, wherein: the protection circuit further comprises a first bias circuit, a second bias circuit, a third bias circuit, a load circuit and a first current source; the first end of the first main current path switch is connected with a first power supply voltage through a first bias circuit, the source electrode of the first MOS transistor is connected with the first end of the second main current path switch through a second bias circuit, the second end of the second main current path switch is connected with a first current source, the other end of the first current source is grounded, the source electrode of the first MOS tube is also connected with a load circuit, the input end of the load circuit is connected with a second power supply voltage, and the input end of the third bias circuit is connected with an input working point; the third bias circuit is respectively connected with the working point protection circuit and the working point establishment detection circuit, and provides voltage bias for the input working point and the working point protection circuit.
3. The protection circuit of a cache buffer according to claim 1, wherein: the working point establishment detection circuit comprises a comparator, a first input end of the comparator inputs preset voltage, a second input end of the comparator is connected with the input working point, an output end of the comparator is connected with a first end of a third switch, and meanwhile, the output end of the comparator is connected with a first end of a first main current path switch through a phase inverter; the working point protection circuit comprises a second current source, a source following PMOSFET tube and a third switch, wherein the grid electrode of the source following PMOSFET tube is connected with the second input end of the comparator, the source electrode of the source following PMOSFET tube is connected with the first end of the third switch and the second current source, the other end of the second current source is connected with the first power supply voltage, the drain electrode of the source following PMOSFET tube is grounded, and the second end of the third switch is connected with the second end of the second main current path switch.
4. The protection circuit of a cache buffer according to claim 1, wherein: the multi-power-supply power-on detection circuit comprises a first resistor, a second resistor, a third MOS tube, a fourth MOS tube and an OR-NOT gate, wherein the grid electrode of the third MOS tube is connected with a second power supply voltage, the source electrode is grounded, the drain electrode is connected with a first resistor and a first input end of the NOR gate, and the other end of the first resistor is connected with a first power supply voltage; the grid electrode of the fourth MOS tube is connected with the first power voltage, the source electrode of the fourth MOS tube is grounded, the drain electrode of the fourth MOS tube is connected with the second resistor and the second input end of the NOR gate, the other end of the second resistor is connected with the second power voltage, and the output end of the multi-power-supply power-on detection circuit is the output end of the NOR gate.
5. A method for implementing a protection circuit for a cache memory according to any one of claims 1 to 4, characterized in that it comprises two parts, a protection related to the establishment of an operating point and a protection related to the powering-up of multiple power supplies, which operate independently of each other;
the protection related to the establishment of the working point comprises the following steps:
s11: the working point establishment detection circuit compares the input working point input comparator with a preset voltage, and when the input working point voltage value is lower than the preset voltage value, the working point establishment detection circuit considers that the input working point voltage is not established, skipping to the step S12, otherwise, completing the establishment, and in the state of completing the establishment, closing the working point protection circuit, opening the third switch and closing the first main current path switch;
s12: the working point establishment detection circuit sends out a control signal to control the working point protection circuit to be started, and closing the third switch and opening the first main current path switch;
s13: when the working point protection circuit is started, enabling VD1= VG1+ VTH2, wherein VD1 is the drain voltage of the first MOS tube, VG1 is the gate voltage of the first MOS tube, and VTH2 is the threshold voltage of a source-follower PMOSFET tube;
s14: after the working point protection circuit is started, if the input working point is higher than the preset voltage, the working point detection circuit considers that the establishment of the working point voltage is completed, and simultaneously controls the protection circuit to be closed, and returns to the establishment completion state described in S11;
the protection related to multi-power-supply power-on comprises the following steps:
s21: the multi-power-supply electrifying detection circuit detects whether all the power supplies are electrified, if all the power supplies are not electrified, the multi-power-supply electrifying detection circuit considers that all the power supplies are not electrified, and the step S22 is skipped, otherwise, all the power supplies are electrified, and in the state that all the power supplies are electrified, the clamping circuit is switched off, and the second main current path switch is switched on;
s22: the multi-power-supply power-on detection circuit sends out a control signal to enable a first current source used for providing current for a main current path in the buffer to be disconnected, namely a switch of a second main current path is disconnected, meanwhile, the clamping circuit is started, and the output of the buffer is clamped on a specified level;
s23: after the multi-power-supply power-on protection circuit is turned on, if all power supplies are completely powered on, the circuit will return to the all power-on complete state described in S21.
6. The method of claim 5, wherein the third switch is closed and the first main current path switch is open, and wherein the drain voltage of the first MOS transistor is determined by the source voltage of the source-follower PMOSFET transistor, and the source-follower PMOSFET transistor is connected to the second current source such that VD1= VG1+ VTH2.
7. The method of claim 5, wherein the NOR gate output is high only when the first power supply voltage and the second power supply voltage are powered on and the NOR gate first input and the second input are both low.
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| 基于PI Expert软件的LED驱动电源设计;陈贤;《电子技术与软件工程》;20151102(第21期);92-93 * |
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