CN106060425A - FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method - Google Patents
FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method Download PDFInfo
- Publication number
- CN106060425A CN106060425A CN201510881244.XA CN201510881244A CN106060425A CN 106060425 A CN106060425 A CN 106060425A CN 201510881244 A CN201510881244 A CN 201510881244A CN 106060425 A CN106060425 A CN 106060425A
- Authority
- CN
- China
- Prior art keywords
- video signal
- digital video
- serial
- fpga
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 239000000284 extract Substances 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000012795 verification Methods 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 abstract description 10
- 238000013500 data storage Methods 0.000 abstract 3
- 230000008569 process Effects 0.000 description 9
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N ferric oxide Chemical compound O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
The invention discloses an FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method. The system comprises an input signal processing unit, a video data storage unit, a video image processing unit and a serial data output driving unit, and is characterized in that the input signal processing unit carries out equalization and data recovery processing on received serial digital video signals and converts the serial digital video signals into parallel digital video signals; the video data storage unit stores the parallel digital video signals frame by frame by taking a predefined number of video frames as a unit; the video image processing unit reads the parallel digital video signals stored by the video data storage unit and carries out frame rate conversion processing on the parallel digital video signals; and the serial data output driving unit is connected to the video image processing unit, converts the parallel digital video signals into serial digital video signals and then conveys the serial digital video signals to a backward-stage signal processor in a driving manner. The system and the method disclosed by the invention effectively reduce signal jitter, and ensure the integrity of digital serial video signals inside a matrix.
Description
Technical field
The present invention relates to video signal processing field, particularly relate to one and be applicable to extensive multi-format video signal and cut
Change clock recovery system and the method for the serial video signal based on FPGA of matrix.
Background technology
Inside existing extensive multi-format digital video switching matrix, a large amount of use serial digital video signals pass
Defeated and switching, thus ensure video signal signal transmission integrity and switching chip low cost.But above-mentioned on a large scale
In matrix, serial digital video signal is after the transmission of long-distance, then there is signal jitter increases, and the bad grade of eye pattern effect lacks
Fall into, thus cause the critical defect that cannot ensure signal integrity after the transmission of distance.
At present, the problems referred to above to be solved then must use clock recovery techniques to process, and i.e. utilizes existing umber of feed inlet
Word video signal clock recovers chip and processes, but current clock recovery techniques remains at just for serial signal
Reason, difficulty is relatively big, relatively costly, and cannot carry out agreement verification for video signal, the defect of redundancy check；Also can simultaneously
Cause extensive multiple format video matrix relatively costly, the defects such as internal signal monitoring is difficult.
Summary of the invention
The defect existed in view of prior art, the invention aims to provide a kind of serial video signal based on FPGA
Clock recovery system, this clock recovery system characteristic based on high-speed serial digital signal, use FPGA to digital video signal
Carry out clock recovery process, effectively reduce signal jitter, improve signal transmission objective, and then ensure the number of internal matrix
The integrity of word serial video signal.
To achieve these goals, technical scheme:
A kind of serial video signal clock recovery system based on FPGA, it is characterised in that:
Defeated including input signal processing unit, video data memory element, Computer Vision unit and serial data
Go out driver element；
Described input signal processing unit, in order to equalize and at data recovery reception serial digital video signal
Reason, and send to video data memory element after being converted into parallel digital video signal；
Described video data memory element connects described input signal processing unit, in order to according to predefined frame of video frame
Number stores described parallel digital video signal frame by frame for unit；
Described Computer Vision unit connects described video data memory element, in order to read the storage of described video data
Unit storage parallel digital video signal, and described parallel digital video signal is carried out frame per second conversion processing make described in also
The frame per second of row number video signal and the frame per second proportion relation of described output video signal set in advance；
Described serial data output driver element connects described Computer Vision unit, in order to be believed by parallel digital video
Number being converted to serial digital video signal rear drive is delivered to rear class signal processor.
Further, described input signal processing unit includes the serdes processing module of fpga chip.
Described input signal processing unit is additionally operable to carry out error checking, i.e. from connecing to receiving serial digital video signal
Receive in serial digital video signal extract check code and with the CRC check sent in the lump with described serial digital video signal
Code carries out error checking, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
Further, described video data memory element includes the DDR module control interface connection by fpga chip
DDR storage chip.
Further, described serial data output driver element includes serdes processing module and the port of fpga chip
Drive module.
Present invention also offers a kind of serial video signal clock recovery method based on FPGA, it is characterised in that:
Comprise the steps
S1, equalize and data recovery process receiving serial digital video signal, and be converted into parallel digital video
Send after signal；
S2, it is that unit stores described parallel digital video signal frame by frame according to predefined frame of video frame number；
The parallel digital video signal that S3, reading are stored, and described parallel digital video signal is carried out frame per second conversion
Processing makes the frame per second of described parallel digital video signal become a definite proportion with the frame per second of described output video signal set in advance
Example relation；
S4, parallel digital video signal is converted to serial digital video signal rear drive it is delivered to rear class signal processing
Device.
Further, described S1 also carries out error checking, i.e. to receiving serial digital video signal when changing
From receive in serial digital video signal extract check code and with the CRC sent in the lump with described serial digital video signal
Check code carries out error checking, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
Further, the DDR storage chip storage number that described S2 is connected by the DDR module control interface of fpga chip
According to.
Compared with prior art, beneficial effects of the present invention:
The present invention is directed to the characteristic of high-speed serial digital signal, employ fpga chip and carry out the clock of digital video signal
Recover, effectively reduce video signal shake, improve signal transmission objective；Ensure the data serial video of internal matrix simultaneously
The integrity of signal, considerably reduces cost and improves the flexibility ratio of system, and can detect signal quality to letter
Number carry out redundancy check and redundant correcting.
Accompanying drawing explanation
Fig. 1 is the circuit structure block diagram of clock recovery system of the present invention；
Fig. 2 is existing large-scale multi-format internal matrix serial signal crossbar signal schematic diagram；
Fig. 3 is the serdes processing module signal interface circuit figure of described input signal processing unit；
Fig. 4 is described video data memory element interface circuit figure；
Fig. 5 is the serdes input signal RX path schematic diagram of FPGA；
Fig. 6 is video data memory module workflow diagram；
Fig. 7 is the eye pattern of the serial digital video signal before clock recovery；
Fig. 8 is the eye pattern of the serial digital video signal after clock recovery；
Fig. 9 is the flow chart of steps that clock recovery method of the present invention is corresponding.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the present invention is entered
Row further describes.
As in figure 2 it is shown, generally in the middle of a large-scale multiple format video switching matrix, signal way is more, all
The intersection switching that carries out of a signal switching chip being required for concentrating, therefore major part signal is at the cabling of PCB and cabinet
Internal cabling can be long, thus causes signal to there is the problem (such as Fig. 7) of decay substantially, but when length surpasses
When crossing to a certain degree, rear class signal processor cannot recover correct digital video signal, thus causes the complete of video signal
Property hardly results in guarantee.
Based on the problems referred to above, the present invention devises a kind of in order to realize in the middle of the transmitting procedure of signal and in signal attenuation
Carry out, before cannot completely recovering data, the clock recovery circuitry that the clock recovery of signal processes；So that the numeral after Hui Fuing
The eye pattern of video signal such as Fig. 8, thus effectively extend signal lead length, for the dilatation of extensive multiple format video switching matrix
Basic technical feasibility is provided.
As it is shown in figure 1, described serial video signal clock recovery system based on FPGA, it is single that it includes that input signal processes
Unit, video data memory element, Computer Vision unit and serial data output four unit of driver element；
Wherein, as shown in Figure 3-Figure 5, described input signal processing unit is in order to carry out reception serial digital video signal
Equilibrium and data recovery process, and it is converted into parallel digital video signal；For convenience of description, with the 2nd tunnel input signal of Fig. 2
As a example by Inverse problem output to the 255th tunnel, now signal has occurred in that decay such as Fig. 7, and eye pattern has begun to become not
Clearly, when being directly output to rear class board, the mistake that signal occurs, video signal occurs in that noise, the phenomenon such as Ka Dun and frame-skipping.
It is thus desirable to equalize and data recovery process receiving serial digital video signal so that it is recovery letter to a certain extent
Number integrity；Equilibrium and the restored processed journey of data can directly utilize the serdes processing modules implement of fpga chip, serdes
Processing module can complete such as serioparallel exchange, signal byte-aligned, digital decoding, and the primary signal equalization such as clock compensation is extensive
Multiple processing procedure.
Preferably, described serdes processing module uses the serdes processing module of LFE17EAFP484FPGA chip, right
The data serial signal of input carries out long line equilibrium and data and recovers, and defeated after serial data is converted into parallel video signal
Go out to next stage unit.
Described input signal processing unit is additionally operable to carry out error checking, i.e. from connecing to receiving serial digital video signal
Receive in serial digital video signal extract check code and with the CRC check sent in the lump with described serial digital video signal
Code carries out error checking, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
In order to solve in the middle of input video transmitting procedure, if needing it is carried out the image procossing between frame frame, need
The problem of whole storage multi-frame video, is provided with video data memory element, and described video data memory element is in order to according in advance
The frame of video frame number of definition is that unit stores described parallel digital video signal frame by frame, reads for described Computer Vision unit
Take；
Described video data memory element includes that the DDR connected by the DDR module control interface of fpga chip stores core
Sheet, in order to stored by parallel digital video signal in DDR storage chip, when described Computer Vision unit needs video
During signal, it gives rear class institute after signal reads in units of predefined frame of video frame number from DDR storage chip arrangement
Stating Computer Vision unit, and signal carries out completeness check, the most described video data memory element is additionally operable to reception
Carry out error checking to parallel digital video signal, i.e. from receive parallel digital video signal extracts check code and with institute
Stating the CRC check code that parallel digital video signal sends in the lump and carry out error checking, differing if there is check errors i.e. comparison
Causing, then report to the police, there is decoding error in prompting.Ensure, in the middle of signal storage reading process, there is no loss of data and data
Mistake.
Owing to the frame per second of input video is relevant to the reference clock of incoming serial signal, but with output serial signal ginseng
Examine clock and there is no dependency, then must be the frame relevant to the frame per second of output video signal by the frame rate conversion of input video
Rate, at this time can produce frame losing and mend frame process, in order to not affect the perception of video, need exist for the frame losing to frame of video and
Mend frame process and carry out the process before frame and frame；The most described Computer Vision unit is single in order to read the storage of described video data
The parallel digital video signal of unit's storage, and the frame per second of described parallel digital video signal is carried out frame per second conversion processing, even if
Obtain the frame per second of described parallel digital video signal and the frame per second proportion relation of described output video signal set in advance.
Also need to the video signal of frame per second conversion processing is verified simultaneously, utilize the blanking interval that video signal inputs
Redundancy check code, judges the video signal integrity of transmission link, it may be judged whether the signal maintaining video signal is complete
Whole property；And also can utilize transmitting redundancy coding-8B10B error correcting technique that video data carries out redundant correcting, recover data,
Such as Fig. 6.
Such as when setting the reference clock of incoming video signal as 148.5001Mhz, now video frame rate is 60.00004.
And our video signal reference clock to be exported is when being 148.4999Mhz, video frame rate now is 59.99959.Now by
Different in frame per second, when directly input signal being connected to output signal, the internal FIFO of FPGA there will be fully loaded, causes loss of data
And mistake.Now in order to ensure to export video signal at the visual integrity of user, it would be desirable to FIFO is fully loaded with when
A part of video data is lost in units of frame.But lose the data of a frame, the jump of visually dynamic image can be caused, depending on
Frequency is discontinuous, this data difference algorithm being accomplished by using signal multiframe, and described algorithm refers to take between neighbouring two frame data and transports
Motion video difference, calculates the side-play amount of its relative motion image simultaneously, and then obtains closest moving image position, according to this
Moving image position generates new video data frame, to ensure seriality and the integrity of dynamic image.Simultaneously because we make
With being the active crystal oscillator of the local low jitter (DSC1101-21) of low cost, provide reference source for video signal, in view of reference source
Shake low then output serial data shake low, then can ensure that frame per second is changed into 59.99959 by 60.00004, and then ensure defeated
Publish picture picture shake reduce.
Described serial data output driver element is used in conjunction parallel digital video signal is converted to serial digital video letter
Number rear drive is delivered to rear class signal processor；It serdes processing module including fpga chip and port driver block.
When described video data memory element completes video frequency signal processing, the serdes processing module of fpga chip will also
The digital video signal of row is converted into serial signal, and the serdes processing module that can employ LFE17EAFP484FPGA completes this
Item work, after changing into serial signal, uses the port driver block of FPGA to carry out distance driving and ensure that serial digital is believed
Number integrity, it is achieved clock recovery function.
Concrete, after FPGA has processed four road video signals simultaneously, utilize the serdes module of FPGA to carry out together
Serioparallel exchange and output signal drive, thus cost-effective, reduce outside related chip.The reference clock of this output signal is
It not the 148.50001Mhz inputted but the active crystal oscillator of local low jitter of 148.4999Mhz.So the serial digital of output
The shake of video signal is reduced to 0.15UI from initial 0.5UI.With reference to Fig. 7 and Fig. 8.Now have been completed that video is believed
Number clock recovery processing procedure.And it is to add video protocols redundancy check protocol in output signal, to assist rear class to regard
Frequency processes board judges whether there is new mistake generation in signals transmission.
Such as Fig. 9, present invention also offers a kind of serial video signal clock recovery method based on FPGA, its feature exists
In:
Comprise the steps
S1, equalize and data recovery process receiving serial digital video signal, and be converted into parallel digital video
Send after signal；
S2, it is that unit stores described parallel digital video signal frame by frame according to predefined frame of video frame number；
The parallel digital video signal that S3, reading are stored, and described parallel digital video signal is carried out frame per second conversion
Processing makes the frame per second of described parallel digital video signal become a definite proportion with the frame per second of described output video signal set in advance
Example relation；
S4, parallel digital video signal is converted to serial digital video signal rear drive it is delivered to rear class signal processing
Device.
Further, described S1 also carries out error checking, i.e. to receiving serial digital video signal when changing
From receive in serial digital video signal extract check code and with the CRC sent in the lump with described serial digital video signal
Check code carries out error checking, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
Further, the DDR storage chip storage number that described S2 is connected by the DDR module control interface of fpga chip
According to.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope that the invention discloses, according to technical scheme and
Inventive concept equivalent or change in addition, all should contain within protection scope of the present invention.
Claims (8)
1. a serial video signal clock recovery system based on FPGA, it is characterised in that:
Drive including the output of input signal processing unit, video data memory element, Computer Vision unit and serial data
Moving cell；
Described input signal processing unit, in order to reception serial digital video signal is equalized and data recovery process, and
Send to video data memory element after being converted into parallel digital video signal；
Described video data memory element connects described input signal processing unit, in order to according to predefined frame of video frame number to be
Unit stores described parallel digital video signal frame by frame；
Described Computer Vision unit connects described video data memory element, in order to read described video data memory element
The parallel digital video signal of storage, and described parallel digital video signal is carried out frame per second conversion processing make described and line number
The frame per second of word video signal and the frame per second proportion relation of described output video signal set in advance；
Described serial data output driver element connects described Computer Vision unit, in order to be turned by parallel digital video signal
It is changed to serial digital video signal rear drive and is delivered to rear class signal processor.
Serial video signal clock recovery system based on FPGA the most according to claim 1, it is characterised in that:
Described input signal processing unit includes the serdes processing module of fpga chip.
Serial video signal clock recovery system based on FPGA the most according to claim 1, it is characterised in that:
Described input signal processing unit is additionally operable to carry out error checking, i.e. from receiving to receiving serial digital video signal
Serial digital video signal extracts check code and enters with the CRC check code sent in the lump with described serial digital video signal
Row error checking, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
Serial video signal clock recovery system based on FPGA the most according to claim 1, it is characterised in that:
Described video data memory element includes the DDR storage chip connected by the DDR module control interface of fpga chip.
Serial video signal clock recovery system based on FPGA the most according to claim 1, it is characterised in that:
Described serial data output driver element includes serdes processing module and the port driver block of fpga chip.
6. a serial video signal clock recovery method based on FPGA, it is characterised in that:
Comprise the steps
S1, equalize and data recovery process receiving serial digital video signal, and be converted into parallel digital video signal
Rear transmission；
S2, it is that unit stores described parallel digital video signal frame by frame according to predefined frame of video frame number；
The parallel digital video signal that S3, reading are stored, and described parallel digital video signal is carried out frame per second conversion processing
Make the frame per second of described parallel digital video signal and the proportional pass of frame per second of described output video signal set in advance
System；
S4, parallel digital video signal is converted to serial digital video signal rear drive it is delivered to rear class signal processor.
Serial video signal clock recovery method based on FPGA the most according to claim 6, it is characterised in that:
Described S1 also carries out error checking, i.e. from receiving serial number to receiving serial digital video signal when changing
Word video signal extracts check code and carries out error code with the CRC check code sent in the lump with described serial digital video signal
Verification, if it is inconsistent to there is check errors i.e. comparison, then reports to the police, and decoding error occurs in prompting.
Serial video signal clock recovery method based on FPGA the most according to claim 6, it is characterised in that:
The DDR storage chip storage data that described S2 is connected by the DDR module control interface of fpga chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510881244.XA CN106060425A (en) | 2015-12-03 | 2015-12-03 | FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510881244.XA CN106060425A (en) | 2015-12-03 | 2015-12-03 | FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106060425A true CN106060425A (en) | 2016-10-26 |
Family
ID=57179405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510881244.XA Pending CN106060425A (en) | 2015-12-03 | 2015-12-03 | FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106060425A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831666A (en) * | 2019-02-25 | 2019-05-31 | 苏州长风航空电子有限公司 | A kind of detection method of digital signal transmission quality |
| CN112825562A (en) * | 2019-11-21 | 2021-05-21 | 杭州海康威视数字技术股份有限公司 | Video frame compensation method and device and video processing chip |
| CN113810029A (en) * | 2020-06-12 | 2021-12-17 | 圣邦微电子（北京）股份有限公司 | Circuit for detecting data correlation |
| CN114390237A (en) * | 2021-12-23 | 2022-04-22 | 南京熊猫电子制造有限公司 | 48Gbps ultra-high bandwidth video coding and decoding processing system and method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010064257A (en) * | 1999-12-27 | 2001-07-09 | 오길록 | High-performance software modem platform board |
| CN1960461A (en) * | 2005-10-31 | 2007-05-09 | 三星电子株式会社 | Video signal receiver including display synchronizing signal generation device and control method thereof |
| CN101316360A (en) * | 2008-07-17 | 2008-12-03 | 杭州华三通信技术有限公司 | Method and device for converting video stream frame rate |
| US7742553B1 (en) * | 2005-01-14 | 2010-06-22 | Xilinx, Inc. | VCO initial frequency calibration circuit and method therefore |
| CN201878274U (en) * | 2010-11-24 | 2011-06-22 | 北京格非科技发展有限公司 | Multi-format converter |
| CN103856758A (en) * | 2012-11-29 | 2014-06-11 | 安讯士有限公司 | Method and system for generating real-time motion video |
| CN104754272A (en) * | 2013-12-25 | 2015-07-01 | 深圳艾科创新微电子有限公司 | VGA (Video Graphics Array) full-resolution locked display system and method |
-
2015
- 2015-12-03 CN CN201510881244.XA patent/CN106060425A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010064257A (en) * | 1999-12-27 | 2001-07-09 | 오길록 | High-performance software modem platform board |
| US7742553B1 (en) * | 2005-01-14 | 2010-06-22 | Xilinx, Inc. | VCO initial frequency calibration circuit and method therefore |
| CN1960461A (en) * | 2005-10-31 | 2007-05-09 | 三星电子株式会社 | Video signal receiver including display synchronizing signal generation device and control method thereof |
| CN101316360A (en) * | 2008-07-17 | 2008-12-03 | 杭州华三通信技术有限公司 | Method and device for converting video stream frame rate |
| CN201878274U (en) * | 2010-11-24 | 2011-06-22 | 北京格非科技发展有限公司 | Multi-format converter |
| CN103856758A (en) * | 2012-11-29 | 2014-06-11 | 安讯士有限公司 | Method and system for generating real-time motion video |
| CN104754272A (en) * | 2013-12-25 | 2015-07-01 | 深圳艾科创新微电子有限公司 | VGA (Video Graphics Array) full-resolution locked display system and method |
Non-Patent Citations (1)
| Title |
|---|
| 肖德琴: "《计算机网络原理与应用》", 28 February 2011 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831666A (en) * | 2019-02-25 | 2019-05-31 | 苏州长风航空电子有限公司 | A kind of detection method of digital signal transmission quality |
| CN112825562A (en) * | 2019-11-21 | 2021-05-21 | 杭州海康威视数字技术股份有限公司 | Video frame compensation method and device and video processing chip |
| CN112825562B (en) * | 2019-11-21 | 2022-11-01 | 杭州海康威视数字技术股份有限公司 | Video frame compensation method and device and video processing chip |
| CN113810029A (en) * | 2020-06-12 | 2021-12-17 | 圣邦微电子（北京）股份有限公司 | Circuit for detecting data correlation |
| CN114390237A (en) * | 2021-12-23 | 2022-04-22 | 南京熊猫电子制造有限公司 | 48Gbps ultra-high bandwidth video coding and decoding processing system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106060425A (en) | FPGA (Field Programmable Gate array) based serial video signal clock recovery system and method | |
| US8037370B2 (en) | Data transmission apparatus with information skew and redundant control information and method | |
| US20230092000A1 (en) | Serial interface for semiconductor package | |
| US9621303B2 (en) | Method and apparatus for valid encoding | |
| US11176386B2 (en) | System and method for continuous operation of vision/radar systems in presence of bit errors | |
| US20160125786A1 (en) | Over-driving method, circuit, display panel and display apparatus | |
| US10523867B2 (en) | Methods and apparatus for multi-lane mapping, link training and lower power modes for a high speed bus interface | |
| US20150294614A1 (en) | Display panel driving method, driving device and display device | |
| CN104735299B (en) | ARINC818 receives control circuit and method | |
| US10447429B2 (en) | Methods to transport forward error correction codes in a symbol encoded transmission stream | |
| CN103888693A (en) | Image transmission device | |
| CN105721102B (en) | Memory efficient method for transmitting error correction codes in symbol encoded transport streams | |
| EP1605621A2 (en) | Data transmission with improved error correction capability | |
| WO2024094191A1 (en) | Display data processing method and apparatus, electronic device, and storage medium | |
| CN103795499A (en) | Satellite load high-speed serial port error detection and correction method | |
| CN107452324B (en) | It is a kind of to upgrade multiple anti-interference optimization methods of reception card and display screen control system | |
| US9100555B2 (en) | Hybrid mode repeater/re-driver for high speed digital video signaling | |
| KR100450320B1 (en) | Method/Module of Digital TV image signal processing with Auto Error Correction | |
| CN105025291A (en) | Method and device for generating TTL video signal | |
| CN104703028A (en) | Method, device and system for correcting video frames | |
| CN205212949U (en) | Serial video signal's clock recovery device based on FPGA | |
| CN101561998A (en) | Method and device for processing data of liquid crystal display | |
| CN204810422U (en) | System for be used for converting LVDS into 8LaneV -BY -ONE video signal | |
| CN115223488B (en) | Data transmission method, device, time sequence controller and storage medium | |
| EP4266585A1 (en) | Data error correction circuit and data transmission method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161026 |
|
| RJ01 | Rejection of invention patent application after publication |