CN113810029A - Circuit for detecting data correlation - Google Patents
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- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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Abstract
The application discloses detect circuit of data correlation includes: the serial-parallel conversion module receives a serial data signal and a reference data signal and converts the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; the voltage detection module receives the parallel data signals and converts the parallel data signals into analog voltage detection signals; and the correlation output module is suitable for comparing the voltage detection signal with a first threshold voltage and a second threshold voltage so as to judge the correlation between the serial data signal and the reference data signal. The data correlation is judged in an analog comparison mode, and the resistor and the comparator are adopted to replace an accumulator and a numerical comparator in the existing digital correlator, so that the operation part circuit of the correlation detection is greatly simplified, the circuit structure is simplified, the complexity of the circuit is reduced, and the cost of the correlation detection is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a circuit for detecting data dependency.
Background
In a digital communication system, it is very important to ensure frame synchronization between data streams on a transmitting side and a receiving side. How to quickly and efficiently determine the start position of the frames of a data stream and obtain frame synchronization is a key part in the modern communication field that is directly related to the communication speed and quality.
Generally, a relatively simple and well-accepted method of frame synchronization is to insert a signature at a specific position in a frame during data transmission on the transmitting side for transmission as part of the frame structure, and then to perform frame synchronization detection by the receiving side by continuously searching for signatures in the received data stream. In the prior art, a correlator or a matched filter is generally used to detect a peak value of a correlation value to continuously search for a feature code in a received data stream, the position corresponding to the peak value of the correlation value is the position of the detected feature code, and once the feature code is determined, the start position of a frame is determined, so that frame synchronization is obtained.
Fig. 1 shows a schematic diagram of a digital correlator according to the prior art. The digital correlator mainly plays a role of digital matching filtering in communication signal processing, can perform correlation processing on a specific code sequence so as to complete signal decoding and recover transmitted information, and is widely applied to the fields of frame synchronization detection, error code correction, pattern matching and the like.
As shown in fig. 1, the digital correlator 100 includes an input sequence shift register 110, a reference sequence shift register 120, a correlation operation array 130, and a correlation summation network 140. The input sequence shift register 110 is configured to receive an input data stream DATAIN driven by a sampling clock CLK, the reference sequence shift register 120 is configured to receive a reference data stream REF, the correlation operation array 130 is configured to perform a correlation operation on the input data stream DATAIN and the reference data stream REF, the correlation operation array 130 performs a correlation operation once every time the input sequence shift register 110 updates one bit of data, and then sends the correlation operation result to the correlation summation network 140, and the correlation summation network 140 calculates a correlation value. The correlation value output by the correlation summing network 140 is compared to a DETECTION threshold and a correlation peak signal DETECTION is generated based on the comparison.
The input serial shift register 110 includes a plurality of cascaded D flip-flops 101, where each D flip-flop 101 includes a data input terminal, a clock terminal, a first output terminal, and a second output terminal. The clock terminals of the plurality of D flip-flops 101 are configured to receive the sampling clock CLK, the data input terminal of the first stage D flip-flop 101 is connected to the input data stream DATAIN, the data input terminal of each stage D flip-flop 101 except the first stage D flip-flop 101 is connected to the first output terminal of the previous stage D flip-flop 101 to receive the output of the previous stage D flip-flop 101, and each stage D flip-flop 101 is configured to output a corresponding data bit of the input data stream DATAIN under the driving of the sampling clock CLK.
The correlation operation array 130 includes a plurality of exclusive nor gates XNOR, each of which is used to xor each data of the input data stream DATAIN with a corresponding data bit of the reference data stream REF, and then count the number of "1" s and "0" s in the correlation operation array 130.
The correlation summing network 140 includes an AND gate AND, a NOR gate NOR, AND an OR gate. The input terminals of the AND gate AND are connected to the output terminals of the plurality of exclusive nor gates XNOR in the correlation operation array 130, the AND gate AND is used for detecting the positive correlation peak, AND the positive correlation peak signal SIG1 is output according to the number of "1" s AND "0" s in the correlation operation array 130. The input terminal of the NOR gate NOR is connected to the output terminals of a plurality of exclusive NOR gates XNOR in the correlation operation array 130, the NOR gate NOR is used for detecting the negative correlation peak, and the number of "1" s and "0" s in the correlation operation array 130 outputs the negative correlation peak signal SIG 0. The input terminals of the OR gate OR are respectively connected with the output terminals of the AND gate AND OR the NOR gate NOR, AND the output terminal of the OR gate OR is used for outputting the correlation peak signal DETECTION. The correlation peak signal DETECTION indicates that the current input data stream DATAIN is correlated with the reference data stream REF, the positive correlation peak signal SIG1 indicates that the current input data stream DATAIN is positively correlated with the reference data stream REF, and the negative correlation peak signal SIG0 indicates that the current input data stream DATAIN is negatively correlated with the reference data stream REF.
In the digital correlator 100 in the prior art, an exclusive or operation needs to be performed on an input data stream and a reference data stream, and an operation result needs to be accumulated, so that a shift register, an accumulator, a numerical comparator and an exclusive or operator need to be used in a circuit, the circuit structure is complex, the circuit area is increased, and the digital correlator is not suitable for some fields requiring control cost.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a circuit for detecting data correlation, which can simplify the circuit structure, reduce the complexity of the circuit, and reduce the cost of correlation detection.
According to an embodiment of the present invention, there is provided a circuit for detecting data correlation, including: the serial-parallel conversion module receives a serial data signal and a reference data signal and converts the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; the voltage detection module receives the parallel data signals and converts the parallel data signals into analog voltage detection signals; a correlation output module adapted to compare the voltage detection signal with a first threshold voltage and a second threshold voltage to determine a correlation between the serial data signal and the reference data signal, wherein the correlation output module is adapted to generate a first indication signal and a second indication signal according to a comparison result, the first indication signal representing whether the serial data signal and the reference data signal are correlated or not, and the second indication signal representing whether the serial data signal and the reference data signal are positively correlated or negatively correlated.
Preferably, the correlation output module includes: the inverting input end of the first operational amplifier receives the first threshold voltage, the non-inverting input end of the first operational amplifier receives the voltage detection signal, and the output end of the first operational amplifier is used for providing a first comparison signal; the positive phase input end of the second operational amplifier receives the second threshold voltage, the negative phase input end of the second operational amplifier receives the voltage detection signal, and the output end of the second operational amplifier is used for providing a second comparison signal; the control end of the first transistor is connected with the output end of the first operational amplifier, the first end of the first transistor is connected with a power supply voltage through a pull-up resistor, and the second end of the first transistor is grounded; and a control end of the second transistor is connected with an output end of the second operational amplifier, a first end of the second transistor is connected with a first end of the first transistor, and a second end of the second transistor is grounded, wherein an intermediate node between the first transistor and the second transistor is used for outputting the first indication signal, and an intermediate node between the first transistor and the first operational amplifier is used for outputting the second indication signal.
Preferably, the correlation output module further comprises first to third resistors connected in series in sequence between the supply voltage and ground, wherein an intermediate node of the first resistor and the second resistor is adapted to provide the first threshold voltage, and an intermediate node of the second resistor and the third resistor is adapted to provide the second threshold voltage.
Preferably, the second resistor is an adjustable resistor, and the detection threshold of the data correlation detection can be adjusted by adjusting the resistance value of the second resistor.
Preferably, the serial-to-parallel conversion module includes: a plurality of cascaded trigger units, each stage of the trigger units being adapted to process received data according to the sampling clock to generate first output data and second output data; a plurality of switching units corresponding to the plurality of trigger units, each of the switching units being configured to output one of the first output data and the second output data as one valid data bit of the parallel data signal according to the reference data signal.
Preferably, the voltage detection module includes a plurality of detection resistors disposed corresponding to the plurality of switching units, wherein first ends of the plurality of detection resistors are respectively connected to output ends of the corresponding switching units, and second ends of the plurality of detection resistors are connected to each other to provide the voltage detection signal.
Preferably, each stage of the trigger unit includes a data input end, a clock end, a first output end and a second output end, where the clock end of the trigger unit of each stage is configured to receive the sampling clock, the first output end is configured to output the first output data, the second output end is configured to output the second output data, the data input end of the trigger unit of the first stage is configured to receive the serial data signal, and the data input end of the trigger unit of each stage other than the trigger unit of the first stage is connected to the first output end of the trigger unit of the previous stage to receive the first output data of the trigger unit of the previous stage.
Preferably, each stage of the trigger unit further includes: the first current source, the third transistor and the fourth transistor are sequentially connected between a power supply voltage and the ground, the control end of the third transistor is connected with the data input end, and the control end of the fourth transistor is connected with the clock end; the second current source and the fifth transistor are sequentially connected between the power supply voltage and the ground, and the control end of the fifth transistor is connected with the data input end; the third current source and the sixth transistor are sequentially connected between the power supply voltage and the first end of the fourth transistor, and the control end of the sixth transistor is connected with the first end of the fifth transistor; a fourth current source, a seventh transistor and an eighth transistor sequentially connected between the power supply voltage and ground, wherein a control terminal of the seventh transistor is connected to the first output terminal, a first terminal of the seventh transistor is connected to the second output terminal, and a control terminal of the eighth transistor is connected to a first terminal of the third transistor; the control end of the ninth transistor is connected with the second output end, the first end of the ninth transistor is connected with the first output end, and the control end of the tenth transistor is connected with the first end of the sixth transistor.
Preferably, the first output data is the same as the data received at the data input and the second output data is the opposite of the data received at the data input.
Preferably, the switching unit is selected from a single-pole double-throw switch, and each data bit of the reference data signal is provided to a control terminal of the corresponding single-pole double-throw switch.
The circuit for detecting data correlation comprises a serial-to-parallel conversion module, a voltage detection module and a correlation output module, wherein the voltage detection module converts a parallel data signal into an analog voltage detection signal, the correlation output module compares the voltage detection signal with a first threshold voltage and a second threshold voltage, and the correlation between the serial data signal and the reference data signal is judged according to a comparison result. The data correlation is judged in an analog comparison mode, and the resistor and the comparator are adopted to replace an accumulator and a numerical comparator in the existing digital correlator, so that the operation part circuit of the correlation detection is greatly simplified, the circuit structure is simplified, the complexity of the circuit is reduced, and the cost of the correlation detection is reduced.
In a further embodiment, the circuit for detecting data correlation samples and holds serial data by using 8 transistors and 5 current sources to obtain parallel data, and compared with the existing method of performing exclusive-or operation by using a shift register, the circuit of the embodiment of the invention omits circuits such as an input data shift register, a reference data shift register, an exclusive-or operator and the like, thereby being beneficial to further simplifying the circuit structure and reducing the circuit area of the correlator.
In a further embodiment, the circuit for detecting data correlation adjusts the voltage values of the first threshold voltage and the second threshold voltage through the adjustable resistor, so as to achieve the purpose of adjusting the detection threshold, and a special comparison set value register is not required to be arranged in the circuit, so that not only can the circuit structure be further simplified, but also the applicability of multi-bit serial data correlation detection can be increased, and the circuit can be applied to intermittent short-sequence data acquisition, and is not a particularly strict application field for sequence acquisition.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a digital correlator of the prior art;
FIG. 2 is a schematic diagram showing a circuit for detecting data correlation according to a first embodiment of the present invention;
fig. 3 shows a schematic structural diagram of a trigger unit according to a second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
It is to be noted that, in the binary data transmission, the high level signal "1" and the low level signal "0" are a relative concept.
Fig. 2 is a schematic diagram showing a structure of a circuit for detecting data correlation according to a first embodiment of the present invention. As shown in fig. 2, the circuit 200 includes a serial-to-parallel conversion module 210, a voltage detection module 220, and a correlation output module 230.
The serial-to-parallel conversion module 210 is configured to receive the serial data signal DATAIN, the sampling clock CLK, and the reference data signal REF, and convert the serial data signal DATAIN into a parallel data signal according to the reference data signal REF and the sampling clock CLK. In a data transmission system, data on the transmitting side is transmitted byte by byte, forming a bit stream arranged in serial order. Each byte is a "0" or "1" of fixed but unimportant length. The serial-to-parallel conversion block 210 samples the serial data signal DATAIN synchronization with the sampling clock CLK and generates a plurality of output signals, which are supplied in parallel to the voltage detection block 220, each of which corresponds to one valid bit data of the parallel data signal.
The voltage detection module 220 receives the parallel data signal and converts the parallel data signal into an analog voltage detection signal Vs.
The correlation output module 230 receives the voltage detection signal Vs and compares the voltage detection signal Vs with the first threshold voltage Vu and the second threshold voltage Vd to determine the correlation between the serial data signal DATAIN and the reference data signal REF. The correlation output module 230 generates a first indication signal LOST and a second indication signal SIG according to the comparison result, wherein the first indication signal LOST represents whether the serial data signal DATAIN and the reference data signal REF are correlated, and the second indication signal SIG represents whether the serial data signal DATAIN and the reference data signal REF are positively correlated or negatively correlated.
When the first indication signal LOST is a low level signal "0", the characterization serial data signal DATAIN is correlated with the reference data signal REF; when the first indicator signal LOST is a high level signal "1", the characterization serial data signal DATAIN is uncorrelated with the reference data signal REF.
On the premise that the first indication signal LOST is a low level signal "0", when the second indication signal SIG is a low level signal "0", the characterization serial data signal DATAIN is positively correlated with the reference data signal REF, that is, the serial data signal DATAIN is the same as the reference data signal REF; when the second indication signal SIG is a high level signal "1", the characterization serial data signal DATAIN is opposite to the reference data signal REF, i.e., the serial data signal DATAIN is the inverse of the reference data signal REF.
Further, the serial-to-parallel conversion module 210 includes a plurality of cascaded trigger units 201 and a plurality of switching units 202 corresponding to the plurality of trigger units 201, and for convenience of description, fig. 2 takes 4 trigger units 201 and switching units 202 as an example for description. Each of the flip-flop cells 201 includes a data input terminal D, a clock terminal Clk, a first output terminal Q + and a second output terminal Q-. The clock terminals Clk of the plurality of flip-flop cells 201 are all connected to the sampling clock Clk, the data input terminal D of the first stage flip-flop cell is configured to receive the serial data signal DATAIN, and the data input terminal D of each stage of flip-flop cells other than the first stage flip-flop cell is connected to the first output terminal Q + of the previous stage of flip-flop cell. Each stage of the flip-flop cell 201 is adapted to process the received data according to the sampling clock CLK to generate a first output data and a second output data at a first output terminal Q + and a second output terminal Q-, respectively.
The plurality of switching units 202 are used for obtaining a plurality of output signals S1-S4 according to the outputs of the plurality of flip-flops 201 and the reference data signal REF. Further, the reference data signal REF is a multi-bit binary number, and each of the switching units 202 is configured to output one of the first output data and the second output data as one valid bit data of the parallel data signal according to a data bit corresponding to the reference data signal REF. Taking the first switching unit as an example, when the first data bit of the reference data signal REF is the high level signal "1", the first switching unit outputs the second output data as the output signal S1; when the first data bit of the reference data signal REF is the low level signal "0", the first switching unit outputs the first output data as the output signal S1. Further, the plurality of switching units 202 are implemented by single-pole double-throw switches, and control terminals of the single-pole double-throw switches are controlled by one data bit of the reference data signal REF.
Further, the voltage detection module 220 includes a plurality of detection resistors R (only detection resistors R1-R4 are shown in the figure) disposed corresponding to the plurality of switching units 202, first ends of the plurality of detection resistors R are respectively connected to output ends of the corresponding switching units 202, and second ends of the plurality of detection resistors R are connected to each other to provide the voltage detection signal Vs.
Further, the correlation output module 230 includes an operational amplifier OPA1, an operational amplifier OPA2, a transistor M1, a transistor M2, and a pull-up resistor Rpull. The operational amplifier OPA1 has an inverting input receiving the first threshold voltage Vu, a non-inverting input receiving the voltage detection signal Vs, and an output for providing a first comparison signal. The non-inverting input of the operational amplifier OPA2 receives the second threshold voltage Vd, the inverting input receives the voltage detection signal Vs, and the output provides a second comparison signal. The control end of the transistor M1 is connected with the output end of the operational amplifier OPA1, the first end is connected with the power supply voltage VCC through a pull-up resistor Rpull, and the second end is grounded. The transistor M2 has a control terminal connected to the output terminal of the operational amplifier OPA2, a first terminal connected to the first terminal of the transistor M1, and a second terminal connected to ground. An intermediate node between the transistor M1 and the transistor M2 is configured to output the first indication signal LOST, and an intermediate node between the transistor M1 and the operational amplifier OPA1 is configured to output the second indication signal SIG.
Further, the related output module 230 further includes a resistor Ru, a resistor Rv, and a resistor Rd sequentially connected in series between the power voltage VCC and the ground. Wherein an intermediate node of the resistor Ru and the resistor Rv is adapted to provide the first threshold voltage Vu, and an intermediate node of the resistor Rv and the resistor Rd is adapted to provide the second threshold voltage Vd. Further, the first threshold voltage Vu is always greater than the second threshold voltage Vd. The transistor M1 and the transistor M2 compare the first comparison signal and the second comparison signal, and the comparison result generates the first indication signal LOST through the pull-up of the pull-up resistor Rpull.
When the voltage detection signal Vs is smaller than the second threshold voltage Vd, the first indication signal LOST is a low level signal "0", and the second indication signal SIG is a low level signal "0"; when the voltage detection signal Vs is greater than the second threshold voltage Vd and the voltage detection signal Vs is less than the first threshold voltage Vu, the first indication signal LOST is a high level signal "1", and the second indication signal SIG is a low level signal "0"; when the voltage detection signal Vs is greater than the first threshold voltage Vu, the first indication signal LOST is a low level signal "0", and the second indication signal SIG is a high level signal "1".
Therefore, the first threshold voltage Vu and the second threshold voltage Vd constitute a detection threshold for detecting correlation, and when the voltage detection signal Vs is higher or lower than the detection threshold, the serial data signal DATAIN is considered to be correlated with the reference data signal REF; when the voltage detection signal Vs is within the detection threshold, the serial data signal DATAIN is considered to be uncorrelated with the reference data signal REF. Therefore, the magnitude of the false alarm probability and the false alarm probability of the correlation detection is determined by the high or low detection threshold (the false alarm means that the correlator considers that the serial data signal DATAIN is correlated with the reference data signal REF when the serial data signal DATAIN is uncorrelated with the reference data signal REF; the false alarm means that the correlator erroneously considers that the serial data signal DATAIN is uncorrelated with the reference data signal REF when the serial data signal DATAIN is correlated with the reference data signal REF).
Furthermore, the resistor Rv is an adjustable resistor, and the magnitudes of the first threshold voltage Vu and the second threshold voltage Vd can be adjusted by adjusting the resistance value of the resistor Rv, so as to achieve the purposes of adjusting the detection threshold of the correlation detection and increasing or reducing the number of data bits allowed to make mistakes.
Fig. 3 shows a schematic structural diagram of a trigger unit according to a second embodiment of the present invention. As shown in FIG. 3, the trigger cell 201 includes current sources I1-I5 and transistors M3-M10. The current source I1, the transistor M3, and the transistor M4 are sequentially connected between the power voltage VCC and the ground, the control terminal of the transistor M3 is connected to the data input terminal D, and the control terminal of the transistor M4 is connected to the clock terminal Clk. The current source I2 and the transistor M5 are in turn connected between the supply voltage VCC and ground, with the control terminal of the transistor M5 connected to the data input terminal D. The current source I3 and the transistor M6 are sequentially connected between the power supply voltage VCC and the first terminal of the transistor M4, and the control terminal of the transistor M6 is connected to the first terminal of the transistor M5. The current source I4, the transistor M7 and the transistor M8 are sequentially connected between the power supply voltage VCC and the ground, the control end of the transistor M7 is connected with the first output end Q +, the first end of the transistor M7 is connected with the second output end Q-, and the control end of the transistor M8 is connected with the first end of the transistor M3. The current source I5, the transistor M9 and the transistor M10 are sequentially connected between the power supply voltage VCC and the ground, a first end of the transistor M9 is connected with a first output end Q +, a control end of the transistor M9 is connected with a second output end Q-, and a control end of the transistor M10 is connected with a first end of the transistor M6.
The data input port D is a bit input port of serial data, the clock terminal Clk is an input port of a local sampling clock, the transistor M4 receives the local sampling clock, the transistors M7-M10 function to output and maintain states of the first output port Q + and the second output port Q-according to states of the transistor M8 and the transistor M10, and the transistor M3, the transistor M5 and the transistor M6 are used for generating input states of the transistor M8 and the transistor M10 under control of the transistor M4. Through synchronization of the local sampling clocks, the transistors M3-M10 generate first output data and second output data at the first output port Q + and the second output port Q-, according to the data at the data input port D, wherein the first output data is identical to the data at the data input port D, and the second output data is opposite to the data at the data input port D.
In the present application, the transistors M1-M10 are implemented by, for example, N-type MOSFETs (N-Metal-Oxide-Semiconductor Field-Effect transistors), and the first terminal, the second terminal, and the control terminal of the N-type MOSFET are a drain, a source, and a gate, respectively.
In summary, the circuit for detecting data correlation according to the embodiment of the present invention includes a serial-to-parallel conversion module, a voltage detection module, and a correlation output module, wherein the voltage detection module converts the parallel data signal into an analog voltage detection signal, the correlation output module compares the voltage detection signal with a first threshold voltage and a second threshold voltage, and determines the correlation between the serial data signal and the reference data signal according to a comparison result. The data correlation is judged in an analog comparison mode, and the resistor and the comparator are adopted to replace an accumulator and a numerical comparator in the existing digital correlator, so that the operation part circuit of the correlation detection is greatly simplified, the circuit structure is simplified, the complexity of the circuit is reduced, and the cost of the correlation detection is reduced.
In a further embodiment, the circuit for detecting data correlation samples and holds serial data by using 8 transistors and 5 current sources to obtain parallel data, and compared with the existing method of performing exclusive-or operation by using a shift register, the circuit of the embodiment of the invention omits circuits such as an input data shift register, a reference data shift register, an exclusive-or operator and the like, thereby being beneficial to further simplifying the circuit structure and reducing the circuit area of the correlator.
In a further embodiment, the circuit for detecting data correlation adjusts the voltage values of the first threshold voltage and the second threshold voltage through the adjustable resistor, so as to achieve the purpose of adjusting the detection threshold, and a special comparison set value register is not required to be arranged in the circuit, so that not only can the circuit structure be further simplified, but also the applicability of multi-bit serial data correlation detection can be increased, and the circuit can be applied to intermittent short-sequence data acquisition, and is not a particularly strict application field for sequence acquisition.
It should be noted that although the device is described herein as being an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be understood by those skilled in the art that conductivity type refers to the mechanism by which conduction occurs, for example by conduction through holes or electrons, and thus does not relate to the doping concentration but to the doping type, for example P-type or N-type. It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it is further understood that the use of relational terms such as first and second, and the like, herein, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A circuit for detecting data dependency, comprising:
the serial-parallel conversion module receives a serial data signal and a reference data signal and converts the serial data signal into a parallel data signal according to the reference data signal and a sampling clock;
the voltage detection module receives the parallel data signals and converts the parallel data signals into analog voltage detection signals;
a correlation output module adapted to compare the voltage detection signal with a first threshold voltage and a second threshold voltage to determine a correlation between the serial data signal and the reference data signal,
wherein the correlation output module is adapted to generate a first indication signal and a second indication signal according to the comparison result, the first indication signal characterizing whether the serial data signal and the reference data signal are correlated, the second indication signal characterizing whether the serial data signal and the reference data signal are positively correlated or negatively correlated.
2. The circuit for detecting data correlation according to claim 1, wherein the correlation output module comprises:
the inverting input end of the first operational amplifier receives the first threshold voltage, and the non-inverting input end of the first operational amplifier receives the voltage detection signal;
a second operational amplifier, wherein a positive phase input end receives the second threshold voltage, and a negative phase input end receives the voltage detection signal;
the control end of the first transistor is connected with the output end of the first operational amplifier, the first end of the first transistor is connected with a power supply voltage through a pull-up resistor, and the second end of the first transistor is grounded;
a second transistor, a control end of which is connected with the output end of the second operational amplifier, a first end of which is connected with the first end of the first transistor, and a second end of which is grounded,
wherein an intermediate node between the first transistor and the second transistor is used for outputting the first indication signal, and an intermediate node between the first transistor and the first operational amplifier is used for outputting the second indication signal.
3. The circuit for detecting data correlation according to claim 2, wherein the correlation output module further comprises first to third resistors connected in series in this order between the power supply voltage and ground,
wherein an intermediate node of the first resistor and the second resistor is adapted to provide the first threshold voltage, and an intermediate node of the second resistor and the third resistor is adapted to provide the second threshold voltage.
4. The circuit for detecting data dependency according to claim 3, wherein the second resistor is an adjustable resistor, and the detection threshold of the data dependency detection can be adjusted by adjusting the resistance of the second resistor.
5. The circuit for detecting data dependency according to claim 1, wherein the serial-to-parallel conversion module comprises:
a plurality of cascaded trigger units, each stage of the trigger units being adapted to process received data according to the sampling clock to generate first output data and second output data;
a plurality of switching units corresponding to the plurality of trigger units, each of the switching units being configured to output one of the first output data and the second output data as one valid data bit of the parallel data signal according to the reference data signal.
6. The circuit for detecting data correlation according to claim 5, wherein the voltage detection module includes a plurality of detection resistors provided corresponding to the plurality of switching units,
first ends of the detection resistors are respectively connected with output ends of the corresponding switching units, and second ends of the detection resistors are connected with each other to provide the voltage detection signal.
7. The circuit of claim 5, wherein each stage of the flip-flop cells comprises a data input terminal, a clock terminal, a first output terminal, and a second output terminal,
wherein a clock terminal of the trigger unit of each stage is configured to receive the sampling clock, a first output terminal is configured to output the first output data, and a second output terminal is configured to output the second output data,
the data input end of the first-stage trigger unit is used for receiving the serial data signal, and the data input end of each stage of trigger unit except the first-stage trigger unit is connected with the first output end of the previous-stage trigger unit to receive the first output data of the previous-stage trigger unit.
8. The circuit for detecting data dependency according to claim 7, wherein each stage of the trigger unit further comprises:
the first current source, the third transistor and the fourth transistor are sequentially connected between a power supply voltage and the ground, the control end of the third transistor is connected with the data input end, and the control end of the fourth transistor is connected with the clock end;
the second current source and the fifth transistor are sequentially connected between the power supply voltage and the ground, and the control end of the fifth transistor is connected with the data input end;
the third current source and the sixth transistor are sequentially connected between the power supply voltage and the first end of the fourth transistor, and the control end of the sixth transistor is connected with the first end of the fifth transistor;
a fourth current source, a seventh transistor and an eighth transistor sequentially connected between the power supply voltage and ground, wherein a control terminal of the seventh transistor is connected to the first output terminal, a first terminal of the seventh transistor is connected to the second output terminal, and a control terminal of the eighth transistor is connected to a first terminal of the third transistor;
the control end of the ninth transistor is connected with the second output end, the first end of the ninth transistor is connected with the first output end, and the control end of the tenth transistor is connected with the first end of the sixth transistor.
9. The circuit for detecting data dependency of claim 8 wherein the first output data is the same as the data received at the data input and the second output data is the opposite of the data received at the data input.
10. The circuit for detecting data dependency according to claim 5, wherein the switching unit is selected from a single-pole double-throw switch, and each data bit of the reference data signal is provided to a control terminal of the corresponding single-pole double-throw switch.
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