CN106057911A - Film transistor, preparation method thereof and logic circuit - Google Patents
Film transistor, preparation method thereof and logic circuit Download PDFInfo
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- CN106057911A CN106057911A CN201610681225.7A CN201610681225A CN106057911A CN 106057911 A CN106057911 A CN 106057911A CN 201610681225 A CN201610681225 A CN 201610681225A CN 106057911 A CN106057911 A CN 106057911A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000007667 floating Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 20
- 239000012528 membrane Substances 0.000 claims description 18
- 239000007769 metal material Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 5
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N SnO2 Inorganic materials O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses a film transistor comprising a substrate, wherein a first structure layer and a second structure layer are successively formed on the substrate, and an insulating dielectric layer is arranged between the first structure layer and the second structure layer; first-Nth gate electrodes, a source electrode and a drain electrode are arranged in the first structure layer at intervals, and the source electrode and the drain electrode are connected through a semiconductor active area; a floating grate electrode is arranged in the second structure layer, the projection of the floating grate electrode on the first structure layer at least covers the partial area of the semiconductor active area and the partial area of each of the first-Nth gate electrodes, and N is an integer larger than 1. The invention further discloses a preparation method of the film transistor and a logic circuit including the film transistor. According to the invention, multi-input and single-output of the basic logic unit circuit are realized by one film transistor, and the process difficulty of the logic circuit is lowered.
Description
Technical field
The present invention relates to technical field of semiconductor device, a kind of thin film transistor (TFT) for logic circuit and system thereof
Preparation Method, further relates to a kind of logic circuit.
Background technology
Along with thin-film transistor technologies develops, high mobility, the film transistor device of high stability are applicable not only to put down
The image element circuit of panel display, applies equally to integrated peripheral drive circuit on substrate.Drive circuit comprises multiple substantially
Logic unit circuit, these basic logic unit circuits, it is directly realized by by thin film transistor (TFT), a basic logical block
Circuit includes that multiple inputs of multiple thin film transistor (TFT), such as logic unit circuit have been connected respectively a film crystal
Pipe.But current non-crystalline silicon or metal oxide thin-film transistor major part are N-type TFT, N-type TFT
The circuit constituted, compares complementary pair shaping circuit, and circuit power consumption is bigger；Additionally, due to basic logic unit circuit is by multiple
Transistor forms, if one of them transistor nonfunctional, then likely results in whole circuit function and lost efficacy.Therefore, multiple crystal
Pipe composition logic unit circuit, it is higher to process dependency, improves the complexity of technique.
Summary of the invention
The deficiency existed in view of prior art, the invention provides a kind of thin film transistor (TFT) and preparation method thereof, this thin film
Transistor application, in logic circuit, is realized multiple inputs of basic logic unit circuit and single by a thin film transistor (TFT)
Output, reduces the technology difficulty of logic circuit.
To achieve the above object, present invention employs following technical scheme:
A kind of thin film transistor (TFT), including substrate, wherein, described substrate is sequentially formed with the first structure sheaf and the second structure
Layer, is provided with insulating medium layer between described first structure sheaf and the second structure sheaf；Described first structure sheaf is provided with mutually
1st～N gate electrode, source electrode and the drain electrode at interval, by semiconductor active region phase between described source electrode and drain electrode
Connect；Described second structure sheaf is provided with a floating gate electrode, the projection on described first structure sheaf of the described floating gate electrode
At least cover the subregion of described semiconductor active region and the described 1st～N gate electrode in each subregion；Its
In, N is the integer more than 1.
Preferably, the projection on described first structure sheaf of the described floating gate electrode covers the whole of described semiconductor active region
Region.
Preferably, the described 1st～the mutual parallel arranged of N gate electrode, described floating gate electrode is on described first structure sheaf
Projection cover the described 1st～N gate electrode in each the area of more than half.
Preferably, N=5～15.
Preferably, the material of described semiconductor active region is metal oxide semiconductor material.
Preferably, the described 1st～the material of N gate electrode and described source electrode and drain electrode be conductive metal material,
The material of described floating gate electrode is conductive metal material or transparent metal oxide conductive material.
Preferably, the material of described insulating medium layer is SiNx or SiOx.
The preparation method of thin film transistor (TFT) as above, gas bag includes step: provides a substrate and sinks over the substrate
Long-pending formation the first conductive membrane layer；By photoetching process described first conductive membrane layer etching formed the spaced 1st～
N gate electrode, source electrode and drain electrode；Formation of deposits semiconductor film layer over the substrate, by photoetching process by described
Semiconductor film layer etching forms described semiconductor active region, obtains described first structure sheaf over the substrate；Described
On one structure sheaf, preparation forms insulating medium layer；Formation of deposits the second conductive membrane layer on described insulating medium layer, by light
Described second conductive membrane layer etching is formed described floating gate electrode by carving technology, it is thus achieved that described second structure sheaf.
Preferably, the thickness of described first conductive membrane layer is 200～500nm, the thickness of described second conductive membrane layer
It is 300～600nm.
Another aspect of the present invention is to provide a kind of logic circuit, and it includes thin film transistor (TFT) as above, described thin
1st～input that N gate electrode is described logic circuit of film transistor, the source electrode of described thin film transistor (TFT) or drain electrode
Outfan for described logic circuit.
Beneficial effect: the thin film transistor (TFT) that the embodiment of the present invention provides, including multiple gate electrodes and a floating gate electrode,
Formed between floating gate electrode with each gate electrode and couple electric capacity, utilize capacitance coupling effect, multiple by single thin film transistor (TFT)
Grid voltage carries out Capacitance Coupled, forms an equivalent voltage, it is achieved the input of an equivalent voltage is corresponding on floating gate electrode
The output (flowing through the electric current of thin film transistor (TFT)) of one electric current, thus realize the logic function of " multi input, single output ".Thus,
Can be directly realized by elementary logic circuit function by this thin film transistor (TFT) single, therefore the thin film transistor (TFT) needed for logic circuit is more
Few, compare the logic function circuit that tradition is complicated, power consumption is lower, and less to process dependency, reduces logic circuit
Technology difficulty, saves production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of the thin film transistor (TFT) that the embodiment of the present invention provides；
Fig. 2 is the plan structure schematic diagram of the thin film transistor (TFT) that the embodiment of the present invention provides；
Fig. 3 is the graphical representation of exemplary of the thin film transistor (TFT) logic circuit that the embodiment of the present invention provides；
Fig. 4 a-Fig. 4 g is the technological process diagram of the preparation method of the thin film transistor (TFT) that the embodiment of the present invention provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, the concrete reality to the present invention below in conjunction with the accompanying drawings
The mode of executing is described in detail.The example of these preferred implementations is illustrated in the accompanying drawings.Shown in accompanying drawing and according to
The embodiments of the present invention that accompanying drawing describes are merely exemplary, and the present invention is not limited to these embodiments.
Here, also, it should be noted in order to avoid having obscured the present invention because of unnecessary details, the most only
Show and according to the closely-related structure of the solution of the present invention and/or process step, and eliminate little with relation of the present invention
Other details.
Refering to Fig. 1 and Fig. 2, the present embodiment provide firstly a kind of thin film transistor (TFT), as it is shown in figure 1, described film crystal
Pipe 100 includes substrate 1 and the first structure sheaf 2 and the second structure sheaf 3 being sequentially formed on substrate 1, described first structure sheaf 2
With second be provided with insulating medium layer 4 between structure sheaf 3.As in figure 2 it is shown, described first structure sheaf 2 is provided with spaced
The the 1st～N gate electrode G1～GN, source electrode 21 and drain electrode 22, pass through quasiconductor between described source electrode 21 and drain electrode 22
Active area 23 is connected with each other.Being provided with a floating gate electrode 31 in described second structure sheaf 3, described floating gate electrode 31 is described first
Projection on structure sheaf 2 at least covers the subregion and the described 1st～N gate electrode G of described semiconductor active region 231~
GNIn each subregion；Wherein, N is the integer more than 1.Wherein, in fig. 2, each in described first structure sheaf 2
Parts use the diagram of perspective to illustrate.
Thin film transistor (TFT) 100 as above, the described 1st～N gate electrode G1～GNCoupling is formed respectively with floating gate electrode 31
Close electric capacity, utilize capacitance coupling effect, from the described 1st～N gate electrode G1～GNThe voltage that (N number of gate electrode altogether) inputs is floating
Form an equivalent voltage on gate electrode 31, described equivalent voltage control source electrode 21 and the leakage of described thin film transistor (TFT) 100
Size of current between electrode 22, thus realize the logic function of " multi input, single output ".Specifically, by described film crystal
Pipe 100 is applied in logic circuit, as it is shown on figure 3, the described 1st～N gate electrode G1～GNCoupling is formed respectively with floating gate electrode 31
Close electric capacity Cg1～CgN, by the described 1st～N gate electrode G1～GNAs the input of logic circuit, by source electrode 21 or electric leakage
Pole 22 is as the outfan of logic circuit.When logic circuit works, the source electrode 21 of described thin film transistor (TFT) 100 connects active
Pole tension Vs, drain electrode 22 connects drain voltage Vd, and the 1st～N gate electrode G1～GNConnect applied signal voltage V respectivelyg1
～VgN, then the equivalent voltage V of formation on floating gate electrode 31efFor:
Vef=(Cg1Vg1+Cg2Vg2+Cg3Vg3+…+CgN VgN)/C, wherein, C=Cg1+Cg2+Cg3+…+CgN.Regulation input letter
Number voltage Vg1～VgN, it is thus achieved that different equivalent voltage VefSo that flow through the electric current I of thin film transistor (TFT) 100sdDifference, by with in advance
If reference current I0Compare, it is thus achieved that corresponding output logic signal, such as, work as Isd<I0, then logic value " 0 " is exported；When
Isd>I0, then logic value " 1 " is exported.Thus, basic logic electricity can be directly realized by by single described thin film transistor (TFT) 100
Road function, therefore the thin film transistor (TFT) needed for logic circuit is less, compares the logic function circuit that tradition is complicated, and power consumption is lower,
And less to process dependency, reduce the technology difficulty of logic circuit, save production cost.
Wherein, the input channel of described logic circuit, quantity N of the gate electrode of the most described thin film transistor (TFT) 100 can root
According to being actually needed setting.In common application case, the span of N commonly 5～15.
In the present embodiment, as in figure 2 it is shown, the described floating gate electrode 31 projection on described first structure sheaf 2 covers institute
State the Zone Full of semiconductor active region 23.Described 1st～N gate electrode G1～GNMutually parallel arranged, described floating gate electrode 31
Projection on described first structure sheaf 2 covers the described 1st～N gate electrode G1～GNIn each the area of more than half.
Wherein, in the present embodiment, the material of described semiconductor active region 23 is metal oxide semiconductor material, such as
It is ZnO, In2O3、SnO2Deng material.Described 1st～N gate electrode G1～GNAnd described source electrode 21 and the material of drain electrode 22
For metal materials such as conductive metal material, e.g. Al, Mo, Cu, Ag, it can be the structure of layer of metal or multiple layer metal.
The material of described floating gate electrode 31 is conductive metal material or transparent metal oxide conductive material, described conductive metal material example
The metal material such as Al, Mo, Cu, Ag in this way, it can be the structure of layer of metal or multiple layer metal；Described transparent metal oxide
Conductive material can be such as ITO or IZO.The material of described insulating medium layer 4 is SiNx or SiOx.
The preparation method of thin film transistor (TFT) that the present embodiment provide is described below, refering to Fig. 4 a-Fig. 4 f, its preparation method bag
Include step:
One, as shown in fig. 4 a, it is provided that a substrate 1 formation of deposits the first conductive membrane layer 2a on described substrate 1.Described
The material of the first conductive membrane layer 2a is the metal materials such as conductive metal material, e.g. Al, Mo, Cu, Ag, and it can be one layer
Metal or the structure of multiple layer metal.The thickness of described first conductive membrane layer 2a can be chosen as 200～500nm, in this enforcement
Example is chosen as 250nm.
Two, as shown in Figure 4 b, by photoetching process described first conductive membrane layer etching formed the spaced 1st～
3rd gate electrode G1、G2、G3(merely exemplary in preparation technology illustrate 3 gate electrodes), source electrode 21 and drain electrode 22.
Three, as illustrated in fig. 4 c, formation of deposits semiconductor film layer 2b, described semiconductor film layer 2b on described substrate 1
At least cover the region between described source electrode 21 and drain electrode 22 and source electrode 21 and drain electrode 22.As shown in figure 4d, logical
Cross photoetching process and described semiconductor film layer 2b etching is formed described semiconductor active region 23, thus, described substrate 1 obtains
Obtain described first structure sheaf 2.
Four, as shown in fig 4e, on described first structure sheaf 2, preparation forms insulating medium layer 4.Described insulating medium layer 4
Material be SiNx or SiOx, its thickness can be chosen as 500～1000nm, is chosen as 600nm in the present embodiment.
Five, as shown in fig. 4f, formation of deposits the second conductive membrane layer 3a on described insulating medium layer 4.Described second leads
The material of thin film layer 3a is conductive metal material or transparent metal oxide conductive material, and described conductive metal material is e.g.
The metal materials such as Al, Mo, Cu, Ag, it can be the structure of layer of metal or multiple layer metal；Described transparent metal oxide conducts electricity
Material can be such as ITO or IZO.The thickness of described second conductive membrane layer 3a can be chosen as 300～600nm, in this reality
Execute and example is chosen as 400nm.
Six, as shown in figure 4g, by photoetching process, described second conductive membrane layer 3a etching is formed described floating gate electrode
31, thus, described insulating medium layer 4 obtains described second structure sheaf 3, finally prepares thin film transistor (TFT) 100.
In sum, the thin film transistor (TFT) that the embodiment of the present invention provides, including multiple gate electrodes and a floating gate electrode,
Formed between floating gate electrode with each gate electrode and couple electric capacity, utilize capacitance coupling effect, multiple by single thin film transistor (TFT)
Grid voltage carries out Capacitance Coupled, forms an equivalent voltage, it is achieved the input of an equivalent voltage is corresponding on floating gate electrode
The output (flowing through the electric current of thin film transistor (TFT)) of one electric current, thus realize the logic function of " multi input, single output ".Thus,
Can be directly realized by elementary logic circuit function by this thin film transistor (TFT) single, therefore the thin film transistor (TFT) needed for logic circuit is more
Few, compare the logic function circuit that tradition is complicated, power consumption is lower, and less to process dependency, reduces logic circuit
Technology difficulty, saves production cost.
It should be noted that in this article, the relational terms of such as first and second or the like is used merely to a reality
Body or operation separate with another entity or operating space, and deposit between not necessarily requiring or imply these entities or operating
Relation or order in any this reality.And, term " includes ", " comprising " or its any other variant are intended to
Comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include that those are wanted
Element, but also include other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that
Including process, method, article or the equipment of described key element there is also other identical element.
The above is only the detailed description of the invention of the application, it is noted that for the ordinary skill people of the art
For Yuan, on the premise of without departing from the application principle, it is also possible to make some improvements and modifications, these improvements and modifications also should
It is considered as the protection domain of the application.
Claims (10)
1. a thin film transistor (TFT), including substrate, it is characterised in that be sequentially formed with the first structure sheaf and second on described substrate
Structure sheaf, is provided with insulating medium layer between described first structure sheaf and the second structure sheaf；Described first structure sheaf is provided with
The 1st spaced～N gate electrode, source electrode and drain electrode, passes through semiconductor active between described source electrode and drain electrode
District is connected with each other；Being provided with a floating gate electrode in described second structure sheaf, described floating gate electrode is on described first structure sheaf
Projection at least cover the subregion of described semiconductor active region and the described 1st～N gate electrode in each part district
Territory；
Wherein, N is the integer more than 1.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described floating gate electrode is on described first structure sheaf
Projection cover described semiconductor active region Zone Full.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that the described 1st～N gate electrode arrange the most parallel
Row, described floating gate electrode on described first structure sheaf projection cover the described 1st～N gate electrode in each half with
On area.
4. according to the arbitrary described thin film transistor (TFT) of claim 1-3, it is characterised in that N=5～15.
5. according to the arbitrary described thin film transistor (TFT) of claim 1-3, it is characterised in that the material of described semiconductor active region is
Metal oxide semiconductor material.
6. according to the arbitrary described thin film transistor (TFT) of claim 1-3, it is characterised in that the described 1st～N gate electrode and institute
The material stating source electrode and drain electrode is conductive metal material, and the material of described floating gate electrode is conductive metal material or transparent gold
Belong to oxide conducting material.
7. according to the arbitrary described thin film transistor (TFT) of claim 1-3, it is characterised in that the material of described insulating medium layer is
SiNx or SiOx.
8. the preparation method of the thin film transistor (TFT) as described in claim 1-7 is arbitrary, it is characterised in that include step:
One substrate formation of deposits the first conductive membrane layer over the substrate are provided；By photoetching process by described first conduction
Thin layer etching forms the 1st spaced～N gate electrode, source electrode and drain electrode；
Formation of deposits semiconductor film layer over the substrate, forms institute by photoetching process by described semiconductor film layer etching
State semiconductor active region, obtain described first structure sheaf over the substrate；
On described first structure sheaf, preparation forms insulating medium layer；
Formation of deposits the second conductive membrane layer on described insulating medium layer, by photoetching process by described second conductive membrane layer
Etching forms described floating gate electrode, it is thus achieved that described second structure sheaf.
The preparation method of thin film transistor (TFT) the most according to claim 8, it is characterised in that described first conductive membrane layer
Thickness is 200～500nm, and the thickness of described second conductive membrane layer is 300～600nm.
10. a logic circuit, it is characterised in that including the arbitrary described thin film transistor (TFT) of claim 1-7, described thin film is brilliant
1st～input that N gate electrode is described logic circuit of body pipe, the source electrode of described thin film transistor (TFT) or extremely institute of leaking electricity
State the outfan of logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610681225.7A CN106057911A (en) | 2016-08-17 | 2016-08-17 | Film transistor, preparation method thereof and logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610681225.7A CN106057911A (en) | 2016-08-17 | 2016-08-17 | Film transistor, preparation method thereof and logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106057911A true CN106057911A (en) | 2016-10-26 |
Family
ID=57194886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610681225.7A Pending CN106057911A (en) | 2016-08-17 | 2016-08-17 | Film transistor, preparation method thereof and logic circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN106057911A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982462A (en) * | 1996-03-12 | 1999-11-09 | Frontec Incorporated | Inverse stagger or planar type thin-film transistor device and liquid-crystal display apparatus having floating gate electrode which is capacitively coupled with one or more input electrodes |
| CN101903936A (en) * | 2007-11-02 | 2010-12-01 | 剑桥显示技术有限公司 | Pixel driver circuits |
-
2016
- 2016-08-17 CN CN201610681225.7A patent/CN106057911A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982462A (en) * | 1996-03-12 | 1999-11-09 | Frontec Incorporated | Inverse stagger or planar type thin-film transistor device and liquid-crystal display apparatus having floating gate electrode which is capacitively coupled with one or more input electrodes |
| CN101903936A (en) * | 2007-11-02 | 2010-12-01 | 剑桥显示技术有限公司 | Pixel driver circuits |
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