CN106054710A - Intelligent control system for eating house - Google Patents
Intelligent control system for eating house Download PDFInfo
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- CN106054710A CN106054710A CN201610447740.9A CN201610447740A CN106054710A CN 106054710 A CN106054710 A CN 106054710A CN 201610447740 A CN201610447740 A CN 201610447740A CN 106054710 A CN106054710 A CN 106054710A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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- Automation & Control Theory (AREA)
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Abstract
The invention discloses an intelligent control system for an eating house. The system comprises a plurality of electrical appliance controllers and a main controller. A cyclic wave discrimination circuit is installed in the main controller and each electrical appliance controller and is used for generating synchronous time of the system and keeping the actions of the system consistent, a small telephone program control exchanger for remote control of electrical appliances is installed in the eating house, the exchanger transmits digital signals for receiving instruction codes to the main controller via an interface circuit, and the main controller executes corresponding operations after decoding.
Description
(1) technical field:
The present invention relates to a kind of eating house intelligent control system, comprise multiple appliance controller and a main controller.?
Main controller and each appliance controller are respectively mounted cycle discriminator circuit, keep system acting for producing the lock in time of system
Unanimously, the remote control for electrical equipment of the babyphone programme-controlled exchange is installed in eating house, and switch will receive the number of instruction code
Word signal interface circuit sends main controller to, main controller perform corresponding operating after decoding.
(2) background technology:
Thered is provided the control system of power supply by power network, its each electronic equipment or intermodule are all to be communicated by special circuit,
Correct the timing time of each electronic equipment or electronic module, reach to run simultaneously purpose.Owing to using special circuit communication to make
Wiring complicates and increases cost, if timing time is not corrected by line traffic, then due to tradition timing error, runs number
After hour, its accumulation timing error can make system control action inconsistent, is likely to result in system crash, often changes at some and sets
Meter, its products application of occasion that wiring installation amount is big is restricted.
(3) summary of the invention:
The present invention relates to eating house intelligent control system, can in the winter time or shopkeeper in summer uses mobile phone to pass through telephone network
Open water heater or air-conditioning in advance, it is simple to wash rapidly dish and reception client.It comprises multiple appliance controller and a main controller.
On the main switchboard of eating house, miniature circuit breaker comprises multichannel independent air switch, and it is guide tracked installation and presser type wiring reconfiguration
Convenient, each air switch controls a road electric appliance load, needs to select an air switch according to system, air switch it
One electrical switch of rear installation, this electrical switch parallel connection isolating diode.Main controller and each appliance controller are respectively mounted
Cycle discriminator circuit, keeps system acting consistent for producing, respectively install simultaneously in its telecommunication circuit the lock in time of system
One communications electronics switch, switch drive module.During communication, main controller turns off electrical switch and connects its communications electronics switch,
Through isolating diode, civil power is sent into system, and system uses half wave communication and half-wave through electric lines of force to power, each appliance controller
When can't detect power network and being isolated the half-wave voltage signal that diode blocks, i.e. turn off its electric appliance load power supply, connect communication electricity
Son switch；Otherwise, when switching to before all-wave from half-wave, main controller first sends switching command to each appliance controller, turns off communication
Electrical switch.The output of each appliance controller is serially connected with the circuit of former socket or switch through Phototube Coupling and bidirectional triode thyristor
In, it is achieved its load energized power and control of time, and it is convenient to change design, need not break wall paper line.
The switch drive module of communications electronics switch is that one tunnel is used for each electricity from electric power netting twine point two-way after resistance blood pressure lowering
Device controller, it is connected to the single-chip processor i/o mouth of each appliance controller through reversal connection diode, bears in clock timer timing to cycle
During half-wave, scan this I/O mouth, be in half-wave communications status without signal i.e. system；Another road is used for each electrical equipment control
Device and main controller, communication therebetween is that this Lu Jingzheng connects diode by controlling lock in time to keep communication operation consistent over a long time
After isolation cycle bears half-wave further, being connected to comparator input terminal, its reference voltage is 100Mv to 200Mv, available diode
Pressure drop obtains through electric resistance partial pressure, and therefore the outfan of comparator is square-wave signal, and it creates after the diode-isolated just connect
Corresponding power network cycle bears the positive square-wave signal of half-wave, is connected to the I/O mouth of single-chip microcomputer, and single-chip microcomputer is held when scanning positive square-wave signal
Row traffic operation, this positive square-wave signal is additionally operable to drive communications electronics switch, and therefore communications electronics switchs when cycle positive half-wave
Turning off, cycle is connected when bearing half-wave.Communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode, and carries out letter
Number conditioning, during sign off under main controller control, make drive circuit turn off communications electronics switch.
System installs a babyphone programme-controlled exchange, and one of them extension number is used for appliance remote control.This extension number
It is saved in mobile phone with the synopsis of instruction code Yu instruction, and prevents the data of instruction code from letting out by methods such as screen locking passwords
Close.During communication, owner sends the numeral of instruction code from base or mobile phone, and switch is decoded by dual-tone multifrequency after caller is dialled
After device obtains this extension set calling telephone number, simulate off-hook, and keep dual-tone multifrequency to receive state, to receive instruction code letter
Number, as sent out with mobile phone: " switch telephone number " P " numeral of instruction code ", wherein " P " can pin mobile phone simulating keyboard
* key obtain, some looms are to press * key to obtain for 2-3 time, or key in after waiting switch solidification voice message in the chips again
Instruction code, after sign off, switch sends, through interface circuit, the digital signal receiving instruction code to main controller, by leading
Corresponding operating is performed after control device decoding.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three examination points and realizes sentencing the identification of cycle signal
Fixed, the recycling cycle time sets up lock in time, it is achieved main controller and the synchronous operation of each appliance controller in system.
The cycle discriminator circuit structural representation of main controller and each appliance controller is as in figure 2 it is shown, used hysteresis by three
The voltage comparator composition of comparator, all comprises filter circuit, the reference voltage of its voltage comparator in each voltage comparator
Thered is provided by mu balanced circuit.System arranges clock timer and synchrotimer.If be detected that adjacent two cycle signals are equal
It is true, then takes out the clock timer timing time between these two adjacent cycle signal zero passages, be sequentially stored in the cycle time
In memory element, this cycle time memory cell can deposit 100 cycle times, is often stored in a cycle time, all when being filled with
First remove the cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value to reflect
Cycle signal the most to be identified, to reduce the impact of power network frequency fluctuation, uses three to screen point simultaneously and reduces erroneous judgement probability.
Three comparators are respectively used to three and screen point, i.e. screen point 0, examination point 1, screen point 2, as shown in Figure 1.In week
At the cycle zero passage of ripple positive half cycle ascent stage, i.e. screen point 0 and voltage zero-crossing comparator is set, due to power network cycle negative half period quilt
Commutation diode is isolated, and in order to improve accuracy of detection, the signal input part series diode again in voltage zero-crossing comparator is isolated
Negative half period, its reference voltage brings up to 10mv to 100mv from zero, and depending on the offset voltage of comparator, this reference voltage can profit
Obtain through electric resistance partial pressure with diode drop.Remaining two comparator is separately positioned on cycle positive half cycle ascent stage, crest voltage
35% to 50% place screen point 1 and 50% to the 70% examination point 2 at place.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, works as cycle
During voltage zero-cross, it is arranged on the output voltage upset of voltage zero-crossing comparator V0 screening point 0, produces at its voltage trailing edge
Interrupt, record its zero crossing break period Th0 and close interruption；Hereafter, voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Output voltage, when week, wave voltage reached the threshold voltage of V1, output voltage overturns from high to low, when scanning records its upset
Between Th1；Voltage comparator V2 output voltage Th2 flip-flop transition at point 2 screened in same scanning record.By Th0 and voltage zero-cross
Output voltage setting value Ts0 flip-flop transition of comparator V0 is made comparisons；The output voltage upset of Th1 and voltage comparator V1
Output voltage setting value Ts2 flip-flop transition of time setting value Ts1 and Th2 and voltage comparator V2 is made comparisons respectively, as
Fruit is in the range of allowable error, then this discriminator signal detected is true, is otherwise false.Above-mentioned judge discriminator signal as true time,
Calculate the clock timer meter between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Time time Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle
Signal is true, at this moment preserves Tzu and takes 20ms and be added with synchrotimer timing time, and the value that will add up is stored in synchrotimer
In.
When clock timer starts timing with cycle voltage zero-cross, then timing is to opening the break period between 16ms to 18.5ms
Open interruption during setting value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt.
After system boot, clock timer starts timing, when first cycle voltage zero-cross being detected, is arranged on examination
The output voltage upset of voltage zero-crossing comparator V0 of point 0, thus produce interruption, take out the time T0 of cycle voltage over zero
Preserving, reset by clock timer and start timing, at this moment cycle time voltage crosses zero Th0 is 0, and above-mentioned side pressed by single-chip microcomputer simultaneously
Method scans and judges discriminator signal.Due to detection is first cycle, and clock timer is to start when cycle voltage zero-cross
Timing, the value of its Th0, Th1 and Th2 must deduct open the difference of break period setting value Tk plus cycle time 20ms, if
Three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time, under
Once i.e. for the first time opening the break period takes Tk.Being otherwise fictitious time, now the clock timer time must continue detection plus T0.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving the cycle time of detection,
Therefore the clock timer timing time between twice cycle signal zero passage is to make comparisons with cycle time 20ms, it is determined that cycle signal
For true time, then it is to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, preserves the standard cycle time i.e. for the first time
20ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all when opening interruption by clock meter the most every time
Time device reset after restart timing, and be when opening interruption, the standard cycle time to be counted in synchrotimer, open interruption
Rear clock timer reset, otherwise judges cycle signal as fictitious time, now the clock timer time must add T1=T0+Tk, continue
Continuous first cycle of detection the most again.After first cycle signal of detection is very, recover above-described cycle
Signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, opens the break period and all open the break period at this next time
After, when meansigma methods Tz of time delay cycle time, open interruption, and have no progeny in opening time delay Tns time close and interrupt, pass is set when interrupting
Between be when cycle signal screen point 0 time do not produce interruption, at this moment must be at the setting time point more than Ts0 allowable error scope
Starting scanning, and scanning examination point 1 is with when screening point 2, voltage comparator output voltage does not produce upset, all interrupts in pass
Time Tns closes and interrupts and stop scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and weight after resetting
Newly start timing, close during timing to Tns and interrupt, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and when this cycle judges, discriminator signal is
Vacation, or the cycle time detected compare with meansigma methods Tz of cycle time and exceed setting cycle time error Tzv, or clock meter
Time device timing to when closing break period setting value Tns, voltage zero-crossing comparator V0 output voltage does not overturns, in not producing
Disconnected, then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time after Tz, open interruption, clock timer have no progeny in opening clearing and timing, during timing to Tns
Close and interrupt, judge the cycle signal true and false the most every time, though if false or this detection discriminator signal is true last time is false, then take
N, restores after N+1 in memorizer.
When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by N zero setting in memorizer, and recover to make
Using setting value Tks, the value at this moment taking (N+1) × 20ms is added in synchrotimer.
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by setting flip-flop transition with voltage comparator output voltage
Definite value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen a some signal true and false, can select: Th0, Th1, Th2 are
This cycle discriminator signal of true time is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true time, should
Cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, due to main controller and each electrical equipment in system
Controller, the Tz value of its detection may be different with N value, and at this moment, power network frequency cumulative error, when being likely to result in synchrotimer
Between cannot by true cycle signal being detected time corrected, when detecting that cycle signal is true time, at this moment use clock meter
Time device accumulative clocking value be directly added in synchrotimer, to reduce the asynchronous time of system, accumulative clocking value is N × Tz
+20ms.In the case of power network normal operation, N is much smaller than 25.
The cycle time error Tzv allowed and setting value flip-flop transition of voltage comparator output voltage, by test assessment
Take its meansigma methods to obtain.
(4) accompanying drawing explanation:
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural representation；
Fig. 3 is the circuit structure block diagram of eating house intelligent control system.
(5) detailed description of the invention:
Fig. 3 is that eating house intelligent control system circuit structure block diagram includes: main controller 10, communications electronics switch
11, switch drive module 12, interface circuit 13, babyphone programme-controlled exchange 14, electrical equipment 15, cycle screen electricity
Road 16, appliance controller 17, electrical switch 18.Wherein communications electronics switch 11, switch drive module 12, cycle
During in discriminator circuit 16 and Fig. 2, single-chip microcomputer U0 is included in appliance controller 17 and main controller 10 respectively, electronic cutting
Close 18, communications electronics switch 11 use bidirectional triode thyristors as switch, original in on-off circuit of electrical equipment 15 finger
Electrical equipment.
Fig. 2 is the structural representation of cycle discriminator circuit 16, by: input circuit S0, voltage zero-cross detection module
V0, voltage comparator V1 and voltage comparator V2 are constituted.Single-chip microcomputer U0 refers to appliance controller 17 and main controller
Single-chip microcomputer in 10.Input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to electricity
The input voltage that pressure comparator is the most stable.Single-chip microcomputer U0 uses 89C55WD, voltage zero-cross detection module V0, voltage
Comparator V1, voltage comparator V2 all use special voltage comparator LM339, and its reference voltage is to use stabilivolt
Mu balanced circuit carrys out the threshold voltage of burning voltage comparator.
When mains AC voltage cycle signal zero passage, the output voltage saltus step of voltage zero-cross detection module V0, single
Sheet machine U0 produces interruption, records the break period, and single-chip microcomputer U0 is additionally operable to scanning voltage comparator V1 and voltage ratio simultaneously
The relatively output voltage of device V2, records bound-time, is used for judging power network cycle signal thus produces when output voltage saltus step
Raw lock in time.
Microprocessor AT89C2051 in interface circuit 13 is provided with I2C serial communication module, is used for entering between main controller
Row communication, its EEPRAM is used for preserving data.During communication, select institute's palpus code from cell-phone function interface, by telephone network to little
Type telephone exchanger sends data, after main controller receives relevant character string, is translated into corresponding function and carries out
Control or communication.
Claims (2)
1. the present invention relates to eating house intelligent control system, it is characterized in that, an electrical switch is installed after air switch,
This electrical switch parallel connection isolating diode, is respectively mounted cycle discriminator circuit in main controller and each appliance controller, is used for producing
The lock in time of raw system, simultaneously communications electronics switch, switch drive module of each installation in its telecommunication circuit, system is adopted
Power with half wave communication and the half-wave through electric lines of force, each appliance controller also can't detect power network be isolated diode block
Half-wave voltage signal time, i.e. turn off its electric appliance load power supply, connect communications electronics switch；The output of each appliance controller is through photoelectricity
Isolation and bidirectional triode thyristor are serially connected with in former socket or on-off circuit, it is achieved its load energized power and control of time；
The switch drive module of communications electronics switch is that one tunnel is used for each electrical equipment control from electric power netting twine point two-way after resistance blood pressure lowering
Device processed, it is connected to the single-chip processor i/o mouth of each appliance controller through reversal connection diode, bears half-wave in clock timer timing to cycle
Time, scan this I/O mouth, be in half-wave communications status without signal i.e. system；Another road for each appliance controller and
Main controller, this Lu Jingzheng connects diode and isolates after cycle bears half-wave further, is connected to comparator input terminal, and its reference voltage is
100Mv to 200Mv, available diode drop obtains through electric resistance partial pressure, and therefore the outfan of comparator is square-wave signal, its warp
Create corresponding power network cycle after the diode-isolated just connect and bear the positive square-wave signal of half-wave, be connected to the I/O mouth of single-chip microcomputer, single
Sheet machine performs traffic operation when scanning positive square-wave signal, and this positive square-wave signal is additionally operable to drive communications electronics switch；System is pacified
Fill a babyphone programme-controlled exchange, one of them extension number is used for appliance remote control, this extension number and instruction code and finger
The synopsis of order is saved in mobile phone, and owner sends the numeral of instruction code from base or mobile phone, and reception is instructed generation by switch
The digital signal of code sends main controller to through interface circuit, main controller perform corresponding operating after decoding；
Cycle discriminator circuit is the positive half cycle ascent stage utilizing power network cycle, takes three and screens the some realization knowledge to cycle signal
Not judging, the recycling cycle time sets up lock in time, and system arranges clock timer and synchrotimer, if be detected that phase
Two the cycle signals faced are very, then when taking out the clock timer timing between these two adjacent cycle signal zero passages
Between, sequentially it is stored in cycle time memory cell, is often stored in a cycle time when being filled with 100 cycle time, the most first removes
The cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value to differentiate to wait to know
Other cycle signal；
Three comparators are respectively used to three and screen point, i.e. screen point 0, examination point 1, screen point 2, in the cycle positive half cycle ascent stage
Cycle zero passage at, i.e. screen point and 0 voltage zero-crossing comparator be set, the signal input part in voltage zero-crossing comparator concatenates two again
Pole pipe isolation negative half period, its reference voltage is 10mv to 100mv, and depending on the offset voltage of comparator, this reference voltage can profit
Obtaining through electric resistance partial pressure with diode drop, remaining two comparator is separately positioned on cycle positive half cycle ascent stage, crest voltage
35% to 50% place screen point 1 and 50% to the 70% examination point 2 at place；
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, when week wave voltage
During zero passage, it is arranged on the output voltage upset of the voltage zero-crossing comparator screening point 0, produces at its voltage trailing edge and interrupt, note
Record its zero crossing break period Th0 and close interruption；Hereafter, the output electricity of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Pressure, when week, wave voltage reached the threshold voltage of voltage comparator V1, output voltage overturns from high to low, and scanning records it and turns over
Turn time Th1；Th2 flip-flop transition of voltage comparator V2 output voltage at point 2 screened in same scanning record, if described in turn over
The time that turns, this discriminator signal then detected was true in the range of allowable error, was otherwise false, above-mentioned judged that discriminator signal is as true
Time, calculate the clock timer between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Timing time Tzu, makes comparisons it with meansigma methods Tz of cycle time, if less than setting cycle time error Tzv, all
Ripple signal is true, at this moment preserves Tzu and takes 20ms and be added with synchrotimer timing time, and the value that will add up is stored in time synchronisation
In device；
When clock timer starts timing with cycle voltage zero-cross, then timing set to the break period of opening between 16ms to 18.5ms
Open interruption during value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt；
When first cycle voltage zero-cross being detected, it is arranged on the output voltage upset of the voltage zero-crossing comparator screening point 0,
Thus producing interruption, the time T0 taking out cycle voltage over zero preserves, and is reset by clock timer and starts timing, at this moment week
Wave voltage zero-crossing timing Th0 is 0, and single-chip microcomputer scans as stated above and judges discriminator signal, and the value of its Th0, Th1 and Th2 is equal
The difference of break period setting value Tk, if three discriminator signals are true, the week of taking-up must be deducted open plus cycle time 20ms
The time T0 of wave voltage zero crossing is stored in synchrotimer as initial time, i.e. for the first time opens the break period next time and takes
Tk, is otherwise fictitious time, and now the clock timer time must continue detection plus T0；
When first and adjacent second cycle voltage zero-cross being detected, it is determined that cycle signal is true time, then be to take 20ms to subtract
The difference of Th0 is added with synchrotimer timing time, and clock timer of having no progeny in opening resets, and otherwise judges that cycle signal is as false
Time, now the clock timer time must continue first cycle of detection the most again plus T1=T0+Tk, work as detection
First cycle signal be very after, recover above-described cycle signal determining；
If be detected that cycle signal is false, open the break period all after this opens the break period, when time delay cycle next time
Between meansigma methods Tz time open interruption, and have no progeny in opening time delay Tns time close and interrupt, arranging the pass break period is when cycle signal is discriminated
Not closing the interruption of break period Tns pass for fictitious time and stopping scanning, Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and again opens after resetting
Beginning timing, closes during timing to Tns and interrupts, repeat said process, if described in the upper cycle signal that detects be true, this cycle
During judgement, discriminator signal is false, then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and deposits
Storage, open the break period is to open the break period in last time to open interruption after Tz next time, and clock timer is had no progeny clearing in opening
And timing, during timing to Tns close interrupt, the most every time judge the cycle signal true and false, though if false or this detection discriminator signal
It is true but last time is false, then takes N, restore after N+1 in memorizer；
When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by N zero setting in memorizer, and recover use and set
Definite value Tks, the value at this moment taking (N+1) × 20ms is added in synchrotimer；
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing；
When judging to screen the some signal true and false, select: it is true that Th0, Th1, Th2 are this cycle discriminator signal of true time, or Th0 is
Very, one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true time, and this cycle discriminator signal is true, depending on to judging cycle letter
Depending on number true and false difference requires, if N more than 25 to 70 between a setting value, use the accumulative clocking value of clock timer
Directly being added in synchrotimer, accumulative clocking value is N × Tz+20ms.
Eating house the most according to claim 1 intelligent control system, it is characterised in that including:
Main controller 10, communications electronics switch 11, switch drive module 12, interface circuit 13, the program control friendship of babyphone
Change planes 14, cycle discriminator circuit 16, appliance controller 17, electrical switch 18, wherein single-chip microcomputer U0 and the electricity that communicates
Son switch 11, switch drive module 12 and cycle discriminator circuit 16 are included in appliance controller 17 and master control respectively
In device 10；
Cycle discriminator circuit 16 is by input circuit S0, voltage zero-cross detection module V0, voltage comparator V1 and voltage
Comparator V2 is constituted, and input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to
The input voltage that voltage comparator is the most stable；
Single-chip microcomputer in interface circuit 13 is provided with I2C serial communication module, is used for communicating between main controller, its
EEPRAM is used for preserving data.
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| CN106054710B (en) | 2018-12-04 |
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