CN106033735A - Substrate Processing Apparatus, and Method of Manufacturing Semiconductor Device - Google Patents
Substrate Processing Apparatus, and Method of Manufacturing Semiconductor Device Download PDFInfo
- Publication number
- CN106033735A CN106033735A CN201510111989.8A CN201510111989A CN106033735A CN 106033735 A CN106033735 A CN 106033735A CN 201510111989 A CN201510111989 A CN 201510111989A CN 106033735 A CN106033735 A CN 106033735A
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- substrate
- temperature
- hard mask
- gas
- film
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- 239000000758 substrate Substances 0.000 title claims abstract description 137
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000012545 processing Methods 0.000 title description 29
- 238000000034 method Methods 0.000 claims abstract description 122
- 230000008569 process Effects 0.000 claims abstract description 97
- 238000005530 etching Methods 0.000 claims abstract description 67
- 238000009826 distribution Methods 0.000 claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims description 52
- 238000010438 heat treatment Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000007789 gas Substances 0.000 description 203
- 239000010408 film Substances 0.000 description 120
- 235000012431 wafers Nutrition 0.000 description 112
- 229910052756 noble gas Inorganic materials 0.000 description 32
- 230000015572 biosynthetic process Effects 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 30
- 239000006185 dispersion Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000003860 storage Methods 0.000 description 8
- 230000009471 action Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000011144 upstream manufacturing Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000003028 elevating effect Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- AHJCYBLQMDWLOC-UHFFFAOYSA-N n-methyl-n-silylmethanamine Chemical compound CN(C)[SiH3] AHJCYBLQMDWLOC-UHFFFAOYSA-N 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- BUEYUOWUKCZJSK-UHFFFAOYSA-N Cl[Si]([Si](Cl)(Cl)Cl)(Cl)Cl.Cl.Cl.Cl.Cl.Cl.Cl Chemical compound Cl[Si]([Si](Cl)(Cl)Cl)(Cl)Cl.Cl.Cl.Cl.Cl.Cl.Cl BUEYUOWUKCZJSK-UHFFFAOYSA-N 0.000 description 1
- NNJVILVZKWQKPM-UHFFFAOYSA-N Lidocaine Chemical compound CCN(CC)CC(=O)NC1=C(C)C=CC=C1C NNJVILVZKWQKPM-UHFFFAOYSA-N 0.000 description 1
- 229910007245 Si2Cl6 Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229920013822 aminosilicone Polymers 0.000 description 1
- 125000006309 butyl amino group Chemical group 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- NTQGILPNLZZOJH-UHFFFAOYSA-N disilicon Chemical compound [Si]#[Si] NTQGILPNLZZOJH-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229960004194 lidocaine Drugs 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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Abstract
Provided is a configuration capable of suppressing a variation in characteristics of transistor. The configuration includes: a process chamber; a gas supply unit configured to supply a hard mask forming gas into the process chamber; a substrate support table configured to support a substrate Wn of an nth lot having a film to be etched formed thereon; a heater embedded in the substrate support table; and a controller configured to control a temperature distribution of the heater based on an etching information of a substrate Wm of an mth lot processed prior to the nth lot.
Description
Technical field
The present invention relates to lining processor, the manufacture method of semiconductor device, program.
Background technology
In recent years, semiconductor device had highly integrated trend.It is accompanied by this, semiconductor device
The pattern dimension of the transistor used is by notable miniaturization.Such as forming the grid electricity of transistor
Implement during pole.The width of gate electrode is in the situation of 45nm generation crystal pipe, it is desirable to e.g., less than
40nm.These patterns lead to hard mask and/or the formation process of resist film, photo-mask process,
And etching work procedure etc. is formed.
Summary of the invention
The problem that invention is to be solved
But use the situation of the semiconductor device of multiple transistor, inclined for rejection
Difference, it is desirable to the performance of unified each transistor.In order to unify performance, preferably unify and affect crystal
The gate electrode width that the channel length of the characteristic of pipe is suitable.The permissible value of the deviation of gate electrode width
For such as gate electrode width about about 10%.
Therefore it is an object of the invention to, it is provided that the knot of the deviation of the characteristic of transistor can be suppressed
Structure.
For solving the means of problem
A mode according to the present invention, it is provided that a kind of structure, has:
Process chamber;
Gas supply part, it supplies hard mask to above-mentioned process chamber and forms gas;
Substrate mounting portion, it is placed with the substrate Wn being formed with the n-th batch being eclipsed engraved film;
Heating part, it is enclosed in above-mentioned substrate mounting portion;And
Control portion, its substrate based on m batch processed before above-mentioned n-th batch
The etching information of Wm controls the Temperature Distribution of above-mentioned heating part.
Invention effect
Can the structure of deviation of suppressor electrode width in accordance with the invention it is possible to provide.
Accompanying drawing explanation
Fig. 1 is the explanatory diagram of the forming method of the gate electrode that one embodiment of the present invention is described.
Fig. 2 is the summary construction diagram of the film formation device of the one chip of one embodiment of the present invention.
Fig. 3 is the shower head of the film formation device of the one chip that one embodiment of the present invention is described
Explanatory diagram.
Fig. 4 is the flow chart of the film formation process that one embodiment of the present invention is described.
Fig. 5 is the explanatory diagram of the Etaching device that one embodiment of the present invention is described.
Fig. 6 is the explanatory diagram that explanation implements the substrate of etching work procedure.
Fig. 7 is the explanatory diagram that explanation implements the substrate of etching work procedure.
Description of reference numerals
2000: lining processor
200: wafer (substrate)
201: process space
209: aerofluxus surge chamber
211: substrate mounting surface
222: exhaustor
230: shower head
Detailed description of the invention
The first embodiment > of the < present invention
Hereinafter, about semiconductor making method (the also referred to as substrate of one embodiment of the present invention
Processing method), it is described with reference to the accompanying drawings.
In the present embodiment, as the substrate of process object, such as, making quasiconductor can be enumerated
The semiconductor wafer substrate of device (semiconductor components and devices) is (hreinafter referred to as " wafer ".).
(1) gate electrode formation process
Use Fig. 1 that the gate electrode formation process in present embodiment is described.
(hard mask layer formation process)
(A) (B) that use Fig. 1 illustrates.Described at (A) being formed at Fig. 1
Wafer 200 on Poly-Si film 101 on, by employing the one-tenth of film formation device described later
Membrane process, is formed as described in (B) of figure as the silicon nitride film (SiN of hard mask layer
Film) 102.Poly-Si film 101 is the layer becoming gate electrode afterwards, is also referred to as eclipsed engraved film.
Hard mask layer 102 also has the effect as antireflection film.
Here, explanation forms the reason of hard mask layer.Along with miniaturization in recent years, rear
The resist formation process stated requires the filming of resist.But, due to along with thin film
Changing, the elching resistant of resist deteriorates, so in etching work procedure, resist disappears sometimes.Cause
This, use and use higher firmly the covering of elching resistant on the antireflection film etc. being positioned at resist bottom
The method of film.
(resist film formation process)
(C) that use Fig. 1 illustrates.On hard mask layer 102, resist is used to be coated with
Cloth apparatus and form resist film 103.
(exposure process)
(D) that use Fig. 1 illustrates.Resist film 103 defines etching mask
After 103, with the pattern desired by exposure device exposure.
(etching work procedure)
(E) that use Fig. 1 illustrates.After exposure process, use etching dress described later
Put, carry out dry-etching based on plasma and process and on Poly-Si film 101, form groove.
On groove, in operation later, the dielectric film that embedment is such as made up of silicon nitride film etc..
(resist film/hard mask layer removal step)
(F) that use Fig. 1 illustrates.After etching work procedure, remove and be positioned at Poly-Si
The resist film 103 of the top of film 101, hard mask layer 102.
Multi-disc Poly-Si film 101 is formed as described above on wafer 200.
(2) structure of lining processor (film formation device)
Then, illustrate to be formed the lining processor 2000 of hard mask layer.Lining processor is also
It is referred to as film formation device.The lining processor of present embodiment is configured to as processing object
Substrate process the one chip lining processor of a piece of substrate each time.
Hereinafter, about the structure of the lining processor of present embodiment, say with reference to Fig. 2
Bright.Fig. 2 is the summary construction diagram of the lining processor of the one chip of present embodiment.
(process container)
As in figure 2 it is shown, lining processor 2000 has process container 202.Process container
202 to be configured to such as cross section be circular and flat sealing container.It addition, process container 202
Such as it is made up of metal materials such as aluminum (Al) and rustless steels (SUS).Processing container 202
Inside be formed: process the wafer 200 such as silicon wafer as substrate process space 201 and
By wafer 200 to processing the conveyance space 203 passed through when space 201 transports for wafer 200.
Process container 202 to be made up of upper container 202a and bottom container 202b.At upper container 202a
And it is provided with demarcation strip 204 between bottom container 202b.
Aerofluxus surge chamber 209 it is provided with near the periphery ora terminalis of the inside of upper container 202a.
The substrate carrying-in/carrying-out adjacent with gate valve 205 it is provided with in the side of bottom container 202b
Mouthfuls 206, wafer 200 via substrate carrying-in/carrying-out mouth 206 between not shown carrying room
Mobile.Multiple lift pin 207 it is provided with in the bottom of bottom container 202b.
(substrate mounting portion)
The substrate mounting portion 210 of supporting wafer 200 it is provided with in processing space 201.Substrate carries
Put portion 210 mainly to there is the substrate mounting surface 211 of mounting wafer 200, on surface, there is substrate
The substrate mounting table 212 of mounting surface 211 and by the conduct heating of bag in substrate mounting table 212
The heater 213 in source.In substrate mounting table 212, in the position corresponding with lift pin 207
It is respectively arranged with the through hole 214 through for lift pin 207.
Substrate mounting table 212 is supported by axle 217.The bottom of axle 217 through process container 202,
And it is connected with elevating mechanism 218 in the outside processing container 202.By making elevating mechanism 218
Work and make axle 217 and substrate mounting table 212 lift, it is possible to make to be positioned in substrate mounting surface 211
On wafer 200 lift.It should be noted that the surrounding of the bottom of axle 217 is by corrugated tube
219 cover, and process container 202 inside and are hermetic kept.
Substrate mounting table 212 drops to substrate mounting surface 211 and lining when the conveyance of wafer 200
The position (wafer transfer position) that end carrying-in/carrying-out mouth 206 is relative, in the process of wafer 200
Time, as it is shown in figure 1, wafer 200 rises to process the processing position (wafer in space 201
Processing position).
Specifically, when making substrate mounting table 212 drop to wafer transfer position, lift pin
The upper end of 207 highlights from the upper surface of substrate mounting surface 211, and lift pin 207 props up from below
Hold wafer 200.It addition, when making substrate mounting table 212 rise to wafer-process position, carry
Rising pin 207 to bury from the upper surface of substrate mounting surface 211, substrate mounting surface 211 is propped up from below
Hold wafer 200.It should be noted that owing to lift pin 207 directly contacts with wafer 200,
It is advantageous to formed with materials such as such as quartz, aluminium oxidies.
Heater 213 is can be using the median plane as wafer 200 center with as this median plane
The outer peripheral face of periphery separately carry out the structure of computer heating control.Have and be such as located at substrate
The center of mounting surface 211, the middle section heater 213a of circumferentially shape viewed from above and
The most circumferentially shape and be located at perimeter heater 213a periphery perimeter heating
Device 213b.The median plane of wafer is heated by middle section heater 213a, perimeter
The outer peripheral face of wafer is heated by heater 213b.
Middle section heater 213a, perimeter heater 213b are respectively via heater electricity
Power provides line to be connected with heter temperature control portion 215.Heter temperature control portion 215 passes through
Control the power supply to each heater and control the temperature of the median plane of wafer 200, outer peripheral face.
The temperature meter 216a of the temperature measuring wafer 200 it is surrounded by substrate mounting table 213
With temperature meter 216b.Temperature meter 216a is arranged at the center of substrate mounting table 212
Portion is to measure the temperature near middle section heater 213a.Temperature meter 216b is arranged at
The peripheral part of substrate mounting table 212 is to measure the temperature near the heater 213b of perimeter.
Temperature meter 216a, temperature meter 216b are connected with temperature information acceptance division 216c.With
The temperature that each temperature meter is measured sends to temperature information acceptance division 216c.Temperature information receives
The temperature information of reception is sent by portion 216c to controller 260 described later.Controller 260 base
Heter temperature is controlled in the temperature information received and etching information described later.Additionally, by temperature
Degree measuring device 216a, temperature meter 216b, temperature information acceptance division 216c are as concentrating temperature
Degree test section 216.
(shower head)
It is provided with divides as gas on the top (gas direction of the supply upstream side) processing space 201
Dissipate the shower head 230 of mechanism.Lid 231 in shower head 230 be provided with gas introduction port 231a,
231b.Gas supply system described later is connected at this gas introduction port 231a, 231b.From gas
The gas that body entrance hole 231a, 231b import is fed into the cushion space 232 of shower head 230.
Cushion space 232 has the first cushion space 232a and the second cushion space 232b.The
One cushion space 232a is enclosed in dispersion plate 234.Second cushion space 232b is formed in lid 231
And between dispersion plate 234.
Shower head 230 has dispersion plate 234.Dispersion version 234 make from gas introducing port 231a,
The gas dispersion of 231b supply.The upstream side of this dispersion plate 234 is cushion space 232b, under
Trip side is for processing space 201.Dispersion plate 234 is provided with multiple through hole as described later
234c, through hole 234d.Dispersion plate 234 is configured to relative with substrate mounting surface 211.
(gas supply system)
Gas introducing port 231a on the lid 231 being located at shower head 230 is through with as
The gas supply pipe 243a of one gas supply pipe.Connect at gas introducing port 231b and have as the
The gas supply pipe 242 of two gas supply pipes.Gas supply pipe 243a be enclosed in described later bunch
Penetrate the cushion space 232a of 234 to connect.Gas supply pipe 242 is by the connection of 231b
And connect with cushion space 232b.
Gas supply pipe 244a is connected to gas via remote plasma unit (RPU) 244e
Body supply pipe 242.
Mainly supply from the first gas supply system 243 comprising the first gas supply pipe 243a
First gas, from the second gas comprising the second gas supply pipe 242, gas supply pipe 244a
Feed system 242 mainly supplies the second gas.
(the first gas supply system)
From the beginning of updrift side, the first gas supply pipe 243a is disposed with the first gas
Body supply source 243b, mass flow controller as flow controller (flow-control portion)
(MFC) 243c and the valve 243d as open and close valve.Then, from the first gas supply pipe
First gas via MFC243c, valve 243d, is supplied to surge chamber 232a by 243a.
First gas is one of place's process gases, e.g. contains raw material that is six of Si (silicon) element
Silicon hexachloride (Hexachlorodisilane) (Si2Cl6, it is called for short: HCDS) gas.Need
Illustrate, as the first gas, can be solid, liquid and gas at normal temperatures and pressures
In any one.In the case of the first gas is liquid at normal temperatures and pressures, can be at the first gas
Not shown gasifier is set between supply source 243b and mass flow controller 243c.Here,
It is set to gas illustrate.
Mainly constituted the first gas by the first gas supply pipe 243a, MFC243c, valve 243d
Feed system 243.It should be noted that it is believed that wrap at the first gas supply system 243
Containing the first gas supply source 243b and the first noble gas feed system described later.Additionally, the
One gas supply system 243 supply is as the first gas of one of place's process gases, and therefore it is suitable
In one of treating-gas supply system.
In the downstream of the valve 243d of the first gas supply pipe 243a, connect and have the first indifferent gas
The downstream of body supply pipe 246a.From the beginning of updrift side, at the first noble gas supply pipe
Noble gas supply source 246b it is disposed with, as flow controller (flow control on 246a
Portion processed) mass flow controller (MFC) 246c and as the valve 246d of open and close valve.
Further, pipe 246a is supplied by noble gas via MFC246c, valve from the first noble gas
246d, the first gas supply pipe 243a and be supplied in cushion space 232a.
Noble gas plays a role as the vector gas of the first gas, is preferably used not with first
The gas that gas reacts.Specifically, nitrogen (N can such as be used2).Additionally, remove
N2Beyond gas, it is possible to use such as helium (He), neon (Ne), argon (Ar)
In rare gas.
The mainly it is made up of first noble gas supply pipe 246a, MFC246c and valve 246d
One noble gas feed system.It should be noted that it is also contemplated that supply at the first noble gas
System comprises noble gas supply source 246b, the first gas supply pipe 243a.Additionally, the
One noble gas feed system is it is believed that be contained in the first gas supply system 243.
(the second gas supply system)
It is provided with in the downstream of the gas supply pipe 244a being connected with the second gas supply pipe 242
RPU244e.From the beginning of updrift side, be disposed with in upstream the second gas supply source 244b,
As flow controller (flow-control portion) mass flow controller (MFC) 244c and
Valve 244d as open and close valve.Further, from gas supply pipe 244a by the second gas via
MFC244c, valve 244d, RPU244e, gas supply pipe 242 and be supplied to shower head 230
In.Second gas becomes plasmoid by remote plasma unit 244e, quilt
It is irradiated on wafer 200.
Second gas is one of place's process gases, such as, use ammonia (NH3)。
Main by the second gas supply pipe 242, gas supply pipe 244a, MFC244c, valve 244d
Constitute the second gas supply system 244.It should be noted that it is believed that supply at the second gas
Second gas supply source 244b, RPU244e and the second inertia described later is comprised to system 244
Gas supply system.Additionally, one of process gases at the second gas supply system 244 supply conduct
The second gas, therefore it is equivalent to another of treating-gas supply system.
In the downstream of the valve 244d of gas supply pipe 244a, connect and have the second noble gas to supply
Downstream to pipe 247a.From the beginning of updrift side, supply pipe 247a at the second noble gas
On be disposed with noble gas supply source 247b, as flow controller (flow-control portion)
Mass flow controller (MFC) 247c and as the valve 247d of open and close valve.Further,
From the second noble gas supply pipe 247a by noble gas via MFC247c, valve 247d, gas
Body supply pipe 244a, RPU244e, the second gas supply pipe 242 and be supplied to shower head 230
In.
Noble gas plays a role as vector gas or the diluent gas of the second gas.Concrete and
Speech, such as, can use nitrogen (N2).Additionally, except N2Outside gas, it is possible to use such as
The rare gas such as helium (He), neon (Ne), argon (Ar).
The mainly it is made up of second noble gas supply pipe 247a, MFC247c and valve 247d
Two noble gas feed systems.It should be noted that it is also contemplated that supply at the second noble gas
System comprises noble gas supply source 247b, second gas supply pipe 243a, RPU244e.
Additionally, the second noble gas feed system is it is believed that be contained in the second gas supply system 244.
Mainly constituted gas supply part by the first gas supply system, the second gas supply system.
Furthermore it is possible to think and noble gas feed system, shower head be contained in gas supply part.And
And, it is possible to the first gas and the second gas are generically and collectively referred to as hard mask and form gas.
(gas exhaust system)
The gas extraction system that the atmosphere processing container 202 is discharged is had and is connected with process container 202
Exhaustor 222.Exhaustor 222 is via upper surface or the side being arranged at aerofluxus surge chamber 209
The steam vent 221 of side and be connected with in aerofluxus surge chamber 209.Exhaustor 222 be provided with by with
Space 201 internal control that processes of aerofluxus surge chamber 209 connection is made as the pressure controller of authorized pressure
I.e. APC (Auto Pressure Controller) 223.APC223 has adjustable aperture
Valve body (not shown), adjusts exhaustor 222 according to the instruction from controller 260 described later
Conductance.At exhaustor 222, it is provided with exhaust pump 224 in the downstream of APC223.Aerofluxus
Pump 224 via exhaustor 222 by aerofluxus surge chamber 209 and the process space 201 that communicates therewith
Atmosphere discharge.Additionally, at exhaustor 222, the downstream of APC223 or upstream side,
Or both is provided with not shown valve.Mainly by exhaustor 222, APC223, exhaust pump 224,
And not shown valve constitutes gas exhaust system.
(shower head)
Then, use Fig. 3 that the detailed configuration of shower head 230 is described.
Shower head 230 has the first cushion space 232a and the second cushion space 232b, each
The atmosphere of cushion space be isolated.Specifically, the first cushion space 232a is enclosed in point
Fall apart 234, using the upper wall 234a of the part as dispersion plate 234 as border, with buffering
Space 232b is separately.
Dispersion plate 234 has and processes the lower wall 234b that space 201 contacts.At lower wall 234b
On be provided with the multiple through hole 234c connected with the first cushion space 232a.And, arrange
There are the multiple through hole 234d connected with the second cushion space 232b.Through hole 234c is with through
Hole 234d is radially alternately arranged, and the gas being configured to supply from respective through hole is by all
Supply to wafer 200 evenly.It addition, through hole 234d be enclosed in by upper wall 234a and under
The post 234e that wall 234b couples together.
First gas supply pipe 243a via gas introducing port 231a, cushion space 232b with
Upper wall 234a connects.By connecting, the first gas supply pipe 243a and the first cushion space 232a
Connection.
First cushion space 232a is to have the post 234e of bag in through hole 234d, and edge
The space of radial communication.From the gas of the first gas supply pipe 243a supply at the first buffering sky
Between 232a disperseed, via multiple dispersion hole 234c supply to process space 201.
Second cushion space 232b is formed between upper wall 234a and top board 231.At upper wall 234a
Being provided with through hole 234d, gas supply pipe 242 connects with through hole 234d.Supply from gas
To the gas of pipe 242 supply via through hole 234d supply to processing space 201.
(controller)
Film formation device 2000 has the controller of the action in each portion controlling film formation device 2000
260.Controller 260 at least has operational part 261 and storage part 262.Controller 260 is with upper
State each composition to connect, come from storage part 262 according to the instruction of host controller and/or user
Recall program and/or processing procedure, and the action respectively constituted according to its content-control.Specifically, control
Device 260 processed control gate valve 205, elevating mechanism 218, heater 213, MFC243c, 244c,
246c, 247c, valve 243d, 244d, 246d, 247d, APC223, exhaust pump 224 etc.
Action.
Controller 260 is connected with the epigyny device in factory.Controller 260 is set to be able to receive that
At the substrate with etching work procedure in the Etaching device of the device different from this film formation device
The information etc. that reason is relevant.Controller 260 can not only the independence of information based on this film formation device
(standalone) control, and can be based on the letter of the device used in other operations
Breath controls the action of each composition.
It should be noted that controller 260 may be constructed as special-purpose computer, it is also possible to structure
Become as general purpose computer.Such as, prepare to store the external memory (example of said procedure
Such as disks such as tape, floppy disk, hard disks;The CDs such as CD, DVD;The photomagneto disks such as MO;USB
The semiconductor memory such as memorizer, storage card), by use this external memory 263 to
General computer installation procedure and the controller 260 of present embodiment can be constituted.
Additionally, for being not limited to via external memory to the means of computer supply program
263 situations about providing.Such as can also use the means of communication such as the Internet or special circuit, no
Program is provided via external memory 263 ground.It should be noted that it is storage part 262, outer
Portion's storage device 263 is configured to computer-readable recording medium.Hereinafter, also they are all together
Ground referred to as records medium.It should be noted that in this manual employ record medium this
In the case of the wording of sample, the most only comprise storage part 262, the most only comprise outside storage dress
Put 263, or comprise above-mentioned both.
(3) film formation process
It follows that use Fig. 4 to illustrate about the hard mask layer employing film formation device 2000
Film formation process ((B) of Fig. 1) detailed.Exist as the polysilicon film film forming being eclipsed engraved film
As on the wafer of object.Additionally, in the following description, film formation device 2000 is constituted
The action of each several part is controlled by controller 260.
At this about using HCDS gas as the first gas (process gases at first), use
NH3As the second gas (process gases at second), wafer 200 contains film shape as silicon
The example becoming SiN (silicon nitride) film illustrates.Additionally, SiN film is formed as hard mask layer
102。
(substrate moves into mounting operation: S102)
In film formation device 2000, first, substrate mounting table 212 is made to drop to wafer 200
Conveyance position, thus make lift pin 207 run through the through hole 214 of substrate mounting table 212.
As a result, lift pin 207 becomes and only highlights specified altitude amount than substrate mounting table 212 surface
State.Then, open gate valve 205 and make conveyance space 203 with transferring chamber (not shown) even
Logical.Then, wafer transfer machine (not shown) is used to be moved into by wafer 200 from this transferring chamber
Send space 203, by wafer 200 transfer to lift pin 207.Thus, wafer 200 is with water
Flat posture is supported in the lift pin 207 highlighted from the surface of substrate mounting table 212.
After being moved into by wafer 200 in process container 202, make wafer transfer machine to processing container
Keeping out of the way outside 202, closing gate valve 205 is airtight in processing container 202.Thereafter, by making
Substrate mounting table 212 rises, and wafer 200 is placed in the substrate being located at substrate mounting table 212
In mounting surface 211, and then make substrate mounting table 212 increase, thus make wafer 200 rise to
Processing position in aforesaid process space 201.
After wafer 200 is moved to transport space 203, when rising to process in space 201
Processing position time, open the valve in gas exhaust system, make aerofluxus surge chamber 209 with
Connect between APC223, and make to connect between APC223 with exhaust pump 224.APC223
Aerofluxus surge chamber 209 based on exhaust pump 224 is controlled by adjusting the conductance of exhaustor 222
Extraction flow, the process space 201 connected with aerofluxus surge chamber 209 is maintained regulation pressure
Power.It should be noted that the valve of other gas extraction system remains off state.Additionally, by first
When the valve of gas exhaust system cuts out, it is for closing shape at the valve of the upstream side that will be located in TMP
After state, being closed mode by will be located in the valve in the downstream of TMP, stably maintaining TMP
Action.
(silicon operation: S104)
To middle section heater 213a, the outside area of the inside being embedded to substrate mounting table 212
Territory heater 213b supplies electric power, controls as making the surface of wafer 200 become the temperature of regulation
Distribution.Now, middle section heater 213a, the temperature of perimeter heater 213b are led to
Cross based on the temperature information detected by temperature detecting part 216a, temperature detecting part 216b and erosion
The film information etc. after operation (E) of carving controls to be adjusted the energising situation of heater 213
Whole.Control middle section heater 213a, perimeter heater 213b and make crystalline substance now
The temperature of sheet 200 such as becomes from 250 DEG C to 700 DEG C, preferably from 300 DEG C to 650 DEG C, more
Preferably in the range of 350 DEG C to 600 DEG C.
So, the surface temperature controlling wafer 200 becomes in the range of regulation.It addition, at this
Substrate is moved into mounting operation (S102) and silicon operation (S104) as separate work
Sequence illustrates, it is also possible to be not limited to this, carries out the two operation abreast.
(film formation process: S106)
After silicon operation (S104), carry out locating process gases supply step (S106).
In place's process gases supply step (S106), first, it is set to open also by valve 243d
Control MFC243c and supply the HCDS gas of the first gas as regulation flow.With this
Parallel, valve 244d is set to the second gas opening and controlling MFC243c to supply regulation flow
Body.Now, via the RPU244e started in advance, therefore as the second gas ammonia with etc.
Gas ions state is supplied to process space 201.
Specifically, when supplying process gases (HCDS) at first, open valve 243d, and
Adjust mass flow controller 243c so that the flow of the first gas becomes regulation flow, thus
The supply of the beginning the first gas in processing space 201.The supply flow rate of the first gas is such as
It is 100~500sccm.First gas is disperseed by shower head 230 and is uniformly supplied to process
On wafer 200 in space 201.Now, process gases is preferably used main by heat energy at first
The gas of impact domination.Owing to mainly being arranged by heat energy, so based on Temperature Distribution control described later
The film thickness monitoring of system becomes easy.
Now, open the valve 246d of the first noble gas feed system, supply from the first noble gas
Noble gas (N is supplied to pipe 246a2Gas).The supply flow rate of noble gas for example, 500~
5000sccm.It should be noted that can be from the 3rd gas supply of purging gas supply system
Pipe 245a flows through noble gas.
Process gases (NH at supply second3Gas) time, open valve 244d, via remotely etc.
Gas ions unit 244e, shower head 230, the beginning the second gas in processing space 201
Supply.Now, MFC244c is adjusted so that the flow of the second gas becomes regulation flow.The
The supply flow rate of two gases for example, 1000~10000sccm.
Second gas of plasmoid is disperseed by shower head 230, and is supplied uniformly across
To the wafer 200 processed in space 201, react with the HCDS on wafer 200,
Wafer 200 generates the SiN film as hard mask layer.
Now, open the valve 247d of the second noble gas feed system, supply from the second noble gas
Noble gas (N is supplied to pipe 247a2Gas).The supply flow rate of noble gas for example, 500~
5000sccm。
The treatment temperature processed in space 201 now, processing pressure are controlled in the first gas
Carry out reacting with the second gas and the scope of SiN film can be formed.In process chamber 201 now
Pressure be set to such as 1~13300Pa, the pressure in the range of preferably 20~1330Pa.
(substrate takes out of operation: S108)
After being eclipsed and defining as the SiN film of hard mask layer on engraved film i.e. polysilicon film, logical
Cross the order contrary with moving into mounting operation 102 and take out of wafer 200.After taking out of, will be formed with
The untreated wafer 200 being eclipsed engraved film is moved to process chamber, carries out identical process.
(process sheet number and judge operation: S110)
After the film formation process being made up of above each operation, it is determined that in place's process gases supply step
(S106) whether the wafer 200 processed in has reached regulation sheet number (S110).
If the wafer processed in place's process gases supply step (S106) 200 not up to regulation
Sheet number, thereafter, then start the process to standby new wafer 200, therefore move to substrate
Move into mounting operation (S102).Additionally, the wafer 200 of regulation sheet number is being implemented process
The substrate processing of 1 batch is terminated in the case of gas supply step (S106).
As illustrate in aforementioned gate electrode formation process, define in film formation process and firmly cover
After film layer, via resist film formation process, exposure process, implement etching work with Etaching device
Sequence.
But, after the width of the polysilicon film confirming column after etching work procedure terminates, find
The width of the gate electrode being made up of Poly-Si film in substrate surface is outside the center of wafer is with it
Week is inconsistent.The result studied with keen determination based on inventor is to learn in etching work procedure, brilliant
The rate of etch at the center of sheet and one of the rate of etch of its periphery not reason being both deviation.
The reason that following description is different at the center of wafer and the rate of etch of its periphery.
First, general Etaching device is described.Etching work procedure is implemented based on plasma
The situation of dry-etching, uses Etaching device 5000 as such as Fig. 5.Etaching device 5000
Having parallel plate-type plasma electrode in container 501, the etching gas being supplied to is thus
Become plasmoid.In Figure 5, the bottom electricity of the mounting portion held concurrently as mounting wafer 200
Pole 502 is configured to parallel flat electricity with the upper electrode 503 of the shower head held concurrently as supply gas
Pole.Electrode is connected to power supply.
In Figure 5,504 is the cylindric support of supporting lower electrode 501, and 506 are
The exhaustor of the atmosphere in amount discharge container 501.Arrange at exhaustor 506 and be made up of valve etc.
Exhaust control portion 507 control capacity.Pump is made to be connected to the front end of exhaustor 506, will
Atmosphere in container 501 is discharged.It is formed with stream between lower electrode 502 and container 501
508.Stream 508 is configured to circle-shaped in the case of viewed from above.
Upper electrode 503 is provided with gas flow path in inside, and in the face relative with wafer 200
It is provided with dispersion hole.Gas flow path connects gas supply pipe 509.Gas supply pipe is arranged
There is the gas supply control part 510 of valve and the mass flow controller etc. that control gas supply.Gas
Body supply control part 510 controls the flow etc. of the gas from not shown etch gas source supply.
Gas 511 indicated by an arrow via upper electrode 503 be supplied to upper electrode 503 with under
Space between portion's electrode 502.The etching gas being supplied to passes through upper electrode 503, bottom
Electrode 502 becomes plasmoid, is etched by the film on wafer 200.
Gas used in etching is discharged from exhaustor 506 via stream 508.Continuing
When being etched, incited somebody to action with coordinating of exhaust control portion 507 by gas supply control part 510
Process the pressure in container 501 to be adjusted to desired pressure and be etched processing.
In the case of as with Etaching device 5000, monolithic devices processes substrate, although adjust
Pressure and gas flow, capacity etc. in whole process container 501 and be adjusted to the process of regulation
Condition, but ensuing problem can be caused.
First problem is described.In the case of Etaching device 5000, due to constructional problem,
Etching gas is discharged from exhaustor 506 via the stream 508 as wafer 200 periphery.Example
As carried at the volume increasing the etching gas collided with wafer 200 in order to shorten etching period
In the case of high etching efficiency, rise the pressure in high disposal container 501, or improve gas supply
Flow velocity during/aerofluxus and make gas easily spread.Such situation, with center wafer face 200a
On compare gas to be fed on wafer outer peripheral face 200b at a high speed.Therefore, wafer outer peripheral face
The quantity delivered of etching gas more than center wafer face.That is, the plasma of wafer outer peripheral face is close
Spend higher than the plasma density in center wafer face.Due to such situation, it is believed that wafer
The rate of etch of outer peripheral face 200b is higher than center wafer face 200a.
Second Problem is described.Such as improving plasma density to shorten etching period
And in the case of improving etching efficiency, it is considered to increase the power supply amount to electrode.But, by
In magnetic field concentration space (the i.e. center wafer face 200a in the lower section of upper electrode 503 central part
Superjacent air space), so the plasma density in the space of the lower section of upper electrode 503 central part
Become than the space of the lower section of the periphery of upper electrode 503 that (i.e. wafer outer peripheral face 200b's is upper
Side space) plasma density high.Owing to becoming such situation, it is believed that in wafer
The rate of etch of heart face 200a is higher than wafer outer peripheral face 200b.
It follows that about the problem of the situation different from its periphery rate of etch at the center of wafer
Point, uses Fig. 6, Fig. 7 to illustrate.
Fig. 6 is that the rate of etch ratio that the wafer outer peripheral face 200b as first problem is described is in wafer
The figure of the situation that heart face 200a is high.At this, rate of etch of center wafer face 200a is set to Ra1,
The rate of etch of wafer outer peripheral face is set to Rb1.And, will be formed in center wafer face 200a
On poly-Si film be referred to as 101a, hard mask is referred to as 102a, resist film is referred to as 103a.
The poly-Si film that will be formed on wafer outer peripheral face 200b is referred to as 101b, is referred to as by hard mask
102b, is referred to as 103b by resist film.
Etch with central side in the way of not remaining etch residue on heart face 200a in the wafer
In the case of the etching period of rate Ra1 matches and is etched, due to outer circumferential side rate of etch
The rate of etch of Rb1 is higher, thus on wafer outer peripheral face 200b the quantity delivered of etching gas with
It is many that central side compares change.
As described above, along with miniaturization in recent years, resist film is by filming, when cruelly
When being exposed under a large amount of etching gas, resist film also can be etched.It is additionally, since resist film
Itself is etched, so being formed at the upper exposed of the hard mask below resist film in etching
Under gas.Although hard mask has a certain degree of elching resistant, but is exposed to etch in a large number gas
Can be etched in the case of body.As a result of which it is, a part for the width of hard mask 102b
Can be etched and desired width can not be maintained.Therefore, in the lower section of hard mask 102b,
The Poly-Si film 101b being made up of many columns is etched, and it is desired that respective post becomes ratio
Width is thin.And, it is exposed in etching gas for a long time, thus on Poly-Si film 101b
Cause undercutting (undercut), so desired width can not be maintained.
As described above, wafer outer peripheral face 200b is formed with ratio center wafer face
The Poly-Si film 101b thin for Poly-Si film 101a of 200a.Therefore, in wafer 200
There is deviation with the width of gate electrode on outer peripheral face in heart face.
Fig. 7 be the rate of etch that the center wafer face 200a as Second Problem is described than wafer outside
The figure of the situation that side face 200b is high.At this using the rate of etch of center wafer face 200a as Ra2,
Using the rate of etch of wafer outer peripheral face as Rb2.And, will be formed in center wafer face 200a
On poly-Si film be referred to as 101a, hard mask be referred to as 102a, resist film is referred to as 103a.
Will be formed in the poly-Si film on wafer outer peripheral face 200b to be referred to as 101b, be referred to as by hard mask
102b, resist film is referred to as 103b.
In the way of not remaining etch residue on the 200b of wafer periphery, etch with outer circumferential side
Rate Rb2 matches in the case of being etched, due to central side rate of etch Ra2 rate of etch relatively
Height, thus in the wafer on the 200a of heart face compared with outer circumferential side the supply quantitative change of etching gas many.
As described above, along with miniaturization in recent years, resist film is by filming, when cruelly
When being exposed under a large amount of etching gas, resist film also can be etched.It is additionally, since resist film
Himself is etched, so the top being formed at the hard mask below resist film is exposed on erosion
Carve under gas.Although hard mask has a certain degree of etching gas patience, but is being exposed to greatly
Situation under amount etching gas can be etched.As its result, the width side of hard mask 102a
To a part can be etched and desired width can not be maintained.Therefore, it is formed at hard mask
Poly-Si film 101a below 102a is also shaved, and becomes thinner than desired width.And,
Under the etching gas higher owing to being exposed to plasma density, so at Poly-Si film 101a
On cause undercutting, each post can not maintain desired width.
Owing to becoming such situation, so as recorded in Fig. 7, heart face 200a in the wafer
On be formed with the Poly-Si film of the column thinner than the Poly-Si film 101b of wafer outer peripheral face 200b
101a.Therefore, the median plane at wafer 200 is inclined in the width appearance of gate electrode with on outer peripheral face
Difference.
As described above, in the case of carrying out dry-etching, it is difficult to be unified in wafer face
The width of interior gate electrode.
The most in the present embodiment, at the crystalline substance by the new batch (the referred to as n-th batch) processed
When the film formation process of sheet Wn forms hard mask, complete process batch according to what etching work procedure terminated
The etching information of the wafer of (referred to as m batch), controls film thickness distribution so that the film of hard mask
Thick different from outer peripheral face at the median plane of wafer 200.At this, so-called etching information refers to wafer
It is eclipsed engraved film (Poly-Si film 101) after rate of etch in the median plane of 200, outer peripheral face, etching
The width of post and its be distributed.About the rate of etch in the median plane of wafer 200, outer peripheral face,
Observe the etching result of such as m batch and calculate.Width about the post being eclipsed engraved film
Degree, after etch processes, uses existing determinator to be measured.
Hereinafter, different from outer peripheral face at the median plane of wafer 200 about the thickness making hard mask
Concrete method illustrates with the reason making thickness different.For the n-th batch, by m
The wafer of batch is referred to as " other substrates " or " substrate Wm ".On the other hand, Jiang Xinchu
The batch wafers of reason is referred to as " substrate " or " substrate Wn ".
Complete the etching information of other substrates (substrate Wm) of the m batch of etching work procedure
It is the information wide for width ratio Poly-Si film 101b representing Poly-Si film 101a as shown in Figure 6
Situation, or represent the rate of etch etching than center wafer face 200a of substrate periphery 200b
In the case of the information that rate is high, in the process of the n-th batch, control film formation device 200 so that
The hard mask 102b of wafer outer peripheral face 200b is thicker than hard mask 102a.
As concrete control, in the temperature of the perimeter heater 213b of film formation device 2000
Process gases supply step at enforcement under the state that the degree temperature than middle section heater 213a is high
(S106).It is preferred that the temperature of heater 231b when making process Wn is than processing Wm
Time temperature high.It addition, the temperature maintenance of heater 231a when processing Wn processes Wm
Time temperature.
When chip temperature is higher, the reaction of gas is promoted, and the rate of film build of hard mask 102 becomes
High.Therefore the thickness of hard mask 102b becomes thicker than hard mask 102a.Now, hard mask 101a,
The thickness of hard mask 101b is set at least not expose Poly-Si film in the etching period of regulation
The thickness of 101 degree.
Preferably, the thickness of hard mask 102a is set to Ha1, by the thickness of hard mask 102b
Degree is set to Hb1, when etch processes time is set to t, preferably becomes " Ha1 > Ra1 × t ",
The relation of " Hb1 > Rb1 × t ".By being set to such relation, even if center wafer face
Rate of etch is higher than outer peripheral face, it is also possible to be more reliably prevented from over etching and the undercutting of hard mask.
Therefore, in wafer face, it is possible to form uniform gate electrode width.
It addition, the erosion of other substrates (substrate Wm) of the m batch terminated at etching work procedure
Quarter, information was to represent the width ratio Poly-Si film 101a width of Poly-Si film 101b as shown in Figure 7
The situation of information, or represent that the rate of etch of substrate outer peripheral face is higher than the rate of etch of substrate periphery
The situation of information, in the process of the n-th batch, by the hard mask of center wafer face 200a
102a controls thicker than hard mask 102b.
As concrete control, make the middle section heater 213a of film formation device 2000
Process gases supply work at enforcement under the state that the temperature temperature than perimeter heater 213b is high
Sequence (S106), controls Temperature Distribution so that film thickness distribution is in the range of regulation.It is preferred that
The temperature maintenance of perimeter 231b when processing Wn processes temperature during Wm.It addition,
The temperature of middle section heater 231a when processing Wn is set to than temperature when processing Wm
High.
As described above, when chip temperature is higher, the reaction of gas is promoted, hard mask 102
Rate of film build uprise.Therefore the thickness of hard mask 102a becomes thicker than hard mask 102b.Now,
Hard mask 101a, the thickness of hard mask 101b are set at least not reveal in the etching period of regulation
Go out the thickness of the degree of Poly-Si film 101.
Preferably, the thickness of hard mask 102a is set to Ha2, by the thickness of hard mask 102b
Degree is set to H2, when etch processes time is set to t, preferably becomes " Ha2 > Ra2 × t ",
The relation of " Hb2 > Rb2 × t ".By being set to such relation, even if center wafer face
Rate of etch is higher than periphery, it is also possible to be more reliably prevented from over etching and the undercutting of hard mask.Cause
This, in wafer face, it is possible to be set to uniform gate electrode width.
Like this, according to the present invention, even if in etching work in batch before (m batch)
There is deviation in the width of the Poly-Si film after sequence, due to batch (the n-th batch) later
In etching information based on m batch and adjust the thickness of hard mask, it is possible to by Poly-Si
The width of film converges in desired scope.
It addition, in above embodiment, be divided into the median plane of wafer 200, outer peripheral face to carry out
Explanation, it is also possible to be not limited to this, to radially in the Region control wafer temperature of more sectionalization
Degree.For example, it is also possible to the these three district such as be divided between substrate center, periphery, center and periphery
Territory.
It addition, in this as hard mask, silicon nitride film is illustrated as an example, it is possible to
To be not limited to this, for such as silicon nitride film.
It addition, as comprising the gas of silicon, it is preferably used in the explanation of the present embodiment and uses
The main gas being affected domination by heat energy as HCDS.Owing to mainly being arranged by heat energy, institute
It is easy with the film thickness monitoring controlled based on Temperature Distribution.
It addition, as comprising the gas of silicon, in addition to HCDS, it is possible to use DCS (two
Chlorosilane), 4DMAS (four (dimethylamino) silane, the Si (N of amino silicone alkanes
(CH3)2)4), 3DMAS (three (dimethylamino) silane, Si (N (CH3)2)3H),
2DEAS (two (lignocaine) silane, Si (N (C2H5)2)2H2), BTBAS (two (uncles
Butylamino) silane, SiH2(NH(C4H9))2) etc. Organic Ingredients.Alternatively, it is also possible to
Use TCS (tetrachloro silicane, SiCl4)、SiH4(monosilane), Si2H6(Disilicoethane) etc..
It addition, as nitrogenous gas, except NH3Beyond gas, it is also possible to use N2Gas,
N2H4Gas or N3H8Gas etc..
It addition, the substrate processing commercialization being used as m batch illustrates, it is also possible to no
It is defined in goods and uses virtual substrate etc..
It addition, form the side of film by making two kinds of gases react on substrate in the present embodiment
Method is illustrated as an example, but is not limited thereto, if it is possible to film forming, it is possible to so that
With gas more than such as a kind of gas, or 3 kinds.
And, in the way of in the present embodiment two kinds of gases are concurrently present in process space
Supply gas but it also may be not limited thereto, the most alternately to processing space supply gas.
Preferred mode > of the < present invention
Hereinafter, the preferred mode about the present invention carries out remarks.
< remarks 1 >
A mode according to the present invention, it is provided that a kind of lining processor, has:
Process chamber;
Gas supply part, it supplies hard mask to above-mentioned process chamber and forms gas;
Substrate mounting portion, it is placed with the substrate Wn being formed with the n-th batch being eclipsed engraved film;
Heating part, it is enclosed in above-mentioned substrate mounting portion;And
Control portion, its substrate Wm based on m batch processed before above-mentioned n-th batch
Etching information control the Temperature Distribution of above-mentioned heating part.
< remarks 2 >
Other modes according to the present invention, it is provided that the lining processor that remarks 1 is recorded,
The rate of etch of the median plane that etching information is the center as substrate of above-mentioned substrate Wm
Information and the rate of etch information of outer peripheral face of the periphery as above-mentioned median plane, or above-mentioned median plane
Information with the width being eclipsed engraved film of above-mentioned outer peripheral face.
< remarks 3 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 2 is recorded,
The etching information of above-mentioned substrate Wm is the rate of etch representing above-mentioned outer peripheral face than in above-mentioned
In the case of the information that the rate of etch in heart face is high, said temperature distributed controll is above-mentioned for being formed at
The thickness of the above-mentioned median plane of Film Thickness Ratio of the above-mentioned outer peripheral face of the hard mask layer of substrate Wn is thick.
< remarks 4 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 2 is recorded,
Above-mentioned heating part have heat above-mentioned median plane middle section heater and heating above-mentioned outside
The perimeter heater of side face,
When controlling said temperature distribution, the temperature of said external zone heater is controlled to obtain ratio
The temperature of middle section heater is high.
< remarks 5 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 4 is recorded,
Control said temperature distribution time, by formed above-mentioned substrate Wn hard mask layer time upper
The temperature stating perimeter heater controls than forming hard mask layer on above-mentioned substrate Wm
Time temperature high.
< remarks 6 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 5 is recorded,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled as dimension
Hold temperature when forming hard mask layer on above-mentioned substrate Wm.
< remarks 7 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 2 is recorded,
It is to represent above-mentioned outer peripheral face is eclipsed engraved film in the etching information of above-mentioned substrate Wm
In the case of the information of the narrow width being eclipsed engraved film in the above-mentioned median plane of width ratio, control above-mentioned
Temperature Distribution is so that being formed at the Film Thickness Ratio in substrate periphery of the hard mask layer of above-mentioned substrate Wn
Thick at the thickness of substrate outer peripheral face.
< remarks 8 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 7 is recorded,
Above-mentioned heating part has heats the middle section heater of above-mentioned median plane and heats above-mentioned
The perimeter heater of outer peripheral face,
When controlling said temperature distribution, the temperature of said external zone heater is controlled to obtain ratio
The temperature of above-mentioned middle section heater is high.
< remarks 9 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 8 is recorded,
When controlling said temperature and being distributed, said external zone heater temperature is controlled than existing
Temperature when forming hard mask layer on above-mentioned substrate Wm is high.
< remarks 10 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 9 is recorded,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled as dimension
Hold temperature when forming hard mask layer on above-mentioned substrate Wm.
< remarks 11 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 2 is recorded,
Etching information at above-mentioned substrate Wm is the rate of etch ratio represented in above-mentioned outer peripheral face
In the case of the information that rate of etch in above-mentioned median plane is little, control said temperature distribution so that shape
Become the Film Thickness Ratio at above-mentioned median plane of hard mask layer of above-mentioned substrate Wn at above-mentioned outer peripheral face
Thickness thick.
< remarks 12 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 11 is recorded,
Above-mentioned heating part has heats the middle section heater of above-mentioned median plane and heats above-mentioned
The perimeter heater of outer peripheral face,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled to obtain ratio
The temperature of perimeter heater is high.
< remarks 13 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 12 is recorded,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled to obtain ratio
Temperature when forming hard mask layer on above-mentioned substrate Wm is high.
< remarks 14 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 13 is recorded,
When controlling said temperature distribution, the temperature of said external zone heater is controlled as dimension
Hold temperature when forming hard mask layer on above-mentioned substrate Wm.
< remarks 15 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 2 is recorded,
The etching information of above-mentioned substrate Wm is to represent to be eclipsed engraved film in above-mentioned outer peripheral face
In the case of the information that the width being eclipsed engraved film in the above-mentioned median plane of width ratio is wide, by above-mentioned temperature
Degree distributed controll is the thickness at above-mentioned median plane of the hard mask layer being formed at above-mentioned substrate Wn
Thicker than the thickness at above-mentioned outer peripheral face.
< remarks 16 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 15 is recorded,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled to obtain ratio
The temperature of said external zone heater is high.
< remarks 17 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 16 is recorded,
When controlling said temperature distribution, the temperature of above-mentioned middle section heater is controlled to obtain ratio
Temperature when forming hard mask layer on above-mentioned substrate Wm is high.
< remarks 18 >
Other modes another according to the present invention, it is provided that the lining processor that remarks 17 is recorded,
When controlling said temperature distribution, the temperature of said external zone heater is controlled as dimension
Hold temperature when forming hard mask layer on above-mentioned substrate Wm.
< remarks 19 >
Other modes another according to the present invention, it is provided that any one note within remarks 1~18
The lining processor carried,
Above-mentioned hard mask layer is silicon nitride film.
< remarks 20 >
Other modes another according to the present invention, it is provided that any one note within remarks 1~19
The lining processor carried,
The above-mentioned engraved film that is eclipsed is gate electrode layer.
< remarks 21 >
Other modes another according to the present invention, it is provided that the manufacture method of a kind of semiconductor device,
Have:
Will be formed with being eclipsed the substrate Wn of the n-th batch of engraved film to be placed in and be enclosed in process chamber
Operation in substrate mounting portion;
The etching letter of the substrate Wm of m batch based on the pre-treatment in above-mentioned n-th batch
Breath controls the operation of Temperature Distribution in the face of above-mentioned substrate Wn;And
Above-mentioned process chamber is supplied hard mask and forms the operation of gas.
< remarks 22 >
Other modes another according to the present invention, it is provided that a kind of program making computer perform, tool
Have:
Will be formed with being eclipsed the substrate Wn of the n-th batch of engraved film to be placed in and be enclosed in process chamber
Operation in substrate mounting portion;
The etching of substrate Wm based on m batch processed before above-mentioned n-th batch
Information controls the operation of Temperature Distribution in the face of above-mentioned substrate Wn;And
Above-mentioned process chamber is supplied hard mask and forms the operation of gas.
< remarks 23 >
Other modes another according to the present invention, it is provided that the storage that a kind of computer can read is situated between
Matter, is stored in following operation in the program making computer perform,
Will be formed with being eclipsed the substrate Wn of the n-th batch of engraved film to be placed in and be enclosed in process chamber
Operation in substrate mounting portion;
The etching of substrate Wm based on m batch processed before above-mentioned n-th batch
Information controls the operation of Temperature Distribution in the face of above-mentioned substrate Wn;And
Above-mentioned process chamber is supplied hard mask and forms the operation of gas.
Claims (19)
1. a lining processor, has:
Process chamber;
Gas supply part, it supplies hard mask to described process chamber and forms gas;
Substrate mounting portion, it is placed with the substrate Wn being formed with the n-th batch being eclipsed engraved film;
Heating part, it is enclosed in described substrate mounting portion;And
Control portion, its substrate Wm based on m batch processed before described n-th batch
Etching information control the Temperature Distribution of described heating part.
Lining processor the most according to claim 1, it is characterised in that
The median plane that etching information is the center as substrate of described substrate Wm and as described
In the rate of etch information of the outer peripheral face of the periphery of median plane, or described median plane and described outer peripheral face
The information of the width being eclipsed engraved film.
Lining processor the most according to claim 1, it is characterised in that
It is the rate of etch representing described outer peripheral face than in described in the etching information of described substrate Wm
In the case of the information that the rate of etch in heart face is high, described Temperature Distribution is controlled for described in being formed at
The Film Thickness Ratio at described outer peripheral face of the hard mask layer of substrate Wn is at the thickness of described median plane
Thick.
Lining processor the most according to claim 3, it is characterised in that
Described heating part has described in middle section heater and the heating heating described median plane
The perimeter heater of outer peripheral face,
When controlling described Temperature Distribution, the temperature of described perimeter heater is controlled to obtain ratio
The temperature of middle section heater is high.
Lining processor the most according to claim 4, it is characterised in that
Control described Temperature Distribution time, by formed described substrate Wn hard mask layer time institute
The temperature stating perimeter heater controls than when forming hard mask layer on described substrate Wm
Temperature high.
Lining processor the most according to claim 1, it is characterised in that
It is to represent described outer peripheral face is eclipsed engraved film in the etching information of described substrate Wm
In the case of the information of the narrow width being eclipsed engraved film in median plane described in width ratio, control described
Temperature Distribution is so that being formed at the Film Thickness Ratio lining of the substrate periphery of the hard mask layer of described substrate Wn
The thickness of end outer peripheral face is thick.
Lining processor the most according to claim 6, it is characterised in that
Described heating part has described in middle section heater and the heating heating described median plane
The perimeter heater of outer peripheral face,
When controlling described Temperature Distribution, the temperature of described perimeter heater is controlled to obtain ratio
The temperature of described middle section heater is high.
Lining processor the most according to claim 7, it is characterised in that
When the described Temperature Distribution of control, described perimeter heter temperature is controlled than existing
Temperature when forming hard mask layer on described substrate Wm is high.
Lining processor the most according to claim 1, it is characterised in that
Etching information at described substrate Wm is the rate of etch ratio represented in described outer peripheral face
In the case of the information that rate of etch in described median plane is little, control described Temperature Distribution so that shape
The Film Thickness Ratio at described median plane of the hard mask layer of substrate Wn described in Cheng Yu is at described outer peripheral face
Thickness thick.
Lining processor the most according to claim 9, it is characterised in that
Described heating part has described in middle section heater and the heating heating described median plane
The perimeter heater of outer peripheral face,
When controlling described Temperature Distribution, the temperature of described middle section heater is controlled to obtain ratio
The temperature of perimeter heater is high.
11. lining processors according to claim 10, it is characterised in that
When controlling described Temperature Distribution, the temperature of described middle section heater is controlled to obtain ratio
Temperature when forming hard mask layer on described substrate Wm is high.
12. lining processors according to claim 1, it is characterised in that
The etching information of described substrate Wm is to represent to be eclipsed engraved film in described outer peripheral face
In the case of the information that width in median plane described in width ratio is wide, by said temperature distributed controll
For being formed at the Film Thickness Ratio at above-mentioned median plane of the hard mask layer of above-mentioned substrate Wn outside above-mentioned
The thickness of side face is thick.
13. lining processors according to claim 12, it is characterised in that
When controlling described Temperature Distribution, the temperature of described middle section heater is controlled to obtain ratio
The temperature of described perimeter heater is high.
14. lining processors according to claim 13, it is characterised in that
When controlling described Temperature Distribution, the temperature of described middle section heater is controlled to obtain ratio
Temperature when forming hard mask layer on described substrate Wm is high.
15. lining processors according to claim 14, it is characterised in that
When controlling described Temperature Distribution, the temperature of described perimeter heater is controlled as dimension
Hold temperature when forming hard mask layer on described substrate Wm.
16. lining processors according to claim 15, it is characterised in that
When controlling described Temperature Distribution, the temperature of described perimeter heater is controlled as dimension
Hold temperature when forming hard mask layer on described substrate Wm.
17. lining processors according to claim 2, it is characterised in that
Described hard mask layer is silicon nitride film.
18. lining processors according to claim 2, it is characterised in that
The described engraved film that is eclipsed is gate electrode layer.
The manufacture method of 19. 1 kinds of semiconductor device, has:
Will be formed with being eclipsed the substrate Wn of the n-th batch of engraved film to be placed in and be enclosed in process chamber
Operation in substrate mounting portion;
The etching of substrate Wm based on m batch processed before described n-th batch
Information controls the operation of Temperature Distribution in the face of described substrate Wn;And
Described process chamber is supplied hard mask and forms the operation of gas.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109216227A (en) * | 2017-06-30 | 2019-01-15 | 无尽电子有限公司 | Chip etching device and its application method |
CN111074242A (en) * | 2018-10-19 | 2020-04-28 | 长鑫存储技术有限公司 | Adjusting method of heating device, heating device and chemical vapor deposition equipment |
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JP6419762B2 (en) * | 2016-09-06 | 2018-11-07 | 株式会社Kokusai Electric | Semiconductor device manufacturing method, substrate processing apparatus, and program |
JP6549074B2 (en) * | 2016-09-28 | 2019-07-24 | 株式会社Kokusai Electric | Semiconductor device manufacturing method, substrate processing apparatus and program |
JP7351865B2 (en) * | 2021-02-15 | 2023-09-27 | 株式会社Kokusai Electric | Substrate processing equipment, semiconductor device manufacturing method and program |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177056A (en) * | 1992-12-09 | 1994-06-24 | Hitachi Ltd | Gas treatment device |
JP2007096189A (en) * | 2005-09-30 | 2007-04-12 | Epson Imaging Devices Corp | Method for managing plasma cvd device |
CN101044601A (en) * | 2004-08-06 | 2007-09-26 | 东京毅力科创株式会社 | Method and system for substrate temperature profile control |
US20100167424A1 (en) * | 2008-12-31 | 2010-07-01 | Texas Instruments Incorporated | Variable thickness single mask etch process |
CN102376541A (en) * | 2010-08-12 | 2012-03-14 | 上海华虹Nec电子有限公司 | Method for adjusting uniformity of critical dimensions in integrated circuit manufacture |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09171953A (en) * | 1995-12-20 | 1997-06-30 | Sony Corp | Heater and heating method for substrate, semiconductor integrated circuit device, photomask and liquid crystal display |
US20030000922A1 (en) * | 2001-06-27 | 2003-01-02 | Ramkumar Subramanian | Using scatterometry to develop real time etch image |
US6932871B2 (en) * | 2002-04-16 | 2005-08-23 | Applied Materials, Inc. | Multi-station deposition apparatus and method |
JP4791034B2 (en) * | 2004-12-28 | 2011-10-12 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
WO2006082730A1 (en) * | 2005-02-01 | 2006-08-10 | Tokyo Electron Limited | Semiconductor device manufacturing method and plasma oxidation method |
JP2009081420A (en) * | 2007-09-07 | 2009-04-16 | Nec Electronics Corp | Method of manufacturing semiconductor device |
JP2010258145A (en) * | 2009-04-23 | 2010-11-11 | Toshiba Corp | Method of manufacturing semiconductor device |
US20120074126A1 (en) * | 2010-03-26 | 2012-03-29 | Applied Materials, Inc. | Wafer profile modification through hot/cold temperature zones on pedestal for semiconductor manufacturing equipment |
-
2015
- 2015-02-23 JP JP2015032843A patent/JP6046757B2/en active Active
- 2015-03-13 CN CN201510111989.8A patent/CN106033735B/en active Active
- 2015-03-16 TW TW104108310A patent/TWI574311B/en active
- 2015-03-25 KR KR1020150041268A patent/KR101664153B1/en active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177056A (en) * | 1992-12-09 | 1994-06-24 | Hitachi Ltd | Gas treatment device |
CN101044601A (en) * | 2004-08-06 | 2007-09-26 | 东京毅力科创株式会社 | Method and system for substrate temperature profile control |
JP2007096189A (en) * | 2005-09-30 | 2007-04-12 | Epson Imaging Devices Corp | Method for managing plasma cvd device |
US20100167424A1 (en) * | 2008-12-31 | 2010-07-01 | Texas Instruments Incorporated | Variable thickness single mask etch process |
CN102376541A (en) * | 2010-08-12 | 2012-03-14 | 上海华虹Nec电子有限公司 | Method for adjusting uniformity of critical dimensions in integrated circuit manufacture |
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CN109216227A (en) * | 2017-06-30 | 2019-01-15 | 无尽电子有限公司 | Chip etching device and its application method |
CN111074242A (en) * | 2018-10-19 | 2020-04-28 | 长鑫存储技术有限公司 | Adjusting method of heating device, heating device and chemical vapor deposition equipment |
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TW201612961A (en) | 2016-04-01 |
KR101664153B1 (en) | 2016-10-10 |
KR20160038688A (en) | 2016-04-07 |
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JP6046757B2 (en) | 2016-12-21 |
CN106033735B (en) | 2019-01-18 |
JP2016072596A (en) | 2016-05-09 |
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