CN106033383A - Hard disk lamp signal control circuit - Google Patents
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- CN106033383A CN106033383A CN201510124490.0A CN201510124490A CN106033383A CN 106033383 A CN106033383 A CN 106033383A CN 201510124490 A CN201510124490 A CN 201510124490A CN 106033383 A CN106033383 A CN 106033383A
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Abstract
The invention provides a hard disk lamp signal control circuit suitable for receiving a status signal from a hard disk and generating a drive signal (according to the received signal) so as to control a LED to shine; the hard disk lamp signal control circuit comprises a first module and a second module; the first module comprises a timer and a multiplexer, wherein the timer receives the status signal and outputs a selection signal according to a logic value of the status signal; the multiplexer selects either the status signal or an indication logic reference voltage according to the selection signal, and outputs a control signal; the second module generates the drive signal according to the control signal; the hard disk lamp signal control circuit allows status signals from different hard disks and with different definitions to control the LED to shine, thus correctly indicating the hard disk status.
Description
Technical field
The invention relates to a kind of control circuit, particularly relate to the control circuit of a kind of hard disk cresset.
Background technology
Known computer system comprises a microprocessor, the hard disk (HDD) of this microprocessor of electrical connection and the light emitting diode (LED) of a green light.Whether whether this hard disk provide a status signal luminous and flash, to indicate the operating state of this hard disk to control this light emitting diode.This hard disk operation is in one first state (Present
State) and between one second state (Active State), when this first state, this hard disk with this microprocessor line, and this hard disk is in idle (Idle) state, this status signal from this hard disk is logical zero or logic 1, i.e. sends green light controlling this light emitting diode.When this second state, this hard disk with this microprocessor line, and this hard disk is in reading or write state, and this status signal from this hard disk beats between logical zero and logic 1, i.e. sends the green light of flicker controlling this light emitting diode.
Although this status signal meets sequence general service input/output (the Serial General at Serial Attached SCSI (SAS) HDD LED interface
Purpose Input/Output；SGPIO) specification, but reality is at different labels even in hard disk design with label different model, definition to this status signal but has significantly different, such as Seagate (Seagate) defines its hard disk produced when this first state, this status signal is logical zero, to control one first lumination of light emitting diode, when this second state, this status signal is beated between logical zero and logic 1, to control this first LED flash.Review Hitachi (Hitachi) and define its hard disk produced when this first state, this status signal is logic 1, to control one second lumination of light emitting diode, when this second state, this status signal is beated between logical zero and logic 1, to control this second LED flash.
Therefore, the light emitting diode of known computer system must use two kinds of designs for different labels or the hard disk of different model, for example, if designing the hard disk being used in Seagate to the second light emitting diode of the hard disk of Hitachi, due to the second light emitting diode of Hitachi's specification when the logic 1 just luminous, and when this first state, the hard disk institute output status signal of Seagate is logical zero, causes this second light emitting diode the most luminous and show mistake.The most such as this computer system is a server and when having multiple different label or the hard disk of different model and multiple light emitting diode, how to make such light emitting diode normal luminous to indicate respectively the state of such hard disk, and becoming is an important problem.
Summary of the invention
Therefore, the main object of the present invention, i.e. providing a kind of control circuit, with the status signal for the different definition described in prior art, lumination of light emitting diode can controlled, correctly to indicate the state of this hard disk.
Then, the control circuit of hard disk cresset of the present invention, it is adaptable to receive from the status signal of a hard disk, and produce a driving signal to control a lumination of light emitting diode according at least to this status signal, and comprise one first module and one second module.This first module includes a timer and a multiplexer.
This timer receives this status signal from this hard disk, and exports a selection signal.When this status signal is logic 1, this selection signal is logical zero, when this status signal is logical zero, and this timer counting starts, and this selection signal is logical zero, until a scheduled time, this selection signal becomes logic 1.
This multiplexer receives this status signal, the reference voltage of an instruction logic 1 and this selection signal, and exports a control signal.When this selection signal is logical zero, the logical value of this control signal is equal to this status signal, and when this selection signal is logic 1, the logical value of this control signal is equal to 1.
This second module receives this control signal, and according at least to this control signal, produces this driving signal.
Compared with prior art, the present invention utilizes the timer of first module of this control circuit to produce this selection signal, this multiplexer is this control signal further according to the one of which of this this status signal of selection signal behavior and logic 1, this second module produces this driving signal further according to this control signal, to control this lumination of light emitting diode, correctly to indicate the state of this hard disk.In other words, make when this status signal is maintained at logical zero or after logic 1 a period of time by this design, can correctly control this light emitting diode perseverance bright, and make, when this status signal alternate between logical zero and logic 1, can correctly control LED flash.
[accompanying drawing explanation]
Other the feature of the present invention and effect, will clearly present, wherein in reference to graphic embodiment:
Fig. 1 is a block chart, and an embodiment of the control circuit of hard disk cresset of the present invention is described.
Fig. 2 is a sequential chart, illustrates that a status signal and of the first aspect of the embodiment of the present invention drives the relation of signal.
Fig. 3 is a sequential chart, illustrates that a status signal and of the second aspect of the embodiment of the present invention drives the relation of signal.
Fig. 4 is a sequential chart, illustrates that a status signal and of the third aspect of the embodiment of the present invention drives the relation of signal.
Fig. 5 is a sequential chart, illustrates that a status signal and of the 4th kind of aspect of the embodiment of the present invention drives the relation of signal.
[detailed description of the invention]
Refering to Fig. 1, the embodiment of the control circuit of hard disk cresset of the present invention is applicable to one and comprises a hard disk 3, one microprocessor 4, one first light emitting diode 5, and one second computer system of light emitting diode 6, to receive a status signal RDY and a line signal PRES from this hard disk 3, and receive the off-lined signal Offline from this microprocessor 4 and rub-out signal Fault, and according to this status signal RDY, this line signal PRES, this off-lined signal Offline, and this rub-out signal Fault, produce an a driving signal Active and caution signals False, luminous to control this first light emitting diode 5 and this second light emitting diode 6 respectively.When this first light emitting diode 5 is luminous, produce green light, when this second light emitting diode 6 is luminous, produce red light.
In the present embodiment, this status signal RDY and this line signal PRES from this hard disk 3 meet Serial Attached
Sequence general service input/output (the Serial General Purpose Input/Output at SCSI (SAS) HDD LED interface；SGPIO) specification.But in other embodiments, it is possible to meet other similar specification or standards.
This hard disk 3 operates in one first state (Present State), one second state (Active State), a third state (Not
Present State), between one the 4th state (Fault State) and one the 5th state (Offline State).
When this first state, this hard disk 3 with this microprocessor 4 line, and this hard disk 3 is in idle (Idle) state, this line signal PRES from this hard disk 3 is logic 1, this status signal RDY from this hard disk 3 is logical zero or logic 1, and this rub-out signal Fault and this off-lined signal Offline from this microprocessor 4 are logical zero, now, this first light emitting diode 5 sends green light, and this second light emitting diode 6 is the most luminous.
When this second state, this hard disk 3 with this microprocessor 4 line, and this hard disk 3 is in reading or write state, this line signal PRES from this hard disk 3 is logic 1, this status signal RDY from this hard disk 3 beats between logical zero and logic 1, and this rub-out signal Fault and this off-lined signal Offline from this microprocessor 4 are logical zero, now, this the first light emitting diode 5 sends the green light of flicker, and this second light emitting diode 6 is the most luminous.
When this third state, this hard disk 3 and this non-line of microprocessor 4, this line signal PRES from this hard disk 3 is logical zero, and now, this first light emitting diode 5 and the second light emitting diode 6 are the most luminous.
When four states, this line signal PRES from this hard disk 3 is logic 1, and the logical value from this rub-out signal Fault of this microprocessor 4 is 1, and now, this first light emitting diode 5 is the most luminous, and this second light emitting diode 6 sends red light.
When five states, this line signal PRES from this hard disk 3 is logic 1, it is respectively 0 and 1 from this rub-out signal Fault of this microprocessor 4 and the logical value of this off-lined signal Offline, now, this first light emitting diode 5 is the most luminous, and this second light emitting diode 6 sends the red light of flicker.
This control circuit comprises one first module 1 and one second module 2.This first module 1 includes timer 11 and a multiplexer 12.This timer 11 receives this status signal RDY from this hard disk 3, and exports a selection signal.When this status signal RDY is logic 1, this selection signal is logical zero, and when this status signal RDY is logical zero, this timer 11 starts counting up, and this selection signal is logical zero, until a scheduled time, this selection signal becomes logic 1.In the present embodiment, this scheduled time is 500 milliseconds.
This multiplexer 12 receives this status signal RDY from this hard disk 3, the reference voltage of an instruction logic 1 and this selection signal, and exports a control signal.When this selection signal is logical zero, the logical value of this control signal is equal to this status signal RDY, and when this selection signal is logic 1, the logical value of this control signal is equal to 1.
This second module 2 receives this off-lined signal Offline from this microprocessor 4 and this rub-out signal Fault, and this line signal PRES from this hard disk 3.When this line signal PRES, this off-lined signal Offline and this rub-out signal Fault are respectively logic 1, logical zero and logical zero, the logical value of this driving signal Active is equal to this control signal, and otherwise, the logical value of this driving signal Active is 0.This second module 2 includes one first reverser 22,1 first and lock 24,1 second reverser 23,1 second and lock 25, the 3rd and lock 26 and a pattern generator (Pattern
Generator)21。
This first reverser 22 receives this rub-out signal Fault from this microprocessor 4, and after the logical value of this rub-out signal Fault is made inverse operation (NOT), produces an output signal.
This first and lock 24 receive this line signal PRES from this hard disk 3, and this output signal from this first reverser 22, and the logical value of this line signal PRES and this output signal is made and after computing (AND), produces an output signal.
This second reverser 23 receives this off-lined signal Offline from this microprocessor 4, and after the logical value of this off-lined signal Offline is made inverse operation (NOT), produces an output signal.
This second and lock 25 receive this from this first and this output signal of lock 24, and this output signal from this second reverser 23, and the logical value of this two output signal is made and after computing (AND), produces an output signal.
3rd and lock 26 receive from this second and this output signal of lock 25, and this control signal from this first module 1, and this output signal and this control signal are made and after computing (AND), produces this driving signal Active.
This pattern generator 21 receives this off-lined signal Offline from this microprocessor 4 and this rub-out signal Fault, and produces this caution signals False according to this to drive this second light emitting diode 6.When this rub-out signal Fault is logic 1, this caution signals False is logic 1, sends red light controlling this second light emitting diode 6.When this rub-out signal Fault is logical zero and this off-lined signal Offline is logic 1, this rub-out signal Fault is a pulse wave signal with a fixed cycle, sends the red light of flicker controlling this second light emitting diode 6.When this rub-out signal Fault is logical zero and this off-lined signal Offline is logical zero, this rub-out signal Fault is logical zero.
It is a sequential chart respectively refering to Fig. 1 to Fig. 5, Fig. 2 to Fig. 5, illustrates the status signal RDY of four kinds of aspects and four kinds of selection signals, control signals of correspondence and drive the relation between signal Active.Fig. 2 and Fig. 3 is that the first and the status signal RDY of the second aspect are described respectively, and its definition is the hard disk 3 produced such as Seagate, and this hard disk 3 is when this first state (Present State), and this status signal RDY is logical zero.Fig. 4 and Fig. 5 is the status signal RDY that third and fourth kind aspect is described respectively, and its definition is the hard disk 3 produced such as Hitachi, and this hard disk 3 is when this first state, and this status signal RDY is logic 1.Below for convenience of description for the sake of, assume that this off-lined signal Offline and this rub-out signal Fault from this microprocessor 4 are all logical zeros, line signal PRES from this hard disk 3 is logic 1, and before the instant, this status signal RDY that this hard disk 3 produces is the most stable, and be between logic 1 and logical zero and beat, and, this status signal RDY is logic 1 before moment t0 in a flash.
Refering to Fig. 1 and Fig. 2, it is assumed that the dutycycle of the pulse wave of produced this status signal RDY of the first hard disk 3 is 50%, and pulse bandwidth T2 is 650 milliseconds.Between moment t0 ~ t1, this hard disk 3 operates in this first state, when moment t0, this status signal RDY becomes logical zero, now, the timer 11 of first module 1 of this control circuit starts counting up, and this selection signal is logical zero, the logic of this control signal is equal to this status signal RDY, i.e. logical zero, the logic of this driving signal Active is equal to this control signal, i.e. logical zero.When moment t0+0.5, this selection signal of this timer 11 output becomes logic 1, and now, the logical value of this control signal becomes 1, and the logical value of this driving signal Active also becomes 1, sends green light controlling this first light emitting diode 5.
Between moment t1 ~ t5, this hard disk 3 operates in this second state, when moment t1, this status signal RDY becomes logic 1, and now, this selection signal is logical zero, this control signal and this driving signal Active are logic 1, send green light controlling this first light emitting diode 5.When moment t2, this status signal RDY becomes logical zero, this selection signal, this control signal and this driving signal Active are logical zero, the most luminous to control this first light emitting diode 5, until during moment t2+0.5, this selection signal, this control signal, this driving signal Active become logic 1, send green light controlling this first light emitting diode 5.
Between moment t3 ~ t5, the change of this driving signal Active and identical between moment t1 ~ t3, therefore, between moment t1 ~ t5, this first light emitting diode 5 is controlled by this driving signal Active, sends the green light of flicker.After moment t5, this hard disk 3 operates in this first state, and this driving signal Active is logic 1, sends green light controlling this first light emitting diode 5.
From the point of view of the explanation of the status signal RDY of the first aspect above-mentioned, for the specification of Seagate, when hard disk 3 is in this first state, this status signal RDY is logical zero, and this control signal and this driving signal Active are logic 1, make this first light emitting diode 5 send green light, when this second state, beating between logic 1 and logical zero of this status signal, and pulse bandwidth T2 is more than under conditions of this scheduled time T1, and this first light emitting diode 5 can be made to send the green light of flicker.
Refering to Fig. 1 and Fig. 3, it is assumed that the dutycycle of the pulse wave of produced this status signal RDY of the second hard disk 3 is 50%, and pulse bandwidth T3 is 325 milliseconds.Between moment t0 ~ t1, this hard disk 3 operates in this first state, when moment t0, this status signal RDY becomes logical zero, now, the timer 11 of first module 1 of this control circuit starts counting up, and this selection signal is logical zero, the logic of this control signal is equal to this status signal RDY, i.e. logical zero, the logic of this driving signal Active is equal to this control signal, i.e. logical zero.When moment t0+0.5, this selection signal of this timer 11 output becomes logic 1, and now, the logical value of this control signal becomes 1, and the logical value of this driving signal Active also becomes 1, sends green light controlling this first light emitting diode 5.
Between moment t1 ~ t7, this hard disk 3 operates in this second state, when moment t1, this status signal RDY becomes logic 1, and now, this selection signal is logical zero, this control signal and this driving signal Active are logic 1, send green light controlling this first light emitting diode 5.When moment t2, this status signal RDY becomes logical zero, and this selection signal, this control signal and this driving signal Active are logical zero, the most luminous to control this first light emitting diode 5.
Between moment t3 ~ t5 and t5 ~ 7, the change of this driving signal Active and identical between moment t1 ~ t3, therefore, between moment t1 ~ t7, this first light emitting diode 5 is controlled by this driving signal Active, sends the green light of flicker.After moment t7, this hard disk 3 operates in this first state, and this driving signal Active becomes logic 1 at moment t6+0.5, sends green light controlling this first light emitting diode 5.
From the point of view of explanation by the status signal RDY of above-mentioned the second aspect, for the specification of Seagate, when hard disk 3 is in this first state, this status signal RDY is logical zero, and this control signal and this driving signal Active are logic 1, make this first light emitting diode 5 send green light, when this second state, beating between logic 1 and logical zero of this status signal, and pulse bandwidth T3 is less than under conditions of this scheduled time T1, and this first light emitting diode 5 can be made to send the green light of flicker.
Refering to Fig. 1 and Fig. 4, it is assumed that the dutycycle of the pulse wave of produced this status signal RDY of the third hard disk 3 is 50%, and pulse bandwidth T2 is 650 milliseconds.Between moment t0 ~ t1, this hard disk 3 operates in this first state, when moment t0, this status signal RDY is logic 1, now, this selection signal of timer 11 output of first module 1 of this control circuit is logical zero, the logic of this control signal is equal to this status signal RDY, i.e. logic 1, and the logic of this driving signal Active is equal to this control signal, i.e. logic 1, sends green light controlling this first light emitting diode 5.
Between moment t1 ~ t5, this hard disk 3 operates in this second state, and when moment t1, this status signal RDY becomes logical zero, now, the timer 11 of first module 1 of this control circuit starts counting up, and this selection signal is logical zero, and the logic of this control signal is equal to this status signal RDY, i.e. logical zero, the logic of this driving signal Active is equal to this control signal, i.e. logical zero, the most luminous to control this first light emitting diode 5.When moment t1+0.5, this selection signal of this timer 11 output becomes logic 1, and now, the logical value of this control signal becomes 1, and the logical value of this driving signal Active also becomes 1, sends green light controlling this first light emitting diode 5.When moment t2, this status signal RDY becomes logic 1, and this selection signal, this control signal and this driving signal Active are logic 1, luminous to control this first light emitting diode 5.
Between moment t3 ~ t5, the change of this driving signal Active and identical between moment t1 ~ t3, therefore, between moment t1 ~ t5, this first light emitting diode 5 is controlled by this driving signal Active, sends the green light of flicker.After moment t5, this hard disk 3 operates in this first state, and this driving signal Active is logic 1, sends green light controlling this first light emitting diode 5.
From the point of view of the explanation of the status signal RDY of the third aspect above-mentioned, for the specification of Hitachi, when hard disk 3 is in this first state, this status signal RDY is logic 1, and this control signal and this driving signal Active are logic 1, make this first light emitting diode 5 send green light, when this second state, beating between logic 1 and logical zero of this status signal, and pulse bandwidth T2 is more than under conditions of this scheduled time T1, and this first light emitting diode 5 can be made to send the green light of flicker.
Refering to Fig. 1 and Fig. 5, it is assumed that the dutycycle of the pulse wave of the 4th kind of produced this status signal RDY of hard disk 3 is 50%, and pulse bandwidth T3 is 350 milliseconds.Between moment t0 ~ t1, this hard disk 3 operates in this first state, when moment t0, this status signal RDY is logic 1, now, this selection signal of timer 11 output of first module 1 of this control circuit is logical zero, the logic of this control signal is equal to this status signal RDY, i.e. logic 1, and the logic of this driving signal Active is equal to this control signal, i.e. logic 1, sends green light controlling this first light emitting diode 5.
Between moment t1 ~ t7, this hard disk 3 operates in this second state, and when moment t1, this status signal RDY becomes logical zero, now, the timer 11 of first module 1 of this control circuit starts counting up, and this selection signal is logical zero, and the logic of this control signal is equal to this status signal RDY, i.e. logical zero, the logic of this driving signal Active is equal to this control signal, i.e. logical zero, the most luminous to control this first light emitting diode 5.When moment t2, this status signal RDY becomes logic 1, and this selection signal, this control signal and this driving signal Active are logic 1, luminous to control this first light emitting diode 5.
Between moment t3 ~ t5 and t5 ~ t7, the change of this driving signal Active and identical between moment t1 ~ t3, therefore, between moment t1 ~ t7, this first light emitting diode 5 is controlled by this driving signal Active, sends the green light of flicker.After moment t7, this hard disk 3 operates in this first state, and this driving signal Active is logic 1, sends green light controlling this first light emitting diode 5.
From the point of view of explanation by the status signal RDY of above-mentioned 4th kind of aspect, for the specification of Hitachi, when hard disk 3 is in this first state, this status signal RDY is logic 1, and this control signal and this driving signal Active are logic 1, make this first light emitting diode 5 send green light, when this second state, beating between logic 1 and logical zero of this status signal, and pulse bandwidth T3 is less than under conditions of this scheduled time T1, and this first light emitting diode 5 can be made to send the green light of flicker.
What is particularly worth mentioning is that: after the timer 11 of first module 1 of this control circuit starts counting up, after this scheduled time, this selection signal exported can be become logic 1, in the present embodiment, this scheduled time is 500 milliseconds, and in other embodiments, this scheduled time is alternatively other value, the size of this scheduled time, as long as the flicker enabling the pulse bandwidth of this driving signal Active be enough to make human eye discover this first light emitting diode 5 changes.Additionally, by this first module 1 of this control circuit and the design of this second module 2, also it is avoided that this first light emitting diode 5 and the most luminous mistake generation of this second light emitting diode 6.It is to say, this control circuit has the mechanism of priority, it is used to refer to abnormality, the i.e. the 4th state (Fault
And this off-lined signal Fault of the 5th state (Offline State) and this rub-out signal Offline control this second light emitting diode 6 and send the priority of red light higher than instruction normal condition, i.e. this first state (Present State)
And this status signal RDY of this second state (Active State) controls this first light emitting diode 5 and sends green light State).Thus without the situation that this first light emitting diode 5 of generation and this second light emitting diode 6 are the most luminous, the user of this computer system is made can correctly to understand the operating state of hard disk.
In sum, whether such as Seagate or the specification of Hitachi, the various different definition having for this status signal, this selection signal can be produced by the timer 11 of first module 1 of this control circuit, this multiplexer 12 is this control signal further according to the one of which of this selection signal behavior this status signal RDY and logic 1, this second module 2 is further according to this control signal, this line signal PRES, this off-lined signal Offline, and this rub-out signal Fault, produce this driving signal Active, to control this two lumination of light emitting diode, correctly to indicate the state of this hard disk 3, therefore really can reach the purpose of the present invention.
Only as described above, it is only presently preferred embodiments of the present invention, the scope that can not limit present invention enforcement with this, the simple equivalence the most generally made according to the claims in the present invention and patent specification content changes and modifies, being all still covered by the present invention within the scope of the patent.
Claims (6)
1. the control circuit of a hard disk cresset, it is adaptable to reception one is from the status signal of a hard disk, and produces a driving signal to control a lumination of light emitting diode according at least to this status signal, it is characterised in that comprise:
One first module, including:
One timer, receive this status signal from this hard disk, and export a selection signal, when this status signal is logic 1, this selection signal is logical zero, when this status signal is logical zero, this timer counting starts, and this selection signal is logical zero, until a scheduled time, this selection signal becomes logic 1；And
One multiplexer, receives this status signal, the reference voltage of an instruction logic 1 and this selection signal, and exports a control signal, when this selection signal is logical zero, the logical value of this control signal is equal to this status signal, and when this selection signal is logic 1, the logical value of this control signal is equal to 1；And
One second module, receives this control signal, and according at least to this control signal, produces this driving signal.
2. the control circuit of hard disk cresset as claimed in claim 1, it is characterised in that this scheduled time is 500 milliseconds.
3. the control circuit of hard disk cresset as claimed in claim 1, it is characterized in that, this second module also receives the off-lined signal from a microprocessor and a rub-out signal, and the line signal from this hard disk, when this line signal, this off-lined signal and this rub-out signal are respectively logic 1, logical zero and logical zero, the logical value of this driving signal is equal to this control signal, and otherwise, the logical value of this driving signal is 0.
4. the control circuit of hard disk cresset as claimed in claim 3, it is characterised in that this second module includes:
One first reverser, receives this rub-out signal from this microprocessor, and produces an output signal；
One first and lock, receive this line signal from this hard disk, and this output signal from this first reverser, and produce an output signal；
One second reverser, receives this off-lined signal from this microprocessor, and produces an output signal；
One second and lock, receive this from this first and this output signal of lock, and this output signal from this second reverser, and produce an output signal；And
One the 3rd and lock, receive from this second and this output signal of lock, and this control signal from this first module, and produce this driving signal.
5. the control circuit of hard disk cresset as claimed in claim 4, it is characterized in that, this second module also includes a pattern generator, this pattern generator receives this off-lined signal from this microprocessor and this rub-out signal, and produce a caution signals to drive another lumination of light emitting diode, when this rub-out signal is logic 1, this caution signals is logic 1, when this rub-out signal is logical zero and this off-lined signal is logic 1, this rub-out signal is a pulse wave signal with a fixed cycle, when this rub-out signal is logical zero and this off-lined signal is logical zero, this rub-out signal is logical zero.
6. the control circuit of hard disk cresset as claimed in claim 5, it is characterised in that this scheduled time is 500 milliseconds.
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| CN108319540B (en) * | 2017-01-18 | 2020-08-11 | 佛山市顺德区顺达电脑厂有限公司 | Hard disk lamp signal control system |
| CN110321263A (en) * | 2018-03-29 | 2019-10-11 | 佛山市顺德区顺达电脑厂有限公司 | Hard disk monitoring system |
| CN109062773A (en) * | 2018-08-03 | 2018-12-21 | 联想(北京)有限公司 | A kind of information processing method and electronic equipment |
| CN112286855A (en) * | 2020-10-23 | 2021-01-29 | 苏州浪潮智能科技有限公司 | Adaptive SGPIO decoder realized through logic chip and program |
| CN112286855B (en) * | 2020-10-23 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Adaptive SGPIO decoder realized through logic chip and program |
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