CN106027047B - The Linearization Method of non-linear analog/digital conversion based on FPGA control - Google Patents
The Linearization Method of non-linear analog/digital conversion based on FPGA control Download PDFInfo
- Publication number
- CN106027047B CN106027047B CN201610330609.4A CN201610330609A CN106027047B CN 106027047 B CN106027047 B CN 106027047B CN 201610330609 A CN201610330609 A CN 201610330609A CN 106027047 B CN106027047 B CN 106027047B
- Authority
- CN
- China
- Prior art keywords
- data
- fpga
- averaging
- signal
- linearization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/0658—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by calculating a running average of a number of subsequent samples
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Complex Calculations (AREA)
Abstract
The invention discloses a kind of Linearization Methods of non-linear analog/digital conversion based on FPGA control, signal is converted by the finite states machine control A/D converter in FPGA, the transition status of A/D converter includes original state, converts starting state, converts judgement state, data output state；Data signal transmission after conversion to FPGA is carried out linearization process by A/D converter；Measurement is repeated several times, the data after obtained multiple groups linearization process are averaging；Data signal transmission after averaging to host computer is subjected to denoising.Data-signal is subjected to linearization process by FPGA, then averaging is taken multiple measurements to it, eliminate troublesome division calculation, the white noise being mixed in final removal signal, it is inputted to exclude to work as Nonlinear A/D in 0V or so with this, the data exception phenomenon occurred when A/D is exported and is averaging, to obtain stable data output.
Description
Technical field
The present invention relates to signal imitation fields, and more particularly, to thermopile detector is a kind of based on the non-of FPGA control
The Linearization Method of linear analog/digital conversion.
Background technique
Every field in modern production life generally requires to measure multiple signals, and the signal surveyed is mostly mould
Quasi- signal, it is necessary to A/D (analog/digital) conversion is first passed through, becomes digital signal and could be sent into computer to perform corresponding processing, thus
Realize the control to system, this process relates to the acquisition and processing of signal.Present FPGA (Field-
Programmable Gate Array: i.e. field programmable gate array) chip not only has very strong logic control ability, and
And there are also stronger digital signal processing capability, thus by FPGA be applied to Signal sampling and processing field have become from now on one
Kind development trend.Here for we are inputted using thermopile detector as A/D, to illustrate to control based on FPGA in the prior art
Nonlinear A/D processing method.
Here Nonlinear A/D chip model that we use is AD7691BRMZ, this is one 18 difference A/D conversions
Device, its output and input voltage corresponding relationship is as shown in table 1, and table 1 is input voltage and output relation table.
Table 1
It is used to most commonly seen in the process of processing to A/D acquisition data be exactly multiple measurement averaging in FPGA
Value, when the input voltage for entering A/D is greater than 38.15 μ V entirely or is less than -38.15 μ V entirely, the digital signal of output is for defeated
Entering voltage is linear relationship, and the data obtained after FPGA control is averaged are right value, but when input voltage is in 0V or so
When hovering, that is, within this period of averaging, had both there is positive voltage or negative voltage had occurred in input voltage, at this moment
It will be an exceptional value by the average value that FPGA control acquires.A simple case is lifted, when only measuring averaging twice,
Input voltage is+1 lowest effective value, and another secondary input voltage is -1 lowest effective value, at this moment corresponding output number
Word signal is respectively 0x00001 and 0x3FFFF, and being added the data after summation is averaged is 0x20000, and this A/D is digital
Signal exports corresponding input voltage and is but negative full scale, it is clear that this result is not right value.Thermopile detector is temperature sensitive type
Detector, when without the irradiation of extraneous incident light, since the presence of noise voltage makes its output voltage usually hover above or below 0V, institute
Under unglazed irradiation, often will appear after repeatedly measuring and averaging on the light power meter of thermopile detector type
The phenomenon that data exception.
Therefore, the prior art needs further improvement and develops.
Summary of the invention
In view of above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a kind of based on the non-linear of FPGA control
The Linearization Method of analog/digital conversion, to solve the technical issues of analog/digital exports the data exception occurred when averaging, into
And obtain stable data output.
In order to solve the above technical problems, the present invention program includes:
A kind of Linearization Method of the non-linear analog/digital conversion based on FPGA control comprising following steps:
A, signal is converted by the finite states machine control A/D converter in FPGA, the conversion of A/D converter
State includes original state, converts starting state, converts judgement state, data output state；
B, the data signal transmission after conversion to FPGA is carried out linearization process by A/D converter；
C, step A, step B is repeated several times, the data after obtained multiple groups linearization process are subjected to averaging processing；
D, the data signal transmission after averaging to host computer is subjected to denoising.
The Linearization Method, wherein the A/D converter in above-mentioned steps A is that 18 potential differences divide analog/digital to turn
Parallel operation.
The Linearization Method, wherein above-mentioned steps B is specific further include: take a data-signal progress high position
Inverse processing, at this time if establishing rectangular coordinate system, at this time using analog/digital input as horizontal axis, using outputting data signals as the longitudinal axis, whole
Linearisation is just presented in the input and output of analog/digital in a operating voltage range.
The Linearization Method, wherein above-mentioned steps C is specific further include: measurement 2nSecondary data are averaged,
Wherein n be positive integer, to the binary data sum after summation move to right n be averaged after data.
The Linearization Method, wherein above-mentioned steps D is specific further include: the data after will be average pass one by one
To host computer, host computer is first deposited after obtaining data, after waiting all test datas all to deposit, then to all registered datas
Wavelet Denoising Method processing is carried out, the white noise being mixed in signal is removed.
The Linearization Method of a kind of non-linear analog/digital conversion based on FPGA control provided by the invention, by data
Signal carries out linearization process by FPGA, and averaging is then taken multiple measurements to it, eliminates troublesome division calculation, most
The white noise being mixed in removal signal eventually is inputted in 0V or so with this to exclude to work as Nonlinear A/D, when being averaging to A/D output
The data exception phenomenon of appearance, to obtain stable data output.
Detailed description of the invention
Fig. 1 is A/D input/output relation figure in the prior art；
Fig. 2 is the A/D input/output relation figure that FPGA carries out after linear process in the present invention；
Fig. 3 is the schematic diagram for handling A/D signal in the prior art；
Fig. 4 is the schematic diagram using present invention processing A/D signal；
Fig. 5 is the flow diagram of Linearization Method in the present invention.
Specific embodiment
The present invention provides a kind of Linearization Methods of non-linear analog/digital conversion based on FPGA control, to make this
The purpose of invention, technical solution and effect are clearer, define, and the present invention is described in more detail below.It should be appreciated that this
Locate described specific embodiment to be only used to explain the present invention, be not intended to limit the present invention.
The present invention provides a kind of Linearization Methods of non-linear analog/digital conversion based on FPGA control comprising
Following steps:
Step 1 is converted signal by the finite states machine control A/D converter in FPGA, A/D converter
Transition status include original state, convert starting state, convert judgement state, data output state；
Data signal transmission after conversion to FPGA is carried out linearization process by step 2, A/D converter；
Step 3 is repeated several times Step 1: step 2, the data after obtained multiple groups linearization process are averaging
Processing；
Data signal transmission after averaging to host computer is carried out denoising by step 4.
Further, the A/D converter in above-mentioned steps one is 18 differentials.
Above-mentioned steps two are specific further include: a data-signal progress high position are negated processing, at this time if establishing right angle seat
Mark system, using analog/digital input as horizontal axis, using outputting data signals as the longitudinal axis, the input of analog/digital is defeated in entire operating voltage range
Linearisation is just presented out.
Above-mentioned steps three are specific further include: measurement 2nSecondary data are averaged, and wherein n is positive integer, after summation
Binary data sum move to right n be it is average after data.
Above-mentioned steps four are specific further include: the data after will be average are transmitted to host computer one by one, after host computer obtains data
It first deposits, after waiting all test datas all to deposit, then Wavelet Denoising Method processing is carried out to all registered datas, remove signal
In the white noise that is mixed with.
In order to which processing method of the invention is further described, it is exemplified below more detailed embodiment and is illustrated.With
18 differentials are illustrated for i.e. 18 AD7691BRMZ chips.As shown in Figure 5, specifically such as
Under:
Step (1): the shift control module of AD7691BRMZ is generated with finite state machine.It can be divided mainly into initial shape
State converts starting state, converts judgement state, data output state etc..
Step (2): after data-signal after FPGA obtains A/D conversion, linearization process is carried out to this data.Specifically
It is obtained A/D output signal to be forced plus 0x20000 into this example, i.e. highest order negates, at this time if establishing right angle seat
Mark system, using A/D input as horizontal axis, using outputting data signals as the longitudinal axis, the input and output of A/D are just in entire operating voltage range
Show linearisation, so that it may the data exception problem that occurs when subsequent 0V or so being avoided to be averaging, comparing result such as Fig. 1 with
It is shown in Fig. 2.
Step (3): averaging is repeatedly measured to high-order negated data.Here if there is no the case where particular/special requirement
Under, 2 can be measurednSecondary data are averaged, and wherein n is positive integer, move to right n to the binary data sum after summation in this way
It is the data after being averaged, eliminates troublesome division calculation.Here we are to every group 210A data are averaged, and are only needed
210A data summation, choosing sum [27 ... 10] this 18 bit is the data after being averaging.
Step (4): having asked average data to be transmitted to host computer and carried out denoising.Data after average are transmitted to one by one
Host computer, host computer obtain data after first deposit, after waiting all test datas all to deposit, then to all registered datas into
The processing of row Wavelet Denoising Method removes the white noise being mixed in signal, the data after final process and the number for not carrying out linearization process
As shown in Figure 3 and Figure 4 according to comparison.Obvious, by carrying out multiple phase again after being first added with 0x20000 to A/D output data
Add averaging to handle, the data jumping phenomenon of 0V or so can be inputted to avoid A/D in this way, to obtain stable data output.
Certainly, described above is only that presently preferred embodiments of the present invention is answered the present invention is not limited to enumerate above-described embodiment
When explanation, anyone skilled in the art is all equivalent substitutes for being made, bright under the introduction of this specification
Aobvious variant, all falls within the essential scope of this specification, ought to be by protection of the invention.
Claims (4)
1. a kind of Linearization Method of the non-linear analog/digital conversion based on FPGA control comprising following steps:
A, signal is converted by the finite states machine control A/D converter in FPGA, the transition status of A/D converter
Including original state, converts starting state, converts judgement state, data output state；
B, the data signal transmission after conversion to FPGA is carried out linearization process by A/D converter；
C, step A, step B is repeated several times, the data after obtained multiple groups linearization process are subjected to averaging processing；
D, the data signal transmission after averaging to host computer is subjected to denoising；
Above-mentioned steps B is specific further include: a data-signal progress high position is negated into processing, at this time if establishing rectangular coordinate system,
Then using analog/digital input as horizontal axis, using outputting data signals as the longitudinal axis, the input and output of analog/digital in entire operating voltage range
It is linearized with regard to presenting.
2. Linearization Method according to claim 1, which is characterized in that the A/D converter in above-mentioned steps A is
18 differentials.
3. Linearization Method according to claim 1, which is characterized in that above-mentioned steps C is specific further include: measurement
2nSecondary data are averaged, wherein n be positive integer, to the binary data sum after summation move to right n be averaged after number
According to.
4. Linearization Method according to claim 1, which is characterized in that above-mentioned steps D is specific further include: will put down
Data after are transmitted to host computer one by one, and host computer is first deposited after obtaining data, after waiting all test datas all to deposit, then
Wavelet Denoising Method processing is carried out to all registered datas, removes the white noise being mixed in signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610330609.4A CN106027047B (en) | 2016-05-18 | 2016-05-18 | The Linearization Method of non-linear analog/digital conversion based on FPGA control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610330609.4A CN106027047B (en) | 2016-05-18 | 2016-05-18 | The Linearization Method of non-linear analog/digital conversion based on FPGA control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106027047A CN106027047A (en) | 2016-10-12 |
| CN106027047B true CN106027047B (en) | 2019-01-22 |
Family
ID=57098430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610330609.4A Active CN106027047B (en) | 2016-05-18 | 2016-05-18 | The Linearization Method of non-linear analog/digital conversion based on FPGA control |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106027047B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1985442A (en) * | 2004-03-25 | 2007-06-20 | 奥普蒂科伦公司 | Digital linearizing system |
| CN102045078A (en) * | 2010-12-01 | 2011-05-04 | 东南大学 | FPGA (Field Programmable Gate Array) based software receiver system and implementation method |
| CN102291580A (en) * | 2011-07-28 | 2011-12-21 | 南京联慧通信技术有限公司 | Video transmission method based on Android system |
| CN102413320A (en) * | 2011-12-21 | 2012-04-11 | 上海大学 | Method for realizing wireless network intelligent video monitoring system |
| CN102938638A (en) * | 2012-10-26 | 2013-02-20 | 宁波大学 | Cross coupling modeling method of concurrency multiband nonlinear system and linear device |
| CN103442204A (en) * | 2013-08-08 | 2013-12-11 | 浙江工业大学 | Network video transmission system and method based on DM365 |
| CN104252550A (en) * | 2013-06-27 | 2014-12-31 | 中国矿业大学 | High-performance real-time simulation method based on FPGA (field programmable gate array) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070058376A (en) * | 2004-03-25 | 2007-06-08 | 옵티크론, 인코포레이티드. | Reduced complexity nonlinear filters for analog-to-digital converter linearization |
-
2016
- 2016-05-18 CN CN201610330609.4A patent/CN106027047B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1985442A (en) * | 2004-03-25 | 2007-06-20 | 奥普蒂科伦公司 | Digital linearizing system |
| CN102045078A (en) * | 2010-12-01 | 2011-05-04 | 东南大学 | FPGA (Field Programmable Gate Array) based software receiver system and implementation method |
| CN102291580A (en) * | 2011-07-28 | 2011-12-21 | 南京联慧通信技术有限公司 | Video transmission method based on Android system |
| CN102413320A (en) * | 2011-12-21 | 2012-04-11 | 上海大学 | Method for realizing wireless network intelligent video monitoring system |
| CN102938638A (en) * | 2012-10-26 | 2013-02-20 | 宁波大学 | Cross coupling modeling method of concurrency multiband nonlinear system and linear device |
| CN104252550A (en) * | 2013-06-27 | 2014-12-31 | 中国矿业大学 | High-performance real-time simulation method based on FPGA (field programmable gate array) |
| CN103442204A (en) * | 2013-08-08 | 2013-12-11 | 浙江工业大学 | Network video transmission system and method based on DM365 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106027047A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102938647B (en) | Change-over circuit and chip | |
| CN108107394B (en) | Method and system for detecting flatness and consistency of bandwidth of multi-channel digital oscilloscope | |
| CN102684696B (en) | The testing apparatus of A/D converter and method of testing | |
| Ghavoronkova et al. | THE REVIEW OF MODERN SYSTEMS OF DATA GATHERING | |
| CN106027047B (en) | The Linearization Method of non-linear analog/digital conversion based on FPGA control | |
| CN106603074A (en) | DAC circuit parallel testing system and parallel testing method | |
| CN110186962B (en) | Incomplete measurement data imaging method for capacitance tomography | |
| CN104614659A (en) | Automatic test system and automatic test method | |
| CN110412644A (en) | Photoncounting methods and device | |
| CN201796119U (en) | Programmable digital integrated circuit alternating-current parameter testing system | |
| CN103093078A (en) | Data inspection method for improved 53H algorithm | |
| CN106446913A (en) | Pointer position extracting method of multi-dial pointer type instrument | |
| CN105223495A (en) | A kind of method of testing of the Analog-digital circuit fault diagnosis based on expert system | |
| CN105739338A (en) | Integrated circuit bypass signal difference amplification sampling system and acquisition method | |
| US10181858B1 (en) | Auto-zero algorithm for reducing measurement noise in analog-to-digital systems over a wide range of sampling rates | |
| CN103941105B (en) | Time-Series analysis device and Time Series Analysis Method | |
| CN110568268A (en) | Electric field intensity test system of electric and magnetic field set based on MEMS technology | |
| CN113701923A (en) | Method, device, terminal and medium for acquiring characteristic curve | |
| CN106709099B (en) | MAP file conversion method for probe station | |
| CN1971530A (en) | Digital temperature sensing system | |
| Maier et al. | Package ‘redas’ | |
| CN104155592B (en) | Test method of DDS dedicated chip static parameter | |
| CN103983871B (en) | A kind of VXI module tester based on FPGA | |
| CN214669453U (en) | Data conversion device verification circuit | |
| CN204101503U (en) | The splicing of magnetic grid guide rail and total length fault locator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |